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kdv |
/*
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* motcomp_dcttype.v
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*
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* Copyright (c) 2007 Koen De Vleeschauwer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* motcomp_dcttype - Motion compensation dct type
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*/
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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`undef CHECK
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`ifdef __IVERILOG__
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`define CHECK 1
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`endif
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/*
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This module converts blocks between different dct types.
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dct_type is a flag indicating whether the macroblock is frame DCT coded or field DCT coded. If this is set to '1', the macroblock is field DCT coded. (par. 6.3.17.1 Macroblock modes)
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See par. 6.1.4, Figure 6-13 and 6-14.
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*/
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module motcomp_dcttype (
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clk, clk_en, rst,
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dct_block_empty, dct_block_cmd, dct_block_en, dct_block_valid,
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idct_rd_dta_empty, idct_rd_dta, idct_rd_dta_en, idct_rd_dta_valid,
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frame_idct_rd_dta_empty, frame_idct_rd_dta, frame_idct_rd_dta_en, frame_idct_rd_dta_valid,
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frame_idct_wr_overflow
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);
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`include "motcomp_dctcodes.v"
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input clk; // clock
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input clk_en; // clock enable
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input rst; // synchronous active low reset
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/* input dct field->frame conversion commands */
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input dct_block_empty; // asserted if no dct_block_type/dct_block_count available.
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input [2:0]dct_block_cmd; // code which indicates number of blocks to transpose and how to transpose them.
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output reg dct_block_en; // assert to read dct_block_type and dct_block_count.
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input dct_block_valid; // asserted if dct_block_type/dct_block_count valid
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/* input field/frame idct coefficients fifo */
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input idct_rd_dta_empty;
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input [71:0]idct_rd_dta;
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output reg idct_rd_dta_en;
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input idct_rd_dta_valid;
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/* output frame idct coefficients fifo */
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output frame_idct_rd_dta_empty;
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output [71:0]frame_idct_rd_dta;
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input frame_idct_rd_dta_en;
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output frame_idct_rd_dta_valid;
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wire frame_idct_wr_dta_full;
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wire frame_idct_wr_dta_almost_full;
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wire [71:0]frame_idct_wr_dta;
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reg frame_idct_wr_dta_en;
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reg frame_idct_wr_dta_en_0;
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output frame_idct_wr_overflow;
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/* ram address register */
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reg [4:0]wr_addr;
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reg [4:0]coeff;
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reg [4:0]dct_count;
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reg [2:0]dct_cmd;
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parameter [2:0]
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STATE_INIT = 3'd0,
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STATE_DCT_RD_EN = 3'd1,
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STATE_DCT_READ = 3'd2,
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STATE_WAIT_IDCT = 3'd3,
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STATE_IDCT_RD_EN = 3'd4,
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STATE_READ_IDCT = 3'd5,
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STATE_WRITE_IDCT = 3'd6,
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STATE_WAIT_WRITE = 3'd7;
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reg [2:0]state;
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reg [2:0]next;
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/* next state logic */
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always @*
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case (state)
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STATE_INIT: if (dct_block_empty || frame_idct_wr_dta_almost_full) next = STATE_INIT; // wait for dct_type fifo (=command input) not empty and frame_idct (=output) not full
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else next = STATE_DCT_RD_EN;
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STATE_DCT_RD_EN: next = STATE_DCT_READ; // assert dct_block_en
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STATE_DCT_READ: next = STATE_WAIT_IDCT; // read dct_block_cmd
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STATE_WAIT_IDCT: if (idct_rd_dta_empty) next = STATE_WAIT_IDCT; // wait for idct fifo not empty
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else next = STATE_IDCT_RD_EN;
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STATE_IDCT_RD_EN: next = STATE_READ_IDCT; // assert idct_rd_dta_en
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STATE_READ_IDCT: if (wr_addr == dct_count) next = STATE_WRITE_IDCT; // read idct_rd_dta; if last idct coefficient write re-arranged coefficients to frame idct fifo,
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else next = STATE_WAIT_IDCT; // else read next idct coefficient
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STATE_WRITE_IDCT: if (coeff == dct_count) next = STATE_WAIT_WRITE; // write idct coefficients to frame idct fifo
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else next = STATE_WRITE_IDCT;
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STATE_WAIT_WRITE: if (frame_idct_wr_dta_en) next = STATE_WAIT_WRITE;
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else next = STATE_INIT;
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default next = STATE_INIT;
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endcase
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/* state */
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always @(posedge clk)
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if (~rst) state <= STATE_INIT;
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else if (clk_en) state <= next;
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else state <= state;
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/* registers */
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/* read from dct_type fifo */
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always @(posedge clk)
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if (~rst) dct_block_en <= 1'b0;
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else if (clk_en) dct_block_en <= next == STATE_DCT_RD_EN;
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else dct_block_en <= 1'b0;
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always @(posedge clk)
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if (~rst) dct_cmd <= 1'b0;
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else if (clk_en && dct_block_valid) dct_cmd <= dct_block_cmd;
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else dct_cmd <= dct_cmd;
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always @(posedge clk)
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if (~rst) dct_count <= 5'b0;
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else if (clk_en && dct_block_valid)
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case (dct_block_cmd)
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DCT_C1_PASS,
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DCT_C1_FRAME_TO_TOP_FIELD: dct_count <= 5'd7; // 1 block, 8 rows
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DCT_L4_PASS,
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DCT_L4_TOP_FIELD_TO_FRAME,
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DCT_L4_FRAME_TO_TOP_FIELD: dct_count <= 5'd31; // 4 blocks, 32 rows
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default dct_count <= 5'd0; // Should never occur
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endcase
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else dct_count <= dct_count;
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/* read from idct_dta fifo */
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always @(posedge clk)
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if (~rst) idct_rd_dta_en <= 1'b0;
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else if (clk_en) idct_rd_dta_en <= next == STATE_IDCT_RD_EN;
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else idct_rd_dta_en <= 1'b0;
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always @(posedge clk)
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if (~rst) wr_addr <= 5'b0;
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else if (clk_en && (state == STATE_INIT)) wr_addr <= 5'b0;
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else if (clk_en && (state == STATE_READ_IDCT)) wr_addr <= wr_addr + 5'b1;
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else wr_addr <= wr_addr;
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always @(posedge clk)
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if (~rst) coeff <= 5'b0;
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else if (clk_en && (state == STATE_INIT)) coeff <= 5'b0;
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else if (clk_en && (state == STATE_WRITE_IDCT)) coeff <= coeff + 5'b1;
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else coeff <= coeff;
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/* write to idct_dta_ram */
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wire idct_ram_wr_en = idct_rd_dta_valid;
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wire [71:0]idct_ram_wr_dta = idct_rd_dta;
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/* write to frame_idct fifo */
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always @(posedge clk)
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if (~rst) frame_idct_wr_dta_en_0 <= 1'b0;
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else if (clk_en) frame_idct_wr_dta_en_0 <= (state == STATE_WRITE_IDCT);
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else frame_idct_wr_dta_en_0 <= 1'b0;
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always @(posedge clk)
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if (~rst) frame_idct_wr_dta_en <= 1'b0;
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else if (clk_en) frame_idct_wr_dta_en <= frame_idct_wr_dta_en_0;
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else frame_idct_wr_dta_en <= 1'b0;
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/* address transposition for reading */
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reg [4:0]rd_addr;
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reg idct_ram_rd_en;
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always @(posedge clk)
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if (~rst) idct_ram_rd_en <= 1'b0;
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else if (clk_en) idct_ram_rd_en <= (state == STATE_WRITE_IDCT);
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else idct_ram_rd_en <= 1'b0;
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/* convert address from field to frame coding, or the other way round */
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always @(posedge clk)
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case (dct_cmd)
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/* chrominance pass-through */
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DCT_C1_PASS:
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rd_addr <= coeff;
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/* rearrange chrominance from frame to field. output top 4 rows are top field, bottom 4 rows are bottom field */
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DCT_C1_FRAME_TO_TOP_FIELD:
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case (coeff)
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5'd0: rd_addr <= 5'd0;
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5'd1: rd_addr <= 5'd2;
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5'd2: rd_addr <= 5'd4;
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5'd3: rd_addr <= 5'd6;
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5'd4: rd_addr <= 5'd1;
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5'd5: rd_addr <= 5'd3;
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5'd6: rd_addr <= 5'd5;
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5'd7: rd_addr <= 5'd7;
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default rd_addr <= 5'd0;
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endcase
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/* luminance pass-through */
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DCT_L4_PASS:
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rd_addr <= coeff;
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/* rearrange luminance from field to frame. input top 8 rows are top field, bottom 8 rows are bottom field */
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DCT_L4_TOP_FIELD_TO_FRAME:
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case (coeff)
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5'd0: rd_addr <= 5'd0;
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5'd1: rd_addr <= 5'd16;
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5'd2: rd_addr <= 5'd1;
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5'd3: rd_addr <= 5'd17;
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5'd4: rd_addr <= 5'd2;
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5'd5: rd_addr <= 5'd18;
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5'd6: rd_addr <= 5'd3;
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5'd7: rd_addr <= 5'd19;
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5'd8: rd_addr <= 5'd8;
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5'd9: rd_addr <= 5'd24;
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5'd10: rd_addr <= 5'd9;
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5'd11: rd_addr <= 5'd25;
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5'd12: rd_addr <= 5'd10;
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5'd13: rd_addr <= 5'd26;
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5'd14: rd_addr <= 5'd11;
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5'd15: rd_addr <= 5'd27;
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5'd16: rd_addr <= 5'd4;
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5'd17: rd_addr <= 5'd20;
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5'd18: rd_addr <= 5'd5;
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5'd19: rd_addr <= 5'd21;
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5'd20: rd_addr <= 5'd6;
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5'd21: rd_addr <= 5'd22;
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5'd22: rd_addr <= 5'd7;
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5'd23: rd_addr <= 5'd23;
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5'd24: rd_addr <= 5'd12;
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5'd25: rd_addr <= 5'd28;
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5'd26: rd_addr <= 5'd13;
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5'd27: rd_addr <= 5'd29;
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5'd28: rd_addr <= 5'd14;
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5'd29: rd_addr <= 5'd30;
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5'd30: rd_addr <= 5'd15;
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5'd31: rd_addr <= 5'd31;
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default rd_addr <= 5'd0;
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endcase
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/* rearrange luminance from frame to field. output top 8 rows are top field, bottom 8 rows are bottom field */
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DCT_L4_FRAME_TO_TOP_FIELD:
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case (coeff)
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5'd0: rd_addr <= 5'd0;
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5'd1: rd_addr <= 5'd2;
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5'd2: rd_addr <= 5'd4;
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5'd3: rd_addr <= 5'd6;
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5'd4: rd_addr <= 5'd16;
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5'd5: rd_addr <= 5'd18;
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5'd6: rd_addr <= 5'd20;
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5'd7: rd_addr <= 5'd22;
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5'd8: rd_addr <= 5'd8;
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5'd9: rd_addr <= 5'd10;
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5'd10: rd_addr <= 5'd12;
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5'd11: rd_addr <= 5'd14;
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5'd12: rd_addr <= 5'd24;
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5'd13: rd_addr <= 5'd26;
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5'd14: rd_addr <= 5'd28;
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5'd15: rd_addr <= 5'd30;
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5'd16: rd_addr <= 5'd1;
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5'd17: rd_addr <= 5'd3;
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5'd18: rd_addr <= 5'd5;
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5'd19: rd_addr <= 5'd7;
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5'd20: rd_addr <= 5'd17;
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5'd21: rd_addr <= 5'd19;
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5'd22: rd_addr <= 5'd21;
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5'd23: rd_addr <= 5'd23;
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5'd24: rd_addr <= 5'd9;
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5'd25: rd_addr <= 5'd11;
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5'd26: rd_addr <= 5'd13;
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5'd27: rd_addr <= 5'd15;
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5'd28: rd_addr <= 5'd25;
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5'd29: rd_addr <= 5'd27;
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5'd30: rd_addr <= 5'd29;
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5'd31: rd_addr <= 5'd31;
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default rd_addr <= 5'd0;
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endcase
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default
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rd_addr <= 5'd0;
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endcase
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/* storage for re-ordering idct coefficients */
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299 |
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dpram_sc
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#(.addr_width(5), // number of bits in address bus
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.dta_width(72)) // number of bits in data bus
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idct_dta_ram (
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.rst(rst), // reset, active low
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.clk(clk), // clock, rising edge trigger
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.wr_en(idct_ram_wr_en), // write enable, active high
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.wr_addr(wr_addr), // write address
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.din(idct_ram_wr_dta), // data input
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309 |
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.rd_en(idct_ram_rd_en), // read enable, active high
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310 |
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.rd_addr(rd_addr), // read address
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311 |
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.dout(frame_idct_wr_dta) // data output
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312 |
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);
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313 |
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314 |
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/* output fifo for idct coefficients */
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315 |
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316 |
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fifo_sc
|
317 |
|
|
#(.addr_width(9'd6), // stores twice 4 blocks
|
318 |
|
|
.dta_width(9'd72),
|
319 |
|
|
.prog_thresh(9'd32)) // almost_full low indicates enough room for writing 4 blocks
|
320 |
|
|
frame_idct_fifo (
|
321 |
|
|
.rst(rst),
|
322 |
|
|
.clk(clk),
|
323 |
|
|
.din(frame_idct_wr_dta),
|
324 |
|
|
.wr_en(frame_idct_wr_dta_en && clk_en),
|
325 |
|
|
.full(frame_idct_wr_dta_full),
|
326 |
|
|
.wr_ack(),
|
327 |
|
|
.overflow(frame_idct_wr_overflow),
|
328 |
|
|
.prog_full(frame_idct_wr_dta_almost_full),
|
329 |
|
|
.dout(frame_idct_rd_dta),
|
330 |
|
|
.rd_en(frame_idct_rd_dta_en),
|
331 |
|
|
.empty(frame_idct_rd_dta_empty),
|
332 |
|
|
.valid(frame_idct_rd_dta_valid),
|
333 |
|
|
.underflow(),
|
334 |
|
|
.prog_empty()
|
335 |
|
|
);
|
336 |
|
|
|
337 |
|
|
`ifdef CHECK
|
338 |
|
|
always @(posedge clk)
|
339 |
|
|
if (frame_idct_wr_overflow)
|
340 |
|
|
begin
|
341 |
|
|
#0 $display("%m\t*** error: frame_idct_fifo overflow. **");
|
342 |
|
|
$stop;
|
343 |
|
|
end
|
344 |
|
|
`endif
|
345 |
|
|
|
346 |
|
|
`ifdef DEBUG
|
347 |
|
|
/* debugging */
|
348 |
|
|
|
349 |
|
|
always @(posedge clk)
|
350 |
|
|
if (clk_en)
|
351 |
|
|
case (state)
|
352 |
|
|
STATE_INIT: #0 $display("%m STATE_INIT");
|
353 |
|
|
STATE_DCT_RD_EN: #0 $display("%m STATE_DCT_RD_EN");
|
354 |
|
|
STATE_DCT_READ: #0 $display("%m STATE_DCT_READ");
|
355 |
|
|
STATE_WAIT_IDCT: #0 $display("%m STATE_WAIT_IDCT");
|
356 |
|
|
STATE_IDCT_RD_EN: #0 $display("%m STATE_IDCT_RD_EN");
|
357 |
|
|
STATE_READ_IDCT: #0 $display("%m STATE_READ_IDCT");
|
358 |
|
|
STATE_WRITE_IDCT: #0 $display("%m STATE_WRITE_IDCT");
|
359 |
|
|
STATE_WAIT_WRITE: #0 $display("%m STATE_WAIT_WRITE");
|
360 |
|
|
default #0 $display("%m *** Error: unknown state %d", state);
|
361 |
|
|
endcase
|
362 |
|
|
|
363 |
|
|
always @(posedge clk)
|
364 |
|
|
if (clk_en)
|
365 |
|
|
begin
|
366 |
|
|
$strobe("%m\tdct_block_empty: %d dct_block_cmd: %d dct_block_en: %d dct_block_valid: %d", dct_block_empty, dct_block_cmd, dct_block_en, dct_block_valid);
|
367 |
|
|
$strobe("%m\tidct_rd_dta_empty: %d idct_rd_dta: %h idct_rd_dta_en: %d idct_rd_dta_valid: %d wr_addr: %d", idct_rd_dta_empty, idct_rd_dta, idct_rd_dta_en, idct_rd_dta_valid, wr_addr);
|
368 |
|
|
$strobe("%m\tframe_idct_wr_dta_almost_full: %d frame_idct_wr_dta: %h frame_idct_wr_dta_en: %d rd_addr: %d", frame_idct_wr_dta_almost_full, frame_idct_wr_dta, frame_idct_wr_dta_en, rd_addr);
|
369 |
|
|
$strobe("%m\tframe_idct_rd_dta_empty: %d frame_idct_rd_dta: %h frame_idct_rd_dta_en: %d frame_idct_rd_dta_valid: %d", frame_idct_rd_dta_empty, frame_idct_rd_dta, frame_idct_rd_dta_en, frame_idct_rd_dta_valid);
|
370 |
|
|
end
|
371 |
|
|
|
372 |
|
|
`endif
|
373 |
|
|
|
374 |
|
|
endmodule
|
375 |
|
|
/* not truncated */
|