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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [mpeg2video.v] - Blame information for rev 2

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/*
2
 * mpeg2video.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 *
21
 * MPEG-2 License Notice
22
 *
23
 * Commercial implementations of MPEG-1 and MPEG-2 video, including shareware,
24
 * are subject to royalty fees to patent holders.  Many of these patents are
25
 * general enough such that they are unavoidable regardless of implementation
26
 * design.
27
 *
28
 * "MPEG-2 INTERMEDIATE PRODUCT. USE OF THIS PRODUCT IN ANY MANNER THAT COMPLIES
29
 * WITH THE MPEG-2 STANDARD IS EXPRESSLY PROHIBITED WITHOUT A LICENSE UNDER
30
 * APPLICABLE PATENTS IN THE MPEG-2 PATENT PORTFOLIO, WHICH LICENSE IS AVAILABLE
31
 * FROM MPEG LA, L.L.C., 250 STELLE STREET, SUITE 300, DENVER, COLORADO 80206."
32
 *
33
 */
34
 
35
/*
36
 * mpeg2 decoder.
37
 *
38
 * Input:
39
 *   stream_data:  video elementary stream
40
 * Output:
41
 *   r, g, b, pixel_en, h_sync, v_sync: rgb values and video synchronisation
42
 */
43
 
44
`include "timescale.v"
45
 
46
`undef CHECK
47
`ifdef __IVERILOG__
48
`define CHECK 1
49
`endif
50
 
51
module mpeg2video(clk, mem_clk, dot_clk,
52
             rst,                                                                                                                 // clocked with clk
53
             stream_data, stream_valid,                                                                                           // clocked with clk
54
             reg_addr, reg_wr_en, reg_dta_in, reg_rd_en, reg_dta_out,                                                             // clocked with clk
55
             busy, error, interrupt, watchdog_rst,                                                                                // clocked with clk
56
             r, g, b, y, u, v, pixel_en, h_sync, v_sync, c_sync,                                                                  // clocked with dot_clk
57
             mem_req_rd_cmd, mem_req_rd_addr, mem_req_rd_dta, mem_req_rd_en, mem_req_rd_valid,                                    // clocked with mem_clk
58
             mem_res_wr_dta, mem_res_wr_en, mem_res_wr_almost_full,                                                               // clocked with mem_clk
59
             testpoint_dip, testpoint_dip_en, testpoint
60
             );
61
 
62
  input            clk;                     // clock. Typically a multiple of 27 Mhz as MPEG2 timestamps have a 27 Mhz resolution.
63
  input            mem_clk;                 // memory clock. Typically 133-166 MHz.
64
  input            dot_clk;                 // video clock. Typically between 25 and 75 Mhz, depending upon MPEG2 resolution and frame rate.
65
 
66
  input            rst;                     // active low reset. Internally synchronized.
67
 
68
  /* MPEG stream input */
69
  input       [7:0]stream_data;             // packetized elementary stream input
70
  input            stream_valid;            // stream_data valid
71
 
72
  /* RGB output */
73
  output      [7:0]r;                       // red component
74
  output      [7:0]g;                       // green component
75
  output      [7:0]b;                       // blue component
76
  output      [7:0]y;                       // luminance 
77
  output      [7:0]u;                       // chrominance
78
  output      [7:0]v;                       // chrominance
79
  output           pixel_en;                // pixel enable - asserted if r, g and b valid.
80
  output           h_sync;                  // horizontal synchronisation
81
  output           v_sync;                  // vertical synchronisation
82
  output           c_sync;                  // composite synchronisation
83
 
84
  /* register file access */
85
  input       [3:0]reg_addr;
86
  input      [31:0]reg_dta_in;
87
  input            reg_wr_en;
88
  output     [31:0]reg_dta_out;
89
  input            reg_rd_en;
90
 
91
  output reg       busy;                    // assert busy when input fifo risks overflow
92
  output           error;
93
  output           interrupt;               // asserted when image size changes, or when vld error occurs. cleared when status register read.
94
 
95
  /* memory controller interface */
96
  output      [1:0]mem_req_rd_cmd;
97
  output     [21:0]mem_req_rd_addr;
98
  output     [63:0]mem_req_rd_dta;
99
  input            mem_req_rd_en;
100
  output           mem_req_rd_valid;
101
  input      [63:0]mem_res_wr_dta;
102
  input            mem_res_wr_en;
103
  output           mem_res_wr_almost_full;
104
  wire             mem_res_wr_full;
105
 
106
  /* logical analyzer test point */
107
  input       [3:0]testpoint_dip;
108
  input            testpoint_dip_en;
109
  output     [33:0]testpoint;
110
  wire        [3:0]testpoint_regfile;
111
 
112
  /* reset signals */
113
  wire             sync_rst;                // reset, either from rst input pin or watchdog, synchronized to clk
114
  wire             mem_rst;                 // reset, either from rst input pin or watchdog, synchronized to mem_clk
115
  wire             dot_rst;                 // reset, either from rst input pin or watchdog, synchronized to dot_clk
116
  wire             hard_rst;                // reset, only from rst input, synchronized to clk
117
 
118
  /* watchdog timer */
119
  output           watchdog_rst;            // low when watchdog timer expires.
120
  wire        [7:0]watchdog_interval;       // new value of the watchdog interval. 255 = never expire; 0 = expire immediate. 
121
  wire             watchdog_interval_wr;    // asserted when the watchdog interval is written 
122
  wire             watchdog_status_rd;      // asserted when the watchdog status is read 
123
  wire             watchdog_status;         // high if watchdog timer has expired
124
 
125
  /* vbuf_write - vbw fifo interface */
126
  wire  [63:0]vbw_wr_dta;
127
  wire        vbw_wr_en;
128
  wire        vbw_wr_full;
129
  wire        vbw_wr_almost_full;
130
 
131
  /* vbw fifo - framestore interface */
132
  wire  [63:0]vbw_rd_dta;
133
  wire        vbw_rd_en;
134
  wire        vbw_rd_valid;
135
  wire        vbw_rd_empty;
136
  wire        vbw_rd_almost_empty;
137
 
138
  /* framestore - vbr fifo interface */
139
  wire  [63:0]vbr_wr_dta;
140
  wire        vbr_wr_en;
141
  wire        vbr_wr_ack;
142
  wire        vbr_wr_full;
143
  wire        vbr_wr_almost_full;
144
 
145
  /* vbr fifo - getbits fifo interface */
146
  wire  [63:0]vbr_rd_dta;
147
  wire        vbr_rd_en;
148
  wire        vbr_rd_valid;
149
  wire        vbr_rd_almost_empty;
150
  wire        vbr_rd_empty;
151
 
152
  /* getbits_fifo - vld interface */
153
  wire  [4:0]advance;                       // number of bits to advance the bitstream (advance <= 24)   
154
  wire       align;                         // byte-align getbits and move forward one byte.
155
  wire [23:0]getbits;                       // elementary stream data. 
156
  wire       signbit;                       // sign bit, used when decoding dct variable length codes.
157
  wire       getbits_valid;                 // getbits_valid is asserted when getbits is valid.
158
  wire       wait_state;                    // after vld requesting getbits to advance or align, vld should wait one cycle for getbits to process the request.
159
  wire       vld_en;                        // enable vld when getbits, rld, motcomp not busy, and not a wait state 
160
 
161
  /* vld - rld_fifo interface */
162
  wire  [5:0]dct_coeff_wr_run;              // dct coefficient runlength, from vlc decoding
163
  wire [11:0]dct_coeff_wr_signed_level;     // dct coefficient level, 2's complement format, from vlc decoding
164
  wire       dct_coeff_wr_end;              // dct_coeff_end_in is asserted at end of block 
165
  wire       rld_wr_almost_full;            // rld fifo almost full signal; used as throttle for vld 
166
  wire       rld_wr_en;                     // rld fifo write enable
167
  wire       rld_wr_overflow;               // rld fifo write overflow
168
  wire  [1:0]rld_cmd_wr;                    // rld command (dct run/level code or quantizer matrix update)
169
  wire  [4:0]quantiser_scale_code;
170
  wire       alternate_scan;
171
  wire       q_scale_type;                  // quantizer scale type
172
  wire       macroblock_intra;
173
  wire  [1:0]intra_dc_precision;
174
  wire  [7:0]quant_wr_data_wr;              // data bus for writing quantizer matrix rams
175
  wire  [5:0]quant_wr_addr_wr;              // address bus for writing quantizer matrix rams
176
  wire       quant_rst_wr;                  // reset quantizer matrix to default values
177
  wire       quant_wr_intra_wr;             // write enable for intra quantiser matrix
178
  wire       quant_wr_non_intra_wr;         // write enable for non intra quantiser matrix
179
  wire       quant_wr_chroma_intra_wr;      // write enable for chroma intra quantiser matrix
180
  wire       quant_wr_chroma_non_intra_wr;  // write enable for chroma non intra quantiser matrix
181
 
182
  /* rld_fifo - rld interface */
183
  wire  [5:0]dct_coeff_rd_run;              // dct coefficient runlength, from vlc decoding
184
  wire [11:0]dct_coeff_rd_signed_level;     // dct coefficient level, 2's complement format, from vlc decoding
185
  wire       dct_coeff_rd_end;              // dct_coeff_end_out is asserted at end of block 
186
  wire       alternate_scan_rd;
187
  wire       q_scale_type_rd;               // quantizer scale type
188
  wire       macroblock_intra_rd;
189
  wire  [1:0]intra_dc_precision_rd;
190
  wire  [4:0]quantiser_scale_code_rd;
191
  wire  [7:0]quant_wr_data_rd;              // data bus for writing quantizer matrix rams
192
  wire  [5:0]quant_wr_addr_rd;              // address bus for writing quantizer matrix rams
193
  wire       quant_rst_rd;                  // reset quantizer matrix to default values
194
  wire       quant_wr_intra_rd;             // write enable for intra quantiser matrix
195
  wire       quant_wr_non_intra_rd;         // write enable for non intra quantiser matrix
196
  wire       quant_wr_chroma_intra_rd;      // write enable for chroma intra quantiser matrix
197
  wire       quant_wr_chroma_non_intra_rd;  // write enable for chroma non intra quantiser matrix
198
  wire  [1:0]rld_cmd_rd;
199
  wire       rld_rd_en;                     // rld fifo read enable
200
  wire       rld_rd_valid;                  // asserted when fifo outputs are valid
201
 
202
  /* quantiser ram - rld interface */
203
  wire       quant_rst;                     // reset quantizer matrix to default values
204
  wire  [5:0]quant_rd_addr;                 // address bus for reading quantizer matrix rams
205
  wire  [7:0]quant_rd_intra_data;           // data bus for reading quantizer matrix rams
206
  wire  [7:0]quant_rd_non_intra_data;       // data bus for reading quantizer matrix rams
207
  wire  [7:0]quant_wr_data;                 // data bus for writing quantizer matrix rams
208
  wire  [5:0]quant_wr_addr;                 // address bus for writing quantizer matrix rams
209
  wire       quant_wr_en_intra;             // write enable for intra quantiser matrix
210
  wire       quant_wr_en_non_intra;         // write enable for non intra quantiser matrix
211
  wire       quant_wr_en_chroma_intra;      // write enable for chroma intra quantiser matrix
212
  wire       quant_wr_en_chroma_non_intra;  // write enable for chroma non intra quantiser matrix
213
  wire       quant_alternate_scan;          // alternate scan
214
 
215
  /* idct - rld interface */
216
  wire [11:0]iquant_level;                  // inverse quantized dct coefficient
217
  wire       iquant_eob;                    // asserted at last inverse quantized dct coefficient of block
218
  wire       iquant_valid;                  // asserted when inverse quantized dct coefficient valid
219
 
220
  /* idct - idct_fifo interface */
221
  wire  [8:0]idct_data;
222
  wire       idct_eob;
223
  wire       idct_valid;
224
 
225
  /* idct_fifo - motcomp interface */
226
  wire             idct_fifo_almost_full;
227
  wire             idct_fifo_overflow;
228
  wire             idct_rd_dta_valid;
229
  wire             idct_rd_dta_empty;
230
  wire             idct_rd_dta_en;
231
  wire       [71:0]idct_rd_dta;
232
 
233
  /* vld - motcomp interface */
234
  wire         [2:0]picture_coding_type;
235
  wire         [1:0]picture_structure;
236
  wire         [1:0]motion_type;
237
  wire              dct_type;
238
  wire        [12:0]macroblock_address;
239
  wire              macroblock_motion_forward;
240
  wire              macroblock_motion_backward;
241
  wire         [7:0]mb_width;
242
  wire         [7:0]mb_height;
243
  wire              motion_vert_field_select_0_0;
244
  wire              motion_vert_field_select_0_1;
245
  wire              motion_vert_field_select_1_0;
246
  wire              motion_vert_field_select_1_1;
247
  wire              second_field;
248
  wire              update_picture_buffers;
249
  wire              last_frame;
250
  wire         [1:0]chroma_format;
251
  wire              motion_vector_valid;    // asserted when pmv_x_x_x, dmv_x_x valid
252
  wire signed [12:0]pmv_0_0_0;              // predicted motion vector
253
  wire signed [12:0]pmv_0_0_1;              // predicted motion vector
254
  wire signed [12:0]pmv_1_0_0;              // predicted motion vector
255
  wire signed [12:0]pmv_1_0_1;              // predicted motion vector
256
  wire signed [12:0]pmv_0_1_0;              // predicted motion vector
257
  wire signed [12:0]pmv_0_1_1;              // predicted motion vector
258
  wire signed [12:0]pmv_1_1_0;              // predicted motion vector
259
  wire signed [12:0]pmv_1_1_1;              // predicted motion vector
260
  wire signed [12:0]dmv_0_0;                // dual-prime motion vector
261
  wire signed [12:0]dmv_0_1;                // dual-prime motion vector
262
  wire signed [12:0]dmv_1_0;                // dual-prime motion vector
263
  wire signed [12:0]dmv_1_1;                // dual-prime motion vector
264
  wire              mvec_wr_almost_full;    // asserted if motion vector fifo fills up; used for flow control
265
 
266
 
267
  /* motcomp output */
268
  wire             motcomp_busy;            // asserted when motcomp input fifo's full
269
 
270
  /* vld - syncgen interface */
271
  wire       [13:0]horizontal_size;         // horizontal size of frame
272
  wire       [13:0]vertical_size;           // vertical size of frame
273
  wire       [13:0]display_horizontal_size; // displayable part of frame. If non-zero, always less than horizontal_size.
274
  wire       [13:0]display_vertical_size;   // displayable part of frame. If non-zero, always less than vertical_size.
275
 
276
  /* syncgen - mixer interface */
277
  wire       [11:0]h_pos;                   // horizontal position; 0 = left
278
  wire       [11:0]v_pos;                   // vertical position; 0 = top
279
  wire             pixel_en_gen;            // pixel enable generated by syncgen
280
  wire             h_sync_gen;              // h_sync generated by syncgen
281
  wire             v_sync_gen;              // v_sync generated by syncgen
282
 
283
  /* vld - syncgen interface */
284
  wire        [7:0]matrix_coefficients;     // determines yuv to rgb conversion factors
285
 
286
  /* resample - pixel queue interface */
287
  wire        [7:0]y_resample;              // luminance
288
  wire        [7:0]u_resample;              // chrominance
289
  wire        [7:0]v_resample;              // chrominance
290
  wire        [7:0]osd_resample;            // osd pixel color 
291
  wire        [2:0]position_resample;       // position, as in resample_codes.v
292
  wire             pixel_wr_en;
293
  wire             pixel_wr_almost_full;
294
  wire             pixel_wr_full;
295
  wire             pixel_wr_overflow;
296
 
297
  /* pixel queue - pixel repetition interface */
298
  wire        [7:0]y_pqueue;                // luminance
299
  wire        [7:0]u_pqueue;                // chrominance
300
  wire        [7:0]v_pqueue;                // chrominance
301
  wire        [7:0]osd_pqueue;              // osd pixel color 
302
  wire        [2:0]position_pqueue;         // position, as in resample_codes.v
303
  wire             pixel_rd_en_pqueue;
304
  wire             pixel_rd_empty_pqueue;
305
  wire             pixel_rd_valid_pqueue;
306
  wire             pixel_rd_underflow_pqueue;
307
 
308
  /* mixer - osd interface */
309
  wire        [7:0]y_mixer;                 // luminance
310
  wire        [7:0]u_mixer;                 // chrominance
311
  wire        [7:0]v_mixer;                 // chrominance
312
  wire        [7:0]osd_mixer;               // osd pixel color 
313
  wire             h_sync_mixer;
314
  wire             v_sync_mixer;
315
  wire             pixel_en_mixer;
316
 
317
  /* osd - yuv2rgb interface */
318
  wire             pixel_en_osd;            // pixel enable 
319
  wire             h_sync_osd;              // h_sync 
320
  wire             v_sync_osd;              // v_sync
321
  wire        [7:0]y_osd;                   // luminance
322
  wire        [7:0]u_osd;                   // chrominance
323
  wire        [7:0]v_osd;                   // chrominance
324
 
325
  /* osd - osd_clt interface */
326
  wire        [7:0]osd_clt_rd_addr;
327
  wire             osd_clt_rd_en;
328
  wire       [31:0]osd_clt_rd_dta;
329
 
330
  /* regfile - osd_clt interface */
331
  wire             osd_clt_wr_en;
332
  wire        [7:0]osd_clt_wr_addr;
333
  wire       [31:0]osd_clt_wr_dta;
334
 
335
  /* regfile - osd interface */
336
  wire             osd_enable;
337
 
338
  /* vld - regfile interface */
339
  wire             vld_err;
340
  wire        [3:0]frame_rate_code;         // par. 6.3.3, Table 6-4
341
  wire        [1:0]frame_rate_extension_n;  // par. 6.3.3, par. 6.3.5
342
  wire        [4:0]frame_rate_extension_d;  // par. 6.3.3, par. 6.3.5
343
  wire        [3:0]aspect_ratio_information;// par. 6.3.3
344
 
345
  assign           error = vld_err;
346
 
347
  /* regfile - syncgen interface */
348
  wire [11:0]horizontal_resolution;         /* horizontal resolution. number of dots per line, minus one  */
349
  wire [11:0]horizontal_sync_start;         /* the dot the horizontal sync pulse begins. */
350
  wire [11:0]horizontal_sync_end;           /* the dot the horizontal sync pulse ends. */
351
  wire [11:0]horizontal_length;             /* total horizontal length */
352
  wire [11:0]vertical_resolution;           /* vertical resolution. number of visible lines per frame (progressive) or field (interlaced), minus one */
353
  wire [11:0]vertical_sync_start;           /* the line number within the frame (progressive) or field (interlaced) the vertical sync pulse begins. */
354
  wire [11:0]vertical_sync_end;             /* the line number within the frame (progressive) or field (interlaced) the vertical sync pulse ends. */
355
  wire [11:0]horizontal_halfline;           /* the dot the vertical sync begins on odd frames of interlaced video. Not used in progressive mode. */
356
  wire [11:0]vertical_length;               /* total number of lines of a vertical frame (progressive) or field (interlaced) */
357
  wire       interlaced;                    /* asserted if interlaced output required. */
358
  wire       pixel_repetition;              /* assert for dot clock rates < 25 MHz, repeats each pixel */
359
  wire       clip_display_size;             /* assert to clip image to (display_horizontal_size, display_vertical_size) */
360
  wire       syncgen_rst;                   /* resets sync generator whenever a modeline parameter changes */
361
 
362
  /* regfile - picbuf  interface */
363
  wire  [2:0]source_select;                 /* select video out source */
364
 
365
  /* regfile - resample interface */
366
  wire       deinterlace;                   /* assert if video has to be deinterlaced */
367
  wire  [4:0]repeat_frame;                  /* repeat decoded images */
368
  wire       persistence;                   /* last decoded image persists */
369
 
370
  /* motcomp - resample interface */
371
  wire  [2:0]output_frame;                  /* frame to be displayed */
372
  wire       output_frame_valid;            /* asserted when output_frame valid */
373
  wire       output_frame_rd;               /* asserted to read next output_frame */
374
  wire       output_progressive_sequence;
375
  wire       output_progressive_frame;
376
  wire       output_top_field_first;
377
  wire       output_repeat_first_field;
378
 
379
  /* vld - motcomp_picbuf interface */
380
  wire       progressive_sequence;
381
  wire       progressive_frame;
382
  wire       top_field_first;
383
  wire       repeat_first_field;
384
 
385
  /*
386
   * Interface with frame store is through fifo's.
387
   */
388
 
389
  /*
390
   * fifo between motion compensation and frame store:
391
   * reading forward reference frame.
392
   */
393
 
394
  wire       fwd_wr_addr_clk_en;
395
  wire       fwd_wr_addr_full;
396
  wire       fwd_wr_addr_almost_full;
397
  wire       fwd_wr_addr_en;
398
  wire       fwd_wr_addr_ack;
399
  wire [21:0]fwd_wr_addr;
400
  wire       fwd_rd_dta_clk_en;
401
  wire       fwd_rd_dta_almost_empty;
402
  wire       fwd_rd_dta_empty;
403
  wire       fwd_rd_dta_en;
404
  wire       fwd_rd_dta_valid;
405
  wire [63:0]fwd_rd_dta;
406
  wire       fwd_rd_addr_empty;
407
  wire       fwd_rd_addr_en;
408
  wire       fwd_rd_addr_valid;
409
  wire [21:0]fwd_rd_addr;
410
  wire       fwd_wr_dta_full;
411
  wire       fwd_wr_dta_almost_full;
412
  wire       fwd_wr_dta_en;
413
  wire       fwd_wr_dta_ack;
414
  wire [63:0]fwd_wr_dta;
415
 
416
  /*
417
   * fifo between motion compensation and frame store:
418
   * reading backward reference frame.
419
   */
420
 
421
  wire       bwd_wr_addr_clk_en;
422
  wire       bwd_wr_addr_full;
423
  wire       bwd_wr_addr_almost_full;
424
  wire       bwd_wr_addr_en;
425
  wire       bwd_wr_addr_ack;
426
  wire [21:0]bwd_wr_addr;
427
  wire       bwd_rd_dta_clk_en;
428
  wire       bwd_rd_dta_empty;
429
  wire       bwd_rd_dta_almost_empty;
430
  wire       bwd_rd_dta_en;
431
  wire       bwd_rd_dta_valid;
432
  wire [63:0]bwd_rd_dta;
433
  wire       bwd_rd_addr_empty;
434
  wire       bwd_rd_addr_en;
435
  wire       bwd_rd_addr_valid;
436
  wire [21:0]bwd_rd_addr;
437
  wire       bwd_wr_dta_full;
438
  wire       bwd_wr_dta_almost_full;
439
  wire       bwd_wr_dta_en;
440
  wire       bwd_wr_dta_ack;
441
  wire [63:0]bwd_wr_dta;
442
 
443
  /*
444
   * fifo between motion compensation and frame store:
445
   * writing reconstructed frame.
446
   */
447
 
448
  wire       recon_wr_full;
449
  wire       recon_wr_almost_full;
450
  wire       recon_wr_en;
451
  wire       recon_wr_ack;
452
  wire [21:0]recon_wr_addr;
453
  wire [63:0]recon_wr_dta;
454
  wire       recon_rd_empty;
455
  wire       recon_rd_almost_empty;
456
  wire       recon_rd_en;
457
  wire       recon_rd_valid;
458
  wire [21:0]recon_rd_addr;
459
  wire [63:0]recon_rd_dta;
460
 
461
  /*
462
   * fifo between chroma resampling and frame store:
463
   * reading reconstructed frames.
464
   */
465
 
466
  wire       disp_wr_addr_full;
467
  wire       disp_wr_addr_almost_full;
468
  wire       disp_wr_addr_en;
469
  wire       disp_wr_addr_ack;
470
  wire [21:0]disp_wr_addr;
471
  wire       disp_rd_dta_empty;
472
  wire       disp_rd_dta_almost_empty;
473
  wire       disp_rd_dta_en;
474
  wire       disp_rd_dta_valid;
475
  wire [63:0]disp_rd_dta;
476
  wire       disp_rd_addr_empty;
477
  wire       disp_rd_addr_en;
478
  wire       disp_rd_addr_valid;
479
  wire [21:0]disp_rd_addr;
480
  wire       disp_wr_dta_full;
481
  wire       disp_wr_dta_almost_full;
482
  wire       disp_wr_dta_en;
483
  wire       disp_wr_dta_ack;
484
  wire [63:0]disp_wr_dta;
485
 
486
  /*
487
   * fifo between register file and frame store:
488
   * writing on-screen display
489
   */
490
 
491
  wire       osd_wr_almost_full;
492
  wire       osd_wr_full;
493
  wire       osd_wr_en;
494
  wire       osd_wr_ack;
495
  wire [21:0]osd_wr_addr;
496
  wire [63:0]osd_wr_dta;
497
  wire       osd_rd_almost_empty;
498
  wire       osd_rd_empty;
499
  wire       osd_rd_en;
500
  wire       osd_rd_valid;
501
  wire [21:0]osd_rd_addr;
502
  wire [63:0]osd_rd_dta;
503
 
504
  /* more overflows */
505
  wire       mem_req_wr_almost_full;
506
  wire       mem_req_wr_full;
507
  wire       mem_req_wr_overflow;
508
  wire       tag_wr_almost_full;
509
  wire       tag_wr_full;
510
  wire       tag_wr_overflow;
511
  wire       mem_res_wr_overflow;
512
  wire       vbw_wr_overflow;
513
  wire       vbr_wr_overflow;
514
  wire       dct_block_wr_overflow;
515
  wire       frame_idct_wr_overflow;
516
  wire       mvec_wr_overflow;
517
  wire       dst_wr_overflow;
518
  wire       fwd_wr_addr_overflow;
519
  wire       fwd_wr_dta_overflow;
520
  wire       bwd_wr_addr_overflow;
521
  wire       bwd_wr_dta_overflow;
522
  wire       recon_wr_overflow;
523
  wire       resample_wr_overflow;
524
  wire       disp_wr_addr_overflow;
525
  wire       disp_wr_dta_overflow;
526
  wire       osd_wr_overflow;
527
 
528
`include "fifo_size.v"
529
 
530
  /*
531
   * assert "busy" at power-on, to allow dual-port rams such as
532
   * quantizer matrices and osd lookup-table to be cleared / initialized.
533
   */
534
  reg [8:0]init_cnt;
535
  always @(posedge clk)
536
    if (~sync_rst) init_cnt <= 9'h0;
537
    else init_cnt <= (init_cnt == 9'h1ff) ? init_cnt : init_cnt + 9'd1;
538
 
539
  always @(posedge clk)
540
    if (~sync_rst) busy <= 1'b1;
541
    else busy <= vbw_wr_almost_full || ~sync_rst || (init_cnt != 9'h1ff);
542
 
543
  /* reset signal synchronizers */
544
 
545
  reset reset (
546
    .clk(clk),
547
    .mem_clk(mem_clk),
548
    .dot_clk(dot_clk),
549
    .async_rst(rst),
550
    .watchdog_rst(watchdog_rst),
551
    .clk_rst(sync_rst),
552
    .mem_rst(mem_rst),
553
    .dot_rst(dot_rst),
554
    .hard_rst(hard_rst)
555
    );
556
 
557
  /* register synchronizers */
558
 
559
  wire  [7:0]dot_matrix_coefficients;
560
  wire       dot_interlaced;
561
  wire       dot_pixel_repetition;
562
  wire       dot_osd_enable;
563
 
564
  sync_reg #(.width(8))  sync_matrix_coefficients     (dot_clk, dot_rst, matrix_coefficients, dot_matrix_coefficients);
565
  sync_reg #(.width(1))  sync_interlaced              (dot_clk, dot_rst, interlaced, dot_interlaced);
566
  sync_reg #(.width(1))  sync_pixel_repetition        (dot_clk, dot_rst, pixel_repetition, dot_pixel_repetition);
567
  sync_reg #(.width(1))  sync_osd_enable              (dot_clk, dot_rst, osd_enable, dot_osd_enable);
568
 
569
  /* test point synchronizer, for reading test point via register file */
570
  wire [31:0]regfile_testpoint;
571
  sync_reg #(.width(32)) sync_testpoint               (clk, sync_rst, testpoint[31:0], regfile_testpoint); // Only pass on bits 31..0. bits 32 and 33 are likely to be clocks and clock enables.
572
 
573
  /* vertical sync synchronizer, for generating interrupt at vertical sync start */
574
  wire       regfile_v_sync;
575
  sync_reg #(.width(1))  sync_v_sync                  (clk, sync_rst, v_sync_gen, regfile_v_sync);
576
 
577
  /* flush video buffer */
578
  wire       flush_vbuf;                              /* flush video buffer */
579
  wire       vbuf_rst;                                /* circular video buffer reset signal, synchronized and at least three clocks long */
580
 
581
  sync_reset sync_vbuf_reset (
582
    .clk(clk),
583
    .asyncrst(rst && ~flush_vbuf),
584
    .syncrst(vbuf_rst)
585
    );
586
 
587
  /* write elementary stream to circular buffer */
588
  vbuf_write vbuf_write (
589
    .clk(clk),
590
    .clk_en(1'b1),
591
    .rst(sync_rst),
592
    .vid_in(stream_data),                                    // program stream input
593
    .vid_in_wr_en(stream_valid),                             // program stream input
594
    .vid_out(vbw_wr_dta),                                    // to vbuf_write_fifo
595
    .vid_out_wr_en(vbw_wr_en)                                // to vbuf_write_fifo
596
    );
597
 
598
  /* vbuf write fifo */
599
  fifo_sc
600
    #(.addr_width(VBUF_WR_DEPTH),
601
    .dta_width(9'd64),
602
    .prog_thresh(VBUF_WR_THRESHOLD))
603
    vbuf_write_fifo (
604
    .rst(vbuf_rst),
605
    .clk(clk),
606
    .din(vbw_wr_dta),                                        // from vbuf_write
607
    .wr_en(vbw_wr_en),                                       // from vbuf_write
608
    .wr_ack(),
609
    .full(vbw_wr_full),
610
    .overflow(vbw_wr_overflow),
611
    .dout(vbw_rd_dta),                                       // to framestore
612
    .rd_en(vbw_rd_en),                                       // to framestore
613
    .valid(vbw_rd_valid),                                    // to framestore
614
    .empty(vbw_rd_empty),                                    // to framestore
615
    .prog_empty(vbw_rd_almost_empty),                        // to framestore
616
    .prog_full(vbw_wr_almost_full),                          // to framestore and output pin "busy"
617
    .underflow()
618
    );
619
 
620
  /* vbuf read fifo */
621
  fifo_sc
622
    #(.addr_width(VBUF_RD_DEPTH),
623
    .dta_width(9'd64),
624
    .prog_thresh(VBUF_RD_THRESHOLD))
625
    vbuf_read_fifo (
626
    .rst(vbuf_rst),
627
    .clk(clk),
628
    .din(vbr_wr_dta),                                        // from framestore
629
    .wr_en(vbr_wr_en),                                       // from framestore
630
    .wr_ack(vbr_wr_ack),                                     // to framestore
631
    .full(vbr_wr_full),                                      // to framestore
632
    .overflow(vbr_wr_overflow),                              // to probe
633
    .dout(vbr_rd_dta),                                       // to getbits_fifo
634
    .rd_en(vbr_rd_en),                                       // from getbits_fifo
635
    .valid(vbr_rd_valid),                                    // to getbits_fifo
636
    .empty(vbr_rd_empty),                                    // to probe
637
    .prog_empty(vbr_rd_almost_empty),                        // to framestore
638
    .prog_full(vbr_wr_almost_full),                          // to framestore
639
    .underflow()
640
    );
641
 
642
  /* read elementary stream from circular buffer, one bitfield at a time */
643
  getbits_fifo getbits_fifo (
644
    .clk(clk),
645
    .clk_en(1'b1),
646
    .rst(sync_rst),
647
    .vid_in(vbr_rd_dta),                                     // from vbuf_read_fifo
648
    .vid_in_rd_en(vbr_rd_en),                                // to vbuf_read_fifo
649
    .vid_in_rd_valid(vbr_rd_valid),                          // from vbuf_read_fifo
650
    .advance(advance),                                       // from vld
651
    .align(align),                                           // from vld
652
    .wait_state(wait_state),                                 // from vld
653
    .rld_wr_almost_full(rld_wr_almost_full),                 // from rld fifo
654
    .mvec_wr_almost_full(mvec_wr_almost_full),               // from motcomp
655
    .motcomp_busy(motcomp_busy),                             // from motcomp
656
    .getbits(getbits),                                       // to vld
657
    .signbit(signbit),                                       // to vld
658
    .getbits_valid(getbits_valid),                           // to probe
659
    .vld_en(vld_en)                                          // to vld
660
    );
661
 
662
  /* variable length decoder */
663
  vld vld(
664
    .clk(clk),
665
    .clk_en(vld_en),                                         // from getbits
666
    .rst(sync_rst),
667
    .getbits(getbits),                                       // from getbits
668
    .signbit(signbit),                                       // from getbits
669
    .advance(advance),                                       // to getbits
670
    .align(align),                                           // to getbits
671
    .wait_state(wait_state),                                 // to getbits
672
    .quant_wr_data(quant_wr_data_wr),                        // to rld_fifo
673
    .quant_wr_addr(quant_wr_addr_wr),                        // to rld_fifo
674
    .quant_rst(quant_rst_wr),                                // to rld_fifo
675
    .wr_intra_quant(quant_wr_intra_wr),                      // to rld_fifo
676
    .wr_non_intra_quant(quant_wr_non_intra_wr),              // to rld_fifo
677
    .wr_chroma_intra_quant(quant_wr_chroma_intra_wr),        // to rld_fifo
678
    .wr_chroma_non_intra_quant(quant_wr_chroma_non_intra_wr),  // to rld_fifo
679
    .rld_wr_en(rld_wr_en),                                   // to rld_fifo
680
    .rld_cmd(rld_cmd_wr),                                    // to rld_fifo
681
    .dct_coeff_run(dct_coeff_wr_run),                        // to rld_fifo
682
    .dct_coeff_signed_level(dct_coeff_wr_signed_level),      // to rld_fifo
683
    .dct_coeff_end(dct_coeff_wr_end),                        // to rld_fifo
684
    .alternate_scan(alternate_scan),                         // to rld_fifo
685
    .q_scale_type(q_scale_type),                             // to rld_fifo
686
    .quantiser_scale_code(quantiser_scale_code),             // to rld_fifo
687
    .macroblock_intra(macroblock_intra),                     // to rld_fifo and motcomp
688
    .intra_dc_precision(intra_dc_precision),                 // to rld_fifo
689
    .matrix_coefficients(matrix_coefficients),               // to yuv2rgb
690
    .horizontal_size(horizontal_size),                       // to regfile
691
    .vertical_size(vertical_size),                           // to regfile
692
    .display_horizontal_size(display_horizontal_size),       // to regfile
693
    .display_vertical_size(display_vertical_size),           // to regfile
694
    .aspect_ratio_information(aspect_ratio_information),     // to regfile
695
    .frame_rate_code(frame_rate_code),                       // to regfile
696
    .frame_rate_extension_n(frame_rate_extension_n),         // to regfile
697
    .frame_rate_extension_d(frame_rate_extension_d),         // to regfile
698
    .picture_coding_type(picture_coding_type),               // to motcomp
699
    .picture_structure(picture_structure),                   // to motcomp
700
    .motion_type(motion_type),                               // to motcomp
701
    .dct_type(dct_type),                                     // to motcomp
702
    .macroblock_address(macroblock_address),                 // to motcomp
703
    .macroblock_motion_forward(macroblock_motion_forward),   // to motcomp
704
    .macroblock_motion_backward(macroblock_motion_backward), // to motcomp
705
    .mb_width(mb_width),                                     // to motcomp
706
    .mb_height(mb_height),                                   // to motcomp
707
    .motion_vert_field_select_0_0(motion_vert_field_select_0_0), // to motcomp
708
    .motion_vert_field_select_0_1(motion_vert_field_select_0_1), // to motcomp
709
    .motion_vert_field_select_1_0(motion_vert_field_select_1_0), // to motcomp
710
    .motion_vert_field_select_1_1(motion_vert_field_select_1_1), // to motcomp
711
    .second_field(second_field),                             // to motcomp
712
    .update_picture_buffers(update_picture_buffers),         // to motcomp
713
    .last_frame(last_frame),                                 // to motcomp
714
    .chroma_format(chroma_format),                           // to motcomp
715
    .motion_vector_valid(motion_vector_valid),               // to motcomp
716
    .pmv_0_0_0(pmv_0_0_0),                                   // to motcomp
717
    .pmv_0_0_1(pmv_0_0_1),                                   // to motcomp
718
    .pmv_1_0_0(pmv_1_0_0),                                   // to motcomp
719
    .pmv_1_0_1(pmv_1_0_1),                                   // to motcomp
720
    .pmv_0_1_0(pmv_0_1_0),                                   // to motcomp
721
    .pmv_0_1_1(pmv_0_1_1),                                   // to motcomp
722
    .pmv_1_1_0(pmv_1_1_0),                                   // to motcomp
723
    .pmv_1_1_1(pmv_1_1_1),                                   // to motcomp
724
    .dmv_0_0(dmv_0_0),                                       // to motcomp
725
    .dmv_0_1(dmv_0_1),                                       // to motcomp
726
    .dmv_1_0(dmv_1_0),                                       // to motcomp
727
    .dmv_1_1(dmv_1_1),                                       // to motcomp
728
    .progressive_sequence(progressive_sequence),             // to resample
729
    .progressive_frame(progressive_frame),                   // to resample
730
    .top_field_first(top_field_first),                       // to resample
731
    .repeat_first_field(repeat_first_field),                 // to resample
732
    .vld_err(vld_err)
733
    );
734
 
735
  rld_fifo rld_fifo (
736
    .clk(clk),
737
    .clk_en(1'b1),
738
    .rst(sync_rst),
739
    .dct_coeff_wr_run(dct_coeff_wr_run),
740
    .dct_coeff_wr_signed_level(dct_coeff_wr_signed_level),
741
    .dct_coeff_wr_end(dct_coeff_wr_end),
742
    .alternate_scan_wr(alternate_scan),
743
    .macroblock_intra_wr(macroblock_intra),
744
    .intra_dc_precision_wr(intra_dc_precision),
745
    .q_scale_type_wr(q_scale_type),
746
    .quantiser_scale_code_wr(quantiser_scale_code),
747
    .quant_wr_data_wr(quant_wr_data_wr),
748
    .quant_wr_addr_wr(quant_wr_addr_wr),
749
    .quant_rst_wr(quant_rst_wr),
750
    .quant_wr_intra_wr(quant_wr_intra_wr),
751
    .quant_wr_non_intra_wr(quant_wr_non_intra_wr),
752
    .quant_wr_chroma_intra_wr(quant_wr_chroma_intra_wr),
753
    .quant_wr_chroma_non_intra_wr(quant_wr_chroma_non_intra_wr),
754
    .rld_cmd_wr(rld_cmd_wr),
755
    .rld_wr_en(rld_wr_en),
756
    .rld_wr_almost_full(rld_wr_almost_full),
757
    .rld_wr_overflow(rld_wr_overflow),
758
    .dct_coeff_rd_run(dct_coeff_rd_run),
759
    .dct_coeff_rd_signed_level(dct_coeff_rd_signed_level),
760
    .dct_coeff_rd_end(dct_coeff_rd_end),
761
    .alternate_scan_rd(alternate_scan_rd),
762
    .macroblock_intra_rd(macroblock_intra_rd),
763
    .intra_dc_precision_rd(intra_dc_precision_rd),
764
    .q_scale_type_rd(q_scale_type_rd),
765
    .quantiser_scale_code_rd(quantiser_scale_code_rd),
766
    .quant_wr_data_rd(quant_wr_data_rd),
767
    .quant_wr_addr_rd(quant_wr_addr_rd),
768
    .quant_rst_rd(quant_rst_rd),
769
    .quant_wr_intra_rd(quant_wr_intra_rd),
770
    .quant_wr_non_intra_rd(quant_wr_non_intra_rd),
771
    .quant_wr_chroma_intra_rd(quant_wr_chroma_intra_rd),
772
    .quant_wr_chroma_non_intra_rd(quant_wr_chroma_non_intra_rd),
773
    .rld_cmd_rd(rld_cmd_rd),
774
    .rld_rd_en(rld_rd_en),
775
    .rld_rd_valid(rld_rd_valid)
776
    );
777
 
778
  /* Run-length decoding */
779
  rld rld (
780
    .clk(clk),
781
    .clk_en(1'b1),
782
    .rst(sync_rst),
783
    .idct_fifo_almost_full(idct_fifo_almost_full),               // from idct_fifo
784
    .dct_coeff_rd_run(dct_coeff_rd_run),                         // from rld_fifo
785
    .dct_coeff_rd_signed_level(dct_coeff_rd_signed_level),       // from rld_fifo
786
    .dct_coeff_rd_end(dct_coeff_rd_end),                         // from rld_fifo
787
    .alternate_scan_rd(alternate_scan_rd),                       // from rld_fifo
788
    .q_scale_type_rd(q_scale_type_rd),                           // from rld_fifo
789
    .macroblock_intra_rd(macroblock_intra_rd),                   // from rld_fifo
790
    .intra_dc_precision_rd(intra_dc_precision_rd),               // from rld_fifo
791
    .quantiser_scale_code_rd(quantiser_scale_code_rd),           // from rld_fifo
792
    .quant_wr_data_rd(quant_wr_data_rd),                         // from rld_fifo
793
    .quant_wr_addr_rd(quant_wr_addr_rd),                         // from rld_fifo
794
    .quant_rst_rd(quant_rst_rd),                                 // from rld_fifo
795
    .quant_wr_intra_rd(quant_wr_intra_rd),                       // from rld_fifo
796
    .quant_wr_non_intra_rd(quant_wr_non_intra_rd),               // from rld_fifo
797
    .quant_wr_chroma_intra_rd(quant_wr_chroma_intra_rd),         // from rld_fifo
798
    .quant_wr_chroma_non_intra_rd(quant_wr_chroma_non_intra_rd), // from rld_fifo
799
    .rld_cmd_rd(rld_cmd_rd),                                     // from rld_fifo
800
    .rld_rd_en(rld_rd_en),                                       // to rld_fifo
801
    .rld_rd_valid(rld_rd_valid),                                 // from rld_fifo
802
    .quant_rst(quant_rst),                                       // to quantiser rams
803
    .quant_rd_addr(quant_rd_addr),                               // to quantiser rams
804
    .quant_rd_intra_data(quant_rd_intra_data),                   // from quantiser rams
805
    .quant_rd_non_intra_data(quant_rd_non_intra_data),           // from quantiser rams
806
    .quant_wr_data(quant_wr_data),                               // to quantiser rams
807
    .quant_wr_addr(quant_wr_addr),                               // to quantiser rams
808
    .quant_wr_en_intra(quant_wr_en_intra),                       // to quantiser rams
809
    .quant_wr_en_non_intra(quant_wr_en_non_intra),               // to quantiser rams
810
    .quant_wr_en_chroma_intra(quant_wr_en_chroma_intra),         // to quantiser rams
811
    .quant_wr_en_chroma_non_intra(quant_wr_en_chroma_non_intra), // to quantiser rams
812
    .quant_alternate_scan(quant_alternate_scan),                 // to quantiser rams
813
    .iquant_level(iquant_level),                                 // to idct
814
    .iquant_eob(iquant_eob),                                     // to idct
815
    .iquant_valid(iquant_valid)                                  // to idct
816
    );
817
 
818
  /* inverse discrete cosine transform */
819
  idct idct(
820
    .clk(clk),
821
    .clk_en(1'b1),
822
    .rst(sync_rst),
823
    .iquant_level(iquant_level),                             // from rld
824
    .iquant_eob(iquant_eob),                                 // from rld
825
    .iquant_valid(iquant_valid),                             // from rld
826
    .idct_data(idct_data),                                   // to idct_fifo
827
    .idct_eob(idct_eob),                                     // to idct_fifo
828
    .idct_valid(idct_valid)                                  // to idct_fifo
829
    );
830
 
831
  /* group inverse discrete cosine transform coefficients in rows of eight */
832
  idct_fifo idct_fifo(
833
    .clk(clk),
834
    .clk_en(1'b1),
835
    .rst(sync_rst),
836
    .idct_data(idct_data),                                   // from idct
837
    .idct_eob(idct_eob),                                     // from idct
838
    .idct_valid(idct_valid),                                 // from idct
839
    .idct_wr_dta_almost_full(idct_fifo_almost_full),         // from idct
840
    .idct_wr_dta_full(),
841
    .idct_wr_dta_overflow(idct_fifo_overflow),               // from idct
842
    .idct_rd_dta_empty(idct_rd_dta_empty),                   // to motcomp
843
    .idct_rd_dta_en(idct_rd_dta_en),                         // to motcomp
844
    .idct_rd_dta(idct_rd_dta),                               // to motcomp
845
    .idct_rd_dta_valid(idct_rd_dta_valid),                   // to motcomp
846
    .idct_rd_dta_almost_empty()
847
    );
848
 
849
  /* motion compensation */
850
  motcomp motcomp(
851
    .clk(clk),
852
    .clk_en(1'b1),
853
    .rst(sync_rst),
854
    .busy(motcomp_busy),
855
    .picture_coding_type(picture_coding_type),               // from vld
856
    .picture_structure(picture_structure),                   // from vld
857
    .motion_type(motion_type),                               // from vld
858
    .dct_type(dct_type),                                     // from vld
859
    .macroblock_address(macroblock_address),                 // from vld
860
    .macroblock_motion_forward(macroblock_motion_forward),   // from vld
861
    .macroblock_motion_backward(macroblock_motion_backward), // from vld
862
    .macroblock_intra(macroblock_intra),                     // from vld
863
    .mb_width(mb_width),                                     // from vld
864
    .mb_height(mb_height),                                   // from vld
865
    .horizontal_size(horizontal_size),                       // from vld
866
    .vertical_size(vertical_size),                           // from vld
867
    .motion_vert_field_select_0_0(motion_vert_field_select_0_0), // from vld
868
    .motion_vert_field_select_0_1(motion_vert_field_select_0_1), // from vld
869
    .motion_vert_field_select_1_0(motion_vert_field_select_1_0), // from vld
870
    .motion_vert_field_select_1_1(motion_vert_field_select_1_1), // from vld
871
    .second_field(second_field),                             // from vld
872
    .update_picture_buffers(update_picture_buffers),         // from vld
873
    .progressive_sequence(progressive_sequence),             // from vld
874
    .progressive_frame(progressive_frame),                   // from vld
875
    .top_field_first(top_field_first),                       // from vld
876
    .repeat_first_field(repeat_first_field),                 // from vld
877
    .last_frame(last_frame),                                 // from vld
878
    .chroma_format(chroma_format),                           // from vld
879
    .motion_vector_valid(motion_vector_valid),               // from vld
880
    .pmv_0_0_0(pmv_0_0_0),                                   // from vld
881
    .pmv_0_0_1(pmv_0_0_1),                                   // from vld
882
    .pmv_1_0_0(pmv_1_0_0),                                   // from vld
883
    .pmv_1_0_1(pmv_1_0_1),                                   // from vld
884
    .pmv_0_1_0(pmv_0_1_0),                                   // from vld
885
    .pmv_0_1_1(pmv_0_1_1),                                   // from vld
886
    .pmv_1_1_0(pmv_1_1_0),                                   // from vld
887
    .pmv_1_1_1(pmv_1_1_1),                                   // from vld
888
    .dmv_0_0(dmv_0_0),                                       // from vld
889
    .dmv_0_1(dmv_0_1),                                       // from vld
890
    .dmv_1_0(dmv_1_0),                                       // from vld
891
    .dmv_1_1(dmv_1_1),                                       // from vld
892
 
893
    .idct_rd_dta_empty(idct_rd_dta_empty),                   // from idct_fifo
894
    .idct_rd_dta_en(idct_rd_dta_en),                         // from idct_fifo
895
    .idct_rd_dta(idct_rd_dta),                               // from idct_fifo
896
    .idct_rd_dta_valid(idct_rd_dta_valid),                   // from idct_fifo
897
    .dct_block_wr_overflow(dct_block_wr_overflow),           // to probe
898
    .frame_idct_wr_overflow(frame_idct_wr_overflow),         // to probe
899
 
900
    .source_select(source_select),                           // from regfile
901
 
902
    .fwd_wr_addr_clk_en(fwd_wr_addr_clk_en),                 // to fwd framestore_reader
903
    .fwd_wr_addr_full(fwd_wr_addr_full),                     // to fwd framestore_reader
904
    .fwd_wr_addr_almost_full(fwd_wr_addr_almost_full),       // to fwd framestore_reader
905
    .fwd_wr_addr_en(fwd_wr_addr_en),                         // to fwd framestore_reader
906
    .fwd_wr_addr_ack(fwd_wr_addr_ack),                       // to fwd framestore_reader
907
    .fwd_wr_addr(fwd_wr_addr),                               // to fwd framestore_reader
908
    .fwd_rd_dta_clk_en(fwd_rd_dta_clk_en),                   // to fwd framestore_reader
909
    .fwd_rd_dta_empty(fwd_rd_dta_empty),                     // to fwd framestore_reader
910
    .fwd_rd_dta_en(fwd_rd_dta_en),                           // to fwd framestore_reader
911
    .fwd_rd_dta_valid(fwd_rd_dta_valid),                     // to fwd framestore_reader
912
    .fwd_rd_dta(fwd_rd_dta),                                 // to fwd framestore_reader
913
 
914
    .bwd_wr_addr_clk_en(bwd_wr_addr_clk_en),                 // to bwd framestore_reader
915
    .bwd_wr_addr_full(bwd_wr_addr_full),                     // to bwd framestore_reader
916
    .bwd_wr_addr_almost_full(bwd_wr_addr_almost_full),       // to bwd framestore_reader
917
    .bwd_wr_addr_en(bwd_wr_addr_en),                         // to bwd framestore_reader
918
    .bwd_wr_addr_ack(bwd_wr_addr_ack),                       // to bwd framestore_reader
919
    .bwd_wr_addr(bwd_wr_addr),                               // to bwd framestore_reader
920
    .bwd_rd_dta_clk_en(bwd_rd_dta_clk_en),                   // to bwd framestore_reader
921
    .bwd_rd_dta_empty(bwd_rd_dta_empty),                     // to bwd framestore_reader
922
    .bwd_rd_dta_en(bwd_rd_dta_en),                           // to bwd framestore_reader
923
    .bwd_rd_dta_valid(bwd_rd_dta_valid),                     // to bwd framestore_reader
924
    .bwd_rd_dta(bwd_rd_dta),                                 // to bwd framestore_reader
925
 
926
    .recon_wr_full(recon_wr_full),                           // to recon framestore_writer
927
    .recon_wr_almost_full(recon_wr_almost_full),             // to recon framestore_writer
928
    .recon_wr_en(recon_wr_en),                               // to recon framestore_writer
929
    .recon_wr_ack(recon_wr_ack),                             // to recon framestore_writer
930
    .recon_wr_addr(recon_wr_addr),                           // to recon framestore_writer
931
    .recon_wr_dta(recon_wr_dta),                             // to recon framestore_writer
932
 
933
    .output_frame(output_frame),                             // to resample
934
    .output_frame_valid(output_frame_valid),                 // to resample
935
    .output_frame_rd(output_frame_rd),                       // from resample
936
    .output_progressive_sequence(output_progressive_sequence),// to resample
937
    .output_progressive_frame(output_progressive_frame),     // to resample
938
    .output_top_field_first(output_top_field_first),         // to resample
939
    .output_repeat_first_field(output_repeat_first_field),   // to resample
940
 
941
    .mvec_wr_almost_full(mvec_wr_almost_full),               // to getbits
942
    .mvec_wr_overflow(mvec_wr_overflow),                     // to probe
943
    .dst_wr_overflow(dst_wr_overflow)                        // to probe
944
    );
945
 
946
  /* Quantisation coefficients */
947
  intra_quant_matrix intra_quantiser_matrix (
948
    .clk(clk),
949
    .rst(sync_rst),
950
    .rd_addr(quant_rd_addr),                                 // from rld
951
    .rd_clk_en(1'b1),                                        // same as rld
952
    .dta_out(quant_rd_intra_data),                           // to rld
953
    .wr_addr(quant_wr_addr),                                 // from rld
954
    .dta_in(quant_wr_data),                                  // from rld
955
    .wr_clk_en(1'b1),                                        // same as rld
956
    .wr_en(quant_wr_en_intra),                               // from rld
957
    .rst_values(quant_rst),                                  // from rld
958
    .alternate_scan(quant_alternate_scan)                    // from rld
959
    );
960
 
961
  non_intra_quant_matrix non_intra_quantiser_matrix (
962
    .clk(clk),
963
    .rst(sync_rst),
964
    .rd_addr(quant_rd_addr),                                 // from rld
965
    .rd_clk_en(1'b1),                                        // same as rld
966
    .dta_out(quant_rd_non_intra_data),                       // to rld
967
    .wr_addr(quant_wr_addr),                                 // from rld
968
    .dta_in(quant_wr_data),                                  // from rld
969
    .wr_clk_en(1'b1),                                        // same as rld
970
    .wr_en(quant_wr_en_non_intra),                           // from rld
971
    .rst_values(quant_rst),                                  // from rld
972
    .alternate_scan(quant_alternate_scan)                    // from rld
973
    );
974
 
975
  /* Chroma resampling */
976
  resample resample (
977
    .clk(clk),
978
    .rst(sync_rst),
979
 
980
    .output_frame(output_frame),                             // from motcomp
981
    .output_frame_valid(output_frame_valid),                 // from motcomp
982
    .output_frame_rd(output_frame_rd),                       // to motcomp
983
 
984
    .progressive_sequence(output_progressive_sequence),      // from motcomp_picbuf
985
    .progressive_frame(output_progressive_frame),            // from motcomp_picbuf
986
    .top_field_first(output_top_field_first),                // from motcomp_picbuf
987
    .repeat_first_field(output_repeat_first_field),          // from motcomp_picbuf
988
    .mb_width(mb_width),                                     // from vld
989
    .mb_height(mb_height),                                   // from vld
990
    .horizontal_size(horizontal_size),                       // from vld
991
    .vertical_size(vertical_size),                           // from vld
992
    .resample_wr_overflow(resample_wr_overflow),             // to probe
993
    .disp_wr_addr_full(disp_wr_addr_full),                   // to disp framestore_reader
994
    .disp_wr_addr_almost_full(disp_wr_addr_almost_full),     // to disp framestore_reader
995
    .disp_wr_addr_en(disp_wr_addr_en),                       // to disp framestore_reader
996
    .disp_wr_addr_ack(disp_wr_addr_ack),                     // to disp framestore_reader
997
    .disp_wr_addr(disp_wr_addr),                             // to disp framestore_reader
998
    .disp_rd_dta_empty(disp_rd_dta_empty),                   // to disp framestore_reader
999
    .disp_rd_dta_en(disp_rd_dta_en),                         // to disp framestore_reader
1000
    .disp_rd_dta_valid(disp_rd_dta_valid),                   // to disp framestore_reader
1001
    .disp_rd_dta(disp_rd_dta),                               // to disp framestore_reader
1002
    .interlaced(interlaced),                                 // from regfile
1003
    .deinterlace(deinterlace),                               // from regfile
1004
    .persistence(persistence),                               // from regfile
1005
    .repeat_frame(repeat_frame),                             // from regfile
1006
 
1007
    .y(y_resample),                                          // to pixel queue
1008
    .u(u_resample),                                          // to pixel queue
1009
    .v(v_resample),                                          // to pixel queue
1010
    .osd_out(osd_resample),                                  // to pixel queue
1011
    .position_out(position_resample),                        // to pixel queue
1012
    .pixel_wr_en(pixel_wr_en),                               // to pixel queue
1013
    .pixel_wr_almost_full(pixel_wr_almost_full)              // to pixel queue
1014
    );
1015
 
1016
  /* Pixel Queue */
1017
  pixel_queue pixel_queue (
1018
    .clk_in(clk),
1019
    .clk_in_en(1'b1),
1020
    .rst(sync_rst),
1021
    /* from resampling */
1022
    .y_in(y_resample),                                       // from resample
1023
    .u_in(u_resample),                                       // from resample
1024
    .v_in(v_resample),                                       // from resample
1025
    .osd_in(osd_resample),                                   // from resample
1026
    .position_in(position_resample),                         // from resample
1027
    .pixel_wr_en(pixel_wr_en),                               // from resample
1028
    .pixel_wr_almost_full(pixel_wr_almost_full),             // to resample
1029
    .pixel_wr_full(pixel_wr_full),                           // to probe
1030
    .pixel_wr_overflow(pixel_wr_overflow),                   // to probe
1031
    .clk_out(dot_clk),
1032
    .clk_out_en(1'b1),
1033
    /* to mixer */
1034
    .y_out(y_pqueue),                                        // to mixer
1035
    .u_out(u_pqueue),                                        // to mixer
1036
    .v_out(v_pqueue),                                        // to mixer
1037
    .osd_out(osd_pqueue),                                    // to mixer
1038
    .position_out(position_pqueue),                          // to mixer
1039
    .pixel_rd_en(pixel_rd_en_pqueue),                        // from mixer
1040
    .pixel_rd_empty(pixel_rd_empty_pqueue),                  // to probe
1041
    .pixel_rd_valid(pixel_rd_valid_pqueue),                  // to mixer
1042
    .pixel_rd_underflow(pixel_rd_underflow_pqueue)           // to mixer
1043
    );
1044
 
1045
  /* Video synchronisation and timing generator */
1046
  syncgen_intf syncgen_intf (
1047
    .clk(dot_clk),
1048
    .clk_en(1'b1),
1049
    .rst(dot_rst),
1050
    .horizontal_size(horizontal_size),                       // from vld
1051
    .vertical_size(vertical_size),                           // from vld
1052
    .display_horizontal_size(display_horizontal_size),       // from vld
1053
    .display_vertical_size(display_vertical_size),           // from vld
1054
    .syncgen_rst(syncgen_rst),                               // from regfile
1055
    .horizontal_resolution(horizontal_resolution),           // from regfile
1056
    .horizontal_sync_start(horizontal_sync_start),           // from regfile
1057
    .horizontal_sync_end(horizontal_sync_end),               // from regfile
1058
    .horizontal_length(horizontal_length),                   // from regfile
1059
    .vertical_resolution(vertical_resolution),               // from regfile
1060
    .vertical_sync_start(vertical_sync_start),               // from regfile
1061
    .vertical_sync_end(vertical_sync_end),                   // from regfile
1062
    .horizontal_halfline(horizontal_halfline),               // from regfile
1063
    .vertical_length(vertical_length),                       // from regfile
1064
    .interlaced(interlaced),                                 // from regfile
1065
    .clip_display_size(clip_display_size),                   // from regfile
1066
    .pixel_repetition(pixel_repetition),                     // from regfile
1067
    .h_pos(h_pos),                                           // to mixer
1068
    .v_pos(v_pos),                                           // to mixer
1069
    .pixel_en(pixel_en_gen),                                 // to mixer
1070
    .h_sync(h_sync_gen),                                     // to mixer
1071
    .v_sync(v_sync_gen),                                     // to mixer
1072
    .c_sync(),
1073
    .h_blank(),
1074
    .v_blank()
1075
    );
1076
 
1077
  /* Mixer */
1078
  mixer mixer (
1079
    .clk(dot_clk),
1080
    .rst(dot_rst),
1081
    .pixel_repetition(dot_pixel_repetition),                 // from register file
1082
    .y_in(y_pqueue),                                         // from pixel queue
1083
    .u_in(u_pqueue),                                         // from pixel queue
1084
    .v_in(v_pqueue),                                         // from pixel queue
1085
    .osd_in(osd_pqueue),                                     // from pixel queue
1086
    .position_in(position_pqueue),                           // from pixel queue
1087
    .pixel_rd_en(pixel_rd_en_pqueue),                        // to pixel queue
1088
    .pixel_rd_valid(pixel_rd_valid_pqueue),                  // from pixel queue
1089
    .pixel_rd_underflow(pixel_rd_underflow_pqueue),          // from pixel queue
1090
    .h_pos(h_pos),                                           // from sync_gen
1091
    .v_pos(v_pos),                                           // from sync_gen
1092
    .h_sync_in(h_sync_gen),                                  // from sync_gen
1093
    .v_sync_in(v_sync_gen),                                  // from sync_gen
1094
    .pixel_en_in(pixel_en_gen),                              // from sync_gen
1095
    .y_out(y_mixer),                                         // to osd
1096
    .u_out(u_mixer),                                         // to osd
1097
    .v_out(v_mixer),                                         // to osd
1098
    .osd_out(osd_mixer),                                     // to osd
1099
    .h_sync_out(h_sync_mixer),                               // to osd
1100
    .v_sync_out(v_sync_mixer),                               // to osd
1101
    .pixel_en_out(pixel_en_mixer)                            // to osd
1102
    );
1103
 
1104
  /* On-Screen Display */
1105
 
1106
  osd osd (
1107
    .clk(dot_clk),
1108
    .clk_en(1'b1),
1109
    .rst(dot_rst),
1110
    .y_in(y_mixer),                                          // from mixer
1111
    .u_in(u_mixer),                                          // from mixer
1112
    .v_in(v_mixer),                                          // from mixer
1113
    .h_sync_in(h_sync_mixer),                                // from mixer
1114
    .v_sync_in(v_sync_mixer),                                // from mixer
1115
    .pixel_en_in(pixel_en_mixer),                            // from mixer
1116
    .osd_in(osd_mixer),                                      // from mixer
1117
    .y_out(y_osd),                                           // to yuv2rgb
1118
    .u_out(u_osd),                                           // to yuv2rgb
1119
    .v_out(v_osd),                                           // to yuv2rgb
1120
    .h_sync_out(h_sync_osd),                                 // to yuv2rgb
1121
    .v_sync_out(v_sync_osd),                                 // to yuv2rgb
1122
    .pixel_en_out(pixel_en_osd),                             // to yuv2rgb
1123
    .osd_clt_rd_addr(osd_clt_rd_addr),                       // to osd color lookup table
1124
    .osd_clt_rd_en(osd_clt_rd_en),                           // to osd color lookup table
1125
    .osd_clt_rd_dta(osd_clt_rd_dta),                         // from osd color lookup table
1126
    .osd_enable(dot_osd_enable),                             // from regfile
1127
    .interlaced(dot_interlaced)                              // from regfile
1128
    );
1129
 
1130
  /* Luminance, chrominance to RGB conversion */
1131
  yuv2rgb yuv2rgb (
1132
    .clk(dot_clk),
1133
    .clk_en(1'b1),
1134
    .rst(dot_rst),
1135
    .matrix_coefficients(dot_matrix_coefficients),           // from vld
1136
    .y(y_osd),                                               // from osd
1137
    .u(u_osd),                                               // from osd
1138
    .v(v_osd),                                               // from osd
1139
    .h_sync_in(h_sync_osd),                                  // from osd
1140
    .v_sync_in(v_sync_osd),                                  // from osd
1141
    .pixel_en_in(pixel_en_osd),                              // from osd
1142
    .r(r),                                                   // to panellink transmitter
1143
    .g(g),                                                   // to panellink transmitter
1144
    .b(b),                                                   // to panellink transmitter
1145
    .y_out(y),                                               // to panellink transmitter
1146
    .u_out(u),                                               // to panellink transmitter
1147
    .v_out(v),                                               // to panellink transmitter
1148
    .h_sync_out(h_sync),                                     // to panellink transmitter
1149
    .v_sync_out(v_sync),                                     // to panellink transmitter
1150
    .c_sync_out(c_sync),                                     // to panellink transmitter
1151
    .pixel_en_out(pixel_en)                                  // to panellink transmitter
1152
    );
1153
 
1154
 /* OSD color look-up table */
1155
  osd_clt osd_clt (
1156
    .clk(clk),
1157
    .rst(sync_rst),
1158
    .osd_clt_wr_en(osd_clt_wr_en),                           // from register file.
1159
    .osd_clt_wr_addr(osd_clt_wr_addr),                       // from register file.
1160
    .osd_clt_wr_dta(osd_clt_wr_dta),                         // from register file.
1161
    .dot_clk(dot_clk),
1162
    .dot_rst(dot_rst),
1163
    .osd_clt_rd_addr(osd_clt_rd_addr),                       // from osd
1164
    .osd_clt_rd_en(osd_clt_rd_en),                           // from osd
1165
    .osd_clt_rd_dta(osd_clt_rd_dta)                          // to osd
1166
    );
1167
 
1168
  /* Register file */
1169
  regfile regfile (
1170
    .clk(clk),
1171
    .clk_en(1'b1),
1172
    .hard_rst(hard_rst),                                     // "hard" reset from rst input pin
1173
    .rst(sync_rst),                                          // "soft" reset from rst input pin or watchdog expiry
1174
    .reg_addr(reg_addr),                                     // register file. register address
1175
    .reg_wr_en(reg_wr_en),                                   // register file. register write enable
1176
    .reg_dta_in(reg_dta_in),                                 // register file. register write data
1177
    .reg_rd_en(reg_rd_en),                                   // register file. register read enable
1178
    .reg_dta_out(reg_dta_out),                               // register file. register read data
1179
    .progressive_sequence(progressive_sequence),             // from vld
1180
    .horizontal_size(horizontal_size),                       // from vld
1181
    .vertical_size(vertical_size),                           // from vld
1182
    .display_horizontal_size(display_horizontal_size),       // from vld
1183
    .display_vertical_size(display_vertical_size),           // from vld
1184
    .frame_rate_code(frame_rate_code),                       // from vld
1185
    .frame_rate_extension_n(frame_rate_extension_n),         // from vld
1186
    .frame_rate_extension_d(frame_rate_extension_d),         // from vld
1187
    .aspect_ratio_information(aspect_ratio_information),     // from vld
1188
    .mb_width(mb_width),                                     // from vld
1189
    .matrix_coefficients(matrix_coefficients),               // from vld
1190
    .update_picture_buffers(update_picture_buffers),         // from vld
1191
    .horizontal_resolution(horizontal_resolution),           // to syncgen
1192
    .horizontal_sync_start(horizontal_sync_start),           // to syncgen
1193
    .horizontal_sync_end(horizontal_sync_end),               // to syncgen
1194
    .horizontal_length(horizontal_length),                   // to syncgen
1195
    .vertical_resolution(vertical_resolution),               // to syncgen
1196
    .vertical_sync_start(vertical_sync_start),               // to syncgen
1197
    .vertical_sync_end(vertical_sync_end),                   // to syncgen
1198
    .horizontal_halfline(horizontal_halfline),               // to syncgen
1199
    .vertical_length(vertical_length),                       // to syncgen
1200
    .interlaced(interlaced),                                 // to syncgen
1201
    .clip_display_size(clip_display_size),                   // to syncgen
1202
    .pixel_repetition(pixel_repetition),                     // to syncgen
1203
    .syncgen_rst(syncgen_rst),                               // to syncgen
1204
 
1205
    .watchdog_interval(watchdog_interval),                   // to watchdog
1206
    .watchdog_interval_wr(watchdog_interval_wr),             // to watchdog
1207
    .watchdog_status_rd(watchdog_status_rd),                 // to watchdog
1208
    .watchdog_status(watchdog_status),                       // from watchdog
1209
 
1210
    .osd_enable(osd_enable),                                 // to osd
1211
    .osd_clt_wr_en(osd_clt_wr_en),                           // to osd color lookup table
1212
    .osd_clt_wr_addr(osd_clt_wr_addr),                       // to osd color lookup table
1213
    .osd_clt_wr_dta(osd_clt_wr_dta),                         // to osd color lookup table
1214
 
1215
    .osd_wr_full(osd_wr_full),                               // from osd framestore_writer
1216
    .osd_wr_en(osd_wr_en),                                   // to osd framestore_writer
1217
    .osd_wr_ack(osd_wr_ack),                                 // from osd framestore_writer
1218
    .osd_wr_addr(osd_wr_addr),                               // to osd framestore_writer
1219
    .osd_wr_dta(osd_wr_dta),                                 // to osd framestore_writer
1220
 
1221
    .deinterlace(deinterlace),                               // to resample
1222
    .repeat_frame(repeat_frame),                             // to motcomp_picbuf
1223
    .persistence(persistence),                               // to motcomp_picbuf
1224
    .source_select(source_select),                           // to motcomp_picbuf
1225
    .flush_vbuf(flush_vbuf),                                 // to framestore_request
1226
    .interrupt(interrupt),                                   // to interrupt pin
1227
    .error(),
1228
    .vld_err(vld_err),                                       // from vld
1229
    .v_sync(regfile_v_sync),                                 // from sync_gen
1230
    .testpoint_sel(testpoint_regfile),                       // to probe
1231
    .testpoint(regfile_testpoint)                            // from probe, synchronized to clk.
1232
    );
1233
 
1234
  /*
1235
   * Frame store
1236
   */
1237
 
1238
  framestore framestore (
1239
    .rst(sync_rst),
1240
    .clk(clk),
1241
    .mem_clk(mem_clk),
1242
    /* motion compensation: reading forward reference frame */
1243
    .fwd_rd_addr_empty(fwd_rd_addr_empty),
1244
    .fwd_rd_addr_en(fwd_rd_addr_en),
1245
    .fwd_rd_addr_valid(fwd_rd_addr_valid),
1246
    .fwd_rd_addr(fwd_rd_addr),
1247
    .fwd_wr_dta_full(fwd_wr_dta_full),
1248
    .fwd_wr_dta_almost_full(fwd_wr_dta_almost_full),
1249
    .fwd_wr_dta_en(fwd_wr_dta_en),
1250
    .fwd_wr_dta_ack(fwd_wr_dta_ack),
1251
    .fwd_wr_dta(fwd_wr_dta),
1252
    .fwd_rd_dta_almost_empty(fwd_rd_dta_almost_empty),
1253
    /* motion compensation: reading backward reference frame */
1254
    .bwd_rd_addr_empty(bwd_rd_addr_empty),
1255
    .bwd_rd_addr_en(bwd_rd_addr_en),
1256
    .bwd_rd_addr_valid(bwd_rd_addr_valid),
1257
    .bwd_rd_addr(bwd_rd_addr),
1258
    .bwd_wr_dta_full(bwd_wr_dta_full),
1259
    .bwd_wr_dta_almost_full(bwd_wr_dta_almost_full),
1260
    .bwd_wr_dta_en(bwd_wr_dta_en),
1261
    .bwd_wr_dta_ack(bwd_wr_dta_ack),
1262
    .bwd_wr_dta(bwd_wr_dta),
1263
    .bwd_rd_dta_almost_empty(bwd_rd_dta_almost_empty),
1264
    /* motion compensation: writing reconstructed frame */
1265
    .recon_rd_empty(recon_rd_empty),
1266
    .recon_rd_almost_empty(recon_rd_almost_empty),
1267
    .recon_rd_en(recon_rd_en),
1268
    .recon_rd_valid(recon_rd_valid),
1269
    .recon_rd_addr(recon_rd_addr),
1270
    .recon_rd_dta(recon_rd_dta),
1271
    .recon_wr_almost_full(recon_wr_almost_full),
1272
    /* display: reading reconstructed frame */
1273
    .disp_rd_addr_empty(disp_rd_addr_empty),
1274
    .disp_rd_addr_en(disp_rd_addr_en),
1275
    .disp_rd_addr_valid(disp_rd_addr_valid),
1276
    .disp_rd_addr(disp_rd_addr),
1277
    .disp_wr_dta_full(disp_wr_dta_full),
1278
    .disp_wr_dta_almost_full(disp_wr_dta_almost_full),
1279
    .disp_wr_dta_en(disp_wr_dta_en),
1280
    .disp_wr_dta_ack(disp_wr_dta_ack),
1281
    .disp_wr_dta(disp_wr_dta),
1282
    .disp_rd_dta_almost_empty(disp_rd_dta_almost_empty),
1283
    /* regfile: writing on-screen display */
1284
    .osd_rd_empty(osd_rd_empty),
1285
    .osd_rd_almost_empty(osd_rd_almost_empty),
1286
    .osd_rd_en(osd_rd_en),
1287
    .osd_rd_valid(osd_rd_valid),
1288
    .osd_rd_addr(osd_rd_addr),
1289
    .osd_rd_dta(osd_rd_dta),
1290
    .osd_wr_almost_full(osd_wr_almost_full),
1291
    /* writing to circular video buffer */
1292
    .vbw_rd_empty(vbw_rd_empty),
1293
    .vbw_rd_almost_empty(vbw_rd_almost_empty),
1294
    .vbw_rd_en(vbw_rd_en),
1295
    .vbw_rd_valid(vbw_rd_valid),
1296
    .vbw_rd_dta(vbw_rd_dta),
1297
    .vbw_wr_almost_full(vbw_wr_almost_full),
1298
    .vb_flush(flush_vbuf),
1299
    /* reading from circular video buffer */
1300
    .vbr_wr_full(vbr_wr_full),
1301
    .vbr_wr_almost_full(vbr_wr_almost_full),
1302
    .vbr_wr_dta(vbr_wr_dta),
1303
    .vbr_wr_en(vbr_wr_en),
1304
    .vbr_wr_ack(vbr_wr_ack),
1305
    .vbr_rd_almost_empty(vbr_rd_almost_empty),
1306
    /* memory controller interface */
1307
    .mem_req_wr_almost_full(mem_req_wr_almost_full),
1308
    .mem_req_wr_full(mem_req_wr_full),
1309
    .mem_req_wr_overflow(mem_req_wr_overflow),
1310
    .mem_req_rd_cmd(mem_req_rd_cmd),
1311
    .mem_req_rd_addr(mem_req_rd_addr),
1312
    .mem_req_rd_dta(mem_req_rd_dta),
1313
    .mem_req_rd_en(mem_req_rd_en),
1314
    .mem_req_rd_valid(mem_req_rd_valid),
1315
    .mem_res_wr_dta(mem_res_wr_dta),
1316
    .mem_res_wr_en(mem_res_wr_en),
1317
    .mem_res_wr_almost_full(mem_res_wr_almost_full),
1318
    .mem_res_wr_full(mem_res_wr_full),
1319
    .mem_res_wr_overflow(mem_res_wr_overflow),
1320
    /* tag fifo status for probe */
1321
    .tag_wr_almost_full(tag_wr_almost_full),
1322
    .tag_wr_full(tag_wr_full),
1323
    .tag_wr_overflow(tag_wr_overflow)
1324
    );
1325
 
1326
  /*
1327
   * Interface with frame store is through fifo's.
1328
   */
1329
 
1330
  /*
1331
   * fifo between motion compensation and frame store:
1332
   * reading forward reference frame.
1333
   */
1334
 
1335
  framestore_reader
1336
    #(.fifo_addr_depth(FWD_ADDR_DEPTH),
1337
    .fifo_dta_depth(FWD_DTA_DEPTH),
1338
    .fifo_addr_threshold(FWD_ADDR_THRESHOLD), // same value for fifo_threshold fwd_reader, bwd_reader and prog_thresh dst_fifo
1339
    .fifo_dta_threshold(FWD_DTA_THRESHOLD)) // same value for fifo_threshold fwd_reader, bwd_reader and prog_thresh dst_fifo
1340
    fwd_reader (
1341
    .rst(sync_rst),
1342
    .clk(clk),
1343
    .wr_addr_clk_en(fwd_wr_addr_clk_en),
1344
    .wr_addr_full(fwd_wr_addr_full),
1345
    .wr_addr_almost_full(fwd_wr_addr_almost_full),
1346
    .wr_addr_en(fwd_wr_addr_en),
1347
    .wr_addr_ack(fwd_wr_addr_ack),
1348
    .wr_addr(fwd_wr_addr),
1349
    .wr_addr_overflow(fwd_wr_addr_overflow),
1350
    .rd_dta_clk_en(fwd_rd_dta_clk_en),
1351
    .rd_dta_almost_empty(fwd_rd_dta_almost_empty),
1352
    .rd_dta_empty(fwd_rd_dta_empty),
1353
    .rd_dta_en(fwd_rd_dta_en),
1354
    .rd_dta_valid(fwd_rd_dta_valid),
1355
    .rd_dta(fwd_rd_dta),
1356
    .rd_addr_empty(fwd_rd_addr_empty),
1357
    .rd_addr_en(fwd_rd_addr_en),
1358
    .rd_addr_valid(fwd_rd_addr_valid),
1359
    .rd_addr(fwd_rd_addr),
1360
    .wr_dta_full(fwd_wr_dta_full),
1361
    .wr_dta_almost_full(fwd_wr_dta_almost_full),
1362
    .wr_dta_en(fwd_wr_dta_en),
1363
    .wr_dta_ack(fwd_wr_dta_ack),
1364
    .wr_dta(fwd_wr_dta),
1365
    .wr_dta_overflow(fwd_wr_dta_overflow)
1366
    );
1367
 
1368
  /*
1369
   * fifo between motion compensation and frame store:
1370
   * reading backward reference frame.
1371
   */
1372
 
1373
  framestore_reader
1374
    #(.fifo_addr_depth(BWD_ADDR_DEPTH),
1375
    .fifo_dta_depth(BWD_DTA_DEPTH),
1376
    .fifo_addr_threshold(BWD_ADDR_THRESHOLD), // same value for fifo_threshold fwd_reader, bwd_reader and prog_thresh dst_fifo
1377
    .fifo_dta_threshold(BWD_DTA_THRESHOLD)) // same value for fifo_threshold fwd_reader, bwd_reader and prog_thresh dst_fifo
1378
    bwd_reader (
1379
    .rst(sync_rst),
1380
    .clk(clk),
1381
    .wr_addr_clk_en(bwd_wr_addr_clk_en),
1382
    .wr_addr_full(bwd_wr_addr_full),
1383
    .wr_addr_almost_full(bwd_wr_addr_almost_full),
1384
    .wr_addr_en(bwd_wr_addr_en),
1385
    .wr_addr(bwd_wr_addr),
1386
    .wr_addr_ack(bwd_wr_addr_ack),
1387
    .wr_addr_overflow(bwd_wr_addr_overflow),
1388
    .rd_dta_clk_en(bwd_rd_dta_clk_en),
1389
    .rd_dta_almost_empty(bwd_rd_dta_almost_empty),
1390
    .rd_dta_empty(bwd_rd_dta_empty),
1391
    .rd_dta_en(bwd_rd_dta_en),
1392
    .rd_dta_valid(bwd_rd_dta_valid),
1393
    .rd_dta(bwd_rd_dta),
1394
    .rd_addr_empty(bwd_rd_addr_empty),
1395
    .rd_addr_en(bwd_rd_addr_en),
1396
    .rd_addr_valid(bwd_rd_addr_valid),
1397
    .rd_addr(bwd_rd_addr),
1398
    .wr_dta_full(bwd_wr_dta_full),
1399
    .wr_dta_almost_full(bwd_wr_dta_almost_full),
1400
    .wr_dta_en(bwd_wr_dta_en),
1401
    .wr_dta_ack(bwd_wr_dta_ack),
1402
    .wr_dta(bwd_wr_dta),
1403
    .wr_dta_overflow(bwd_wr_dta_overflow)
1404
    );
1405
 
1406
  /*
1407
   * fifo between motion compensation and frame store:
1408
   * writing reconstructed frame.
1409
   */
1410
 
1411
  framestore_writer
1412
    #(.fifo_depth(RECON_DEPTH),
1413
    .fifo_threshold(RECON_THRESHOLD))
1414
    recon_writer (
1415
    .rst(sync_rst),
1416
    .clk(clk),
1417
    .clk_en(1'b1),
1418
    .wr_full(recon_wr_full),
1419
    .wr_almost_full(recon_wr_almost_full),
1420
    .wr_en(recon_wr_en),
1421
    .wr_ack(recon_wr_ack),
1422
    .wr_addr(recon_wr_addr),
1423
    .wr_dta(recon_wr_dta),
1424
    .wr_overflow(recon_wr_overflow),
1425
    .rd_empty(recon_rd_empty),
1426
    .rd_almost_empty(recon_rd_almost_empty),
1427
    .rd_en(recon_rd_en),
1428
    .rd_valid(recon_rd_valid),
1429
    .rd_addr(recon_rd_addr),
1430
    .rd_dta(recon_rd_dta)
1431
    );
1432
 
1433
  /*
1434
   * fifo between chroma resampling and frame store:
1435
   * reading reconstructed frames.
1436
   */
1437
 
1438
  framestore_reader
1439
    #(.fifo_addr_depth(DISP_ADDR_DEPTH),
1440
    .fifo_dta_depth(DISP_DTA_DEPTH),
1441
    .fifo_addr_threshold(DISP_ADDR_THRESHOLD),
1442
    .fifo_dta_threshold(DISP_DTA_THRESHOLD))
1443
    disp_reader (
1444
    .rst(sync_rst),
1445
    .clk(clk),
1446
    .wr_addr_clk_en(1'b1),
1447
    .wr_addr_full(disp_wr_addr_full),
1448
    .wr_addr_almost_full(disp_wr_addr_almost_full),
1449
    .wr_addr_en(disp_wr_addr_en),
1450
    .wr_addr_ack(disp_wr_addr_ack),
1451
    .wr_addr(disp_wr_addr),
1452
    .wr_addr_overflow(disp_wr_addr_overflow),
1453
    .rd_dta_clk_en(1'b1),
1454
    .rd_dta_almost_empty(disp_rd_dta_almost_empty),
1455
    .rd_dta_empty(disp_rd_dta_empty),
1456
    .rd_dta_en(disp_rd_dta_en),
1457
    .rd_dta_valid(disp_rd_dta_valid),
1458
    .rd_dta(disp_rd_dta),
1459
    .rd_addr_empty(disp_rd_addr_empty),
1460
    .rd_addr_en(disp_rd_addr_en),
1461
    .rd_addr_valid(disp_rd_addr_valid),
1462
    .rd_addr(disp_rd_addr),
1463
    .wr_dta_full(disp_wr_dta_full),
1464
    .wr_dta_almost_full(disp_wr_dta_almost_full),
1465
    .wr_dta_en(disp_wr_dta_en),
1466
    .wr_dta_ack(disp_wr_dta_ack),
1467
    .wr_dta(disp_wr_dta),
1468
    .wr_dta_overflow(disp_wr_dta_overflow)
1469
    );
1470
 
1471
  /*
1472
   * fifo between register file and frame store:
1473
   * writing on-screen display
1474
   */
1475
 
1476
  framestore_writer
1477
    #(.fifo_depth(OSD_DEPTH),
1478
    .fifo_threshold(OSD_THRESHOLD))
1479
    osd_writer (
1480
    .rst(sync_rst),
1481
    .clk(clk),
1482
    .clk_en(1'b1),
1483
    .wr_full(osd_wr_full),
1484
    .wr_almost_full(osd_wr_almost_full),
1485
    .wr_en(osd_wr_en),
1486
    .wr_ack(osd_wr_ack),
1487
    .wr_addr(osd_wr_addr),
1488
    .wr_dta(osd_wr_dta),
1489
    .wr_overflow(osd_wr_overflow),
1490
    .rd_empty(osd_rd_empty),
1491
    .rd_almost_empty(osd_rd_almost_empty),
1492
    .rd_en(osd_rd_en),
1493
    .rd_valid(osd_rd_valid),
1494
    .rd_addr(osd_rd_addr),
1495
    .rd_dta(osd_rd_dta)
1496
    );
1497
 
1498
 /*
1499
  * Watchdog timer
1500
  */
1501
 
1502
  watchdog watchdog (
1503
    .clk(clk),
1504
    .hard_rst(hard_rst),
1505
    .source_select(source_select),
1506
    .repeat_frame(repeat_frame),
1507
    .busy(busy),
1508
    .watchdog_rst(watchdog_rst),
1509
    .watchdog_interval(watchdog_interval),                   // from regfile
1510
    .watchdog_interval_wr(watchdog_interval_wr),             // from regfile
1511
    .watchdog_status_rd(watchdog_status_rd),                 // from regfile
1512
    .watchdog_status(watchdog_status)                        // to regfile
1513
    );
1514
 
1515
  /*
1516
   * logical analyzer test point
1517
   */
1518
 
1519
  probe probe (
1520
    .clk(clk),
1521
    .mem_clk(mem_clk),
1522
    .dot_clk(dot_clk),
1523
    .sync_rst(sync_rst),
1524
    .mem_rst(mem_rst),
1525
    .dot_rst(dot_rst),
1526
    .testpoint(testpoint),
1527
    .testpoint_regfile(testpoint_regfile),
1528
    .testpoint_dip(testpoint_dip),
1529
    .testpoint_dip_en(testpoint_dip_en),
1530
    /* program stream in */
1531
    .stream_data(stream_data),
1532
    .stream_valid(stream_valid),
1533
    .busy(busy),
1534
    /* getbits in */
1535
    .vbr_rd_dta(vbr_rd_dta),
1536
    .vbr_rd_en(vbr_rd_en),
1537
    .vbr_rd_valid(vbr_rd_valid),
1538
    .advance(advance),
1539
    .align(align),
1540
    /* vld in */
1541
    .getbits(getbits),
1542
    .signbit(signbit),
1543
    .getbits_valid(getbits_valid),
1544
    /* vld out */
1545
    .vld_en(vld_en),
1546
    .error(error),
1547
    .motcomp_busy(motcomp_busy),
1548
    /* rld in */
1549
    .dct_coeff_wr_run(dct_coeff_wr_run),
1550
    .dct_coeff_wr_signed_level(dct_coeff_wr_signed_level),
1551
    .dct_coeff_wr_end(dct_coeff_wr_end),
1552
    .rld_wr_en(rld_wr_en),
1553
    /* regfile */
1554
    .reg_addr(reg_addr),
1555
    .reg_wr_en(reg_wr_en),
1556
    .reg_dta_in(reg_dta_in),
1557
    .reg_rd_en(reg_rd_en),
1558
    .reg_dta_out(reg_dta_out),
1559
    /* watchdog */
1560
    .watchdog_rst(watchdog_rst),
1561
    /* fifo's @ clk */
1562
    .bwd_wr_addr_almost_full(bwd_wr_addr_almost_full),
1563
    .bwd_wr_addr_full(bwd_wr_addr_full),
1564
    .bwd_wr_addr_overflow(bwd_wr_addr_overflow),
1565
    .bwd_rd_addr_empty(bwd_rd_addr_empty),
1566
    .bwd_wr_dta_almost_full(bwd_wr_dta_almost_full),
1567
    .bwd_wr_dta_full(bwd_wr_dta_full),
1568
    .bwd_wr_dta_overflow(bwd_wr_dta_overflow),
1569
    .bwd_rd_dta_empty(bwd_rd_dta_empty),
1570
    .disp_wr_addr_almost_full(disp_wr_addr_almost_full),
1571
    .disp_wr_addr_full(disp_wr_addr_full),
1572
    .disp_wr_addr_overflow(disp_wr_addr_overflow),
1573
    .disp_rd_addr_empty(disp_rd_addr_empty),
1574
    .disp_wr_dta_almost_full(disp_wr_dta_almost_full),
1575
    .disp_wr_dta_full(disp_wr_dta_full),
1576
    .disp_wr_dta_overflow(disp_wr_dta_overflow),
1577
    .disp_rd_dta_empty(disp_rd_dta_empty),
1578
    .fwd_wr_addr_almost_full(fwd_wr_addr_almost_full),
1579
    .fwd_wr_addr_full(fwd_wr_addr_full),
1580
    .fwd_wr_addr_overflow(fwd_wr_addr_overflow),
1581
    .fwd_rd_addr_empty(fwd_rd_addr_empty),
1582
    .fwd_wr_dta_almost_full(fwd_wr_dta_almost_full),
1583
    .fwd_wr_dta_full(fwd_wr_dta_full),
1584
    .fwd_wr_dta_overflow(fwd_wr_dta_overflow),
1585
    .fwd_rd_dta_empty(fwd_rd_dta_empty),
1586
    .dct_block_wr_overflow(dct_block_wr_overflow),
1587
    .frame_idct_wr_overflow(frame_idct_wr_overflow),
1588
    .idct_fifo_almost_full(idct_fifo_almost_full),
1589
    .idct_fifo_overflow(idct_fifo_overflow),
1590
    .idct_rd_dta_empty(idct_rd_dta_empty),
1591
    .mvec_wr_almost_full(mvec_wr_almost_full),
1592
    .mvec_wr_overflow(mvec_wr_overflow),
1593
    .dst_wr_overflow(dst_wr_overflow),
1594
    .mem_req_wr_almost_full(mem_req_wr_almost_full),
1595
    .mem_req_wr_full(mem_req_wr_full),
1596
    .mem_req_wr_overflow(mem_req_wr_overflow),
1597
    .osd_wr_full(osd_wr_full),
1598
    .osd_wr_overflow(osd_wr_overflow),
1599
    .osd_rd_empty(osd_rd_empty),
1600
    .resample_wr_overflow(resample_wr_overflow),
1601
    .pixel_wr_almost_full(pixel_wr_almost_full),
1602
    .pixel_wr_full(pixel_wr_full),
1603
    .pixel_wr_overflow(pixel_wr_overflow),
1604
    .pixel_rd_empty(pixel_rd_empty_pqueue),
1605
    .recon_wr_almost_full(recon_wr_almost_full),
1606
    .recon_wr_full(recon_wr_full),
1607
    .recon_wr_overflow(recon_wr_overflow),
1608
    .recon_rd_empty(recon_rd_empty),
1609
    .rld_wr_almost_full(rld_wr_almost_full),
1610
    .rld_wr_overflow(rld_wr_overflow),
1611
    .tag_wr_almost_full(tag_wr_almost_full),
1612
    .tag_wr_full(tag_wr_full),
1613
    .tag_wr_overflow(tag_wr_overflow),
1614
    .vbr_wr_almost_full(vbr_wr_almost_full),
1615
    .vbr_wr_full(vbr_wr_full),
1616
    .vbr_wr_overflow(vbr_wr_overflow),
1617
    .vbr_rd_empty(vbr_rd_empty),
1618
    .vbw_wr_almost_full(vbw_wr_almost_full),
1619
    .vbw_wr_full(vbw_wr_full),
1620
    .vbw_wr_overflow(vbw_wr_overflow),
1621
    .vbw_rd_empty(vbw_rd_empty),
1622
    /* fifo's @ mem_clk */
1623
    .mem_req_rd_en(mem_req_rd_en),
1624
    .mem_req_rd_valid(mem_req_rd_valid),
1625
    .mem_res_wr_en(mem_res_wr_en),
1626
    .mem_res_wr_almost_full(mem_res_wr_almost_full),
1627
    .mem_res_wr_full(mem_res_wr_full),
1628
    .mem_res_wr_overflow(mem_res_wr_overflow),
1629
    /* motion comp */
1630
    .macroblock_address(macroblock_address),
1631
    .macroblock_motion_forward(macroblock_motion_forward),
1632
    .macroblock_motion_backward(macroblock_motion_backward),
1633
    .macroblock_intra(macroblock_intra),
1634
    .second_field(second_field),
1635
    .update_picture_buffers(update_picture_buffers),
1636
    .last_frame(last_frame),
1637
    .motion_vector_valid(motion_vector_valid),
1638
    /* output frame */
1639
    .output_frame(output_frame),
1640
    .output_frame_valid(output_frame_valid),
1641
    .output_frame_rd(output_frame_rd),
1642
    .output_progressive_sequence(output_progressive_sequence),
1643
    .output_progressive_frame(output_progressive_frame),
1644
    .output_top_field_first(output_top_field_first),
1645
    .output_repeat_first_field(output_repeat_first_field),
1646
    /* osd writes */
1647
    .osd_wr_en(osd_wr_en),
1648
    .osd_wr_ack(osd_wr_ack),
1649
    .osd_wr_addr(osd_wr_addr),
1650
    /* yuv video in */
1651
    .y(y),
1652
    .u(u),
1653
    .v(v),
1654
    .pixel_en(pixel_en),
1655
    .h_sync(h_sync),
1656
    .v_sync(v_sync)
1657
    );
1658
 
1659
`ifdef CHECK
1660
  always @(posedge clk)
1661
    if (vbw_wr_overflow)
1662
      begin
1663
        #0 $display("%m\t*** error: vbw_wr_overflow overflow. **");
1664
        $stop;
1665
      end
1666
 
1667
  always @(posedge clk)
1668
    if (vbr_wr_overflow)
1669
      begin
1670
        #0 $display("%m\t*** error: vbr_wr_overflow overflow. **");
1671
        $stop;
1672
      end
1673
 
1674
`endif
1675
 
1676
endmodule
1677
/* not truncated */

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