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/*

 * mpeg2video.v

 *

 * Copyright (c) 2007 Koen De Vleeschauwer.

 *

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND

 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

 * SUCH DAMAGE.

 */

/*

 *

 * MPEG-2 License Notice

 *

 * Commercial implementations of MPEG-1 and MPEG-2 video, including shareware,

 * are subject to royalty fees to patent holders.  Many of these patents are

 * general enough such that they are unavoidable regardless of implementation

 * design.

 *

 * "MPEG-2 INTERMEDIATE PRODUCT. USE OF THIS PRODUCT IN ANY MANNER THAT COMPLIES

 * WITH THE MPEG-2 STANDARD IS EXPRESSLY PROHIBITED WITHOUT A LICENSE UNDER

 * APPLICABLE PATENTS IN THE MPEG-2 PATENT PORTFOLIO, WHICH LICENSE IS AVAILABLE

 * FROM MPEG LA, L.L.C., 250 STELLE STREET, SUITE 300, DENVER, COLORADO 80206."

 *

 */

/*

 * mpeg2 decoder.

 *

 * Input:

 *   stream_data:  video elementary stream

 * Output:

 *   r, g, b, pixel_en, h_sync, v_sync: rgb values and video synchronisation

 */

`include "timescale.v"

`undef CHECK

`ifdef __IVERILOG__

`define CHECK 1

`endif

module mpeg2video(clk, mem_clk, dot_clk,

             rst,                                                                                                                 // clocked with clk

             stream_data, stream_valid,                                                                                           // clocked with clk

             reg_addr, reg_wr_en, reg_dta_in, reg_rd_en, reg_dta_out,                                                             // clocked with clk

             busy, error, interrupt, watchdog_rst,                                                                                // clocked with clk

             r, g, b, y, u, v, pixel_en, h_sync, v_sync, c_sync,                                                                  // clocked with dot_clk

             mem_req_rd_cmd, mem_req_rd_addr, mem_req_rd_dta, mem_req_rd_en, mem_req_rd_valid,                                    // clocked with mem_clk

             mem_res_wr_dta, mem_res_wr_en, mem_res_wr_almost_full,                                                               // clocked with mem_clk

             testpoint_dip, testpoint_dip_en, testpoint

             );

  input            clk;                     // clock. Typically a multiple of 27 Mhz as MPEG2 timestamps have a 27 Mhz resolution.

  input            mem_clk;                 // memory clock. Typically 133-166 MHz.

  input            dot_clk;                 // video clock. Typically between 25 and 75 Mhz, depending upon MPEG2 resolution and frame rate.

  input            rst;                     // active low reset. Internally synchronized.

  /* MPEG stream input */

  input       [7:0]stream_data;             // packetized elementary stream input

  input            stream_valid;            // stream_data valid

  /* RGB output */

  output      [7:0]r;                       // red component

  output      [7:0]g;                       // green component

  output      [7:0]b;                       // blue component

  output      [7:0]y;                       // luminance 

  output      [7:0]u;                       // chrominance

  output      [7:0]v;                       // chrominance

  output           pixel_en;                // pixel enable - asserted if r, g and b valid.

  output           h_sync;                  // horizontal synchronisation

  output           v_sync;                  // vertical synchronisation

  output           c_sync;                  // composite synchronisation

  /* register file access */

  input       [3:0]reg_addr;

  input      [31:0]reg_dta_in;

  input            reg_wr_en;

  output     [31:0]reg_dta_out;

  input            reg_rd_en;

  output reg       busy;                    // assert busy when input fifo risks overflow

  output           error;

  output           interrupt;               // asserted when image size changes, or when vld error occurs. cleared when status register read.

  /* memory controller interface */

  output      [1:0]mem_req_rd_cmd;

  output     [21:0]mem_req_rd_addr;

  output     [63:0]mem_req_rd_dta;

  input            mem_req_rd_en;

  output           mem_req_rd_valid;

  input      [63:0]mem_res_wr_dta;

  input            mem_res_wr_en;

  output           mem_res_wr_almost_full;

  wire             mem_res_wr_full;

  /* logical analyzer test point */

  input       [3:0]testpoint_dip;

  input            testpoint_dip_en;

  output     [33:0]testpoint;

  wire        [3:0]testpoint_regfile;

  /* reset signals */

  wire             sync_rst;                // reset, either from rst input pin or watchdog, synchronized to clk

  wire             mem_rst;                 // reset, either from rst input pin or watchdog, synchronized to mem_clk

  wire             dot_rst;                 // reset, either from rst input pin or watchdog, synchronized to dot_clk

  wire             hard_rst;                // reset, only from rst input, synchronized to clk

  /* watchdog timer */

  output           watchdog_rst;            // low when watchdog timer expires.

  wire        [7:0]watchdog_interval;       // new value of the watchdog interval. 255 = never expire; 0 = expire immediate. 

  wire             watchdog_interval_wr;    // asserted when the watchdog interval is written 

  wire             watchdog_status_rd;      // asserted when the watchdog status is read 

  wire             watchdog_status;         // high if watchdog timer has expired

  /* vbuf_write - vbw fifo interface */

  wire  [63:0]vbw_wr_dta;

  wire        vbw_wr_en;

  wire        vbw_wr_full;

  wire        vbw_wr_almost_full;

  /* vbw fifo - framestore interface */

  wire  [63:0]vbw_rd_dta;

  wire        vbw_rd_en;

  wire        vbw_rd_valid;

  wire        vbw_rd_empty;

  wire        vbw_rd_almost_empty;

  /* framestore - vbr fifo interface */

  wire  [63:0]vbr_wr_dta;

  wire        vbr_wr_en;

  wire        vbr_wr_ack;

  wire        vbr_wr_full;

  wire        vbr_wr_almost_full;

  /* vbr fifo - getbits fifo interface */

  wire  [63:0]vbr_rd_dta;

  wire        vbr_rd_en;

  wire        vbr_rd_valid;

  wire        vbr_rd_almost_empty;

  wire        vbr_rd_empty;

  /* getbits_fifo - vld interface */

  wire  [4:0]advance;                       // number of bits to advance the bitstream (advance <= 24)   

  wire       align;                         // byte-align getbits and move forward one byte.

  wire [23:0]getbits;                       // elementary stream data. 

  wire       signbit;                       // sign bit, used when decoding dct variable length codes.

  wire       getbits_valid;                 // getbits_valid is asserted when getbits is valid.

  wire       wait_state;                    // after vld requesting getbits to advance or align, vld should wait one cycle for getbits to process the request.

  wire       vld_en;                        // enable vld when getbits, rld, motcomp not busy, and not a wait state 

  /* vld - rld_fifo interface */

  wire  [5:0]dct_coeff_wr_run;              // dct coefficient runlength, from vlc decoding

  wire [11:0]dct_coeff_wr_signed_level;     // dct coefficient level, 2's complement format, from vlc decoding

  wire       dct_coeff_wr_end;              // dct_coeff_end_in is asserted at end of block 

  wire       rld_wr_almost_full;            // rld fifo almost full signal; used as throttle for vld 

  wire       rld_wr_en;                     // rld fifo write enable

  wire       rld_wr_overflow;               // rld fifo write overflow

  wire  [1:0]rld_cmd_wr;                    // rld command (dct run/level code or quantizer matrix update)

  wire  [4:0]quantiser_scale_code;

  wire       alternate_scan;

  wire       q_scale_type;                  // quantizer scale type

  wire       macroblock_intra;

  wire  [1:0]intra_dc_precision;

  wire  [7:0]quant_wr_data_wr;              // data bus for writing quantizer matrix rams

  wire  [5:0]quant_wr_addr_wr;              // address bus for writing quantizer matrix rams

  wire       quant_rst_wr;                  // reset quantizer matrix to default values

  wire       quant_wr_intra_wr;             // write enable for intra quantiser matrix

  wire       quant_wr_non_intra_wr;         // write enable for non intra quantiser matrix

  wire       quant_wr_chroma_intra_wr;      // write enable for chroma intra quantiser matrix

  wire       quant_wr_chroma_non_intra_wr;  // write enable for chroma non intra quantiser matrix

  /* rld_fifo - rld interface */

  wire  [5:0]dct_coeff_rd_run;              // dct coefficient runlength, from vlc decoding

  wire [11:0]dct_coeff_rd_signed_level;     // dct coefficient level, 2's complement format, from vlc decoding

  wire       dct_coeff_rd_end;              // dct_coeff_end_out is asserted at end of block 

  wire       alternate_scan_rd;

  wire       q_scale_type_rd;               // quantizer scale type

  wire       macroblock_intra_rd;

  wire  [1:0]intra_dc_precision_rd;

  wire  [4:0]quantiser_scale_code_rd;

  wire  [7:0]quant_wr_data_rd;              // data bus for writing quantizer matrix rams

  wire  [5:0]quant_wr_addr_rd;              // address bus for writing quantizer matrix rams

  wire       quant_rst_rd;                  // reset quantizer matrix to default values

  wire       quant_wr_intra_rd;             // write enable for intra quantiser matrix

  wire       quant_wr_non_intra_rd;         // write enable for non intra quantiser matrix

  wire       quant_wr_chroma_intra_rd;      // write enable for chroma intra quantiser matrix

  wire       quant_wr_chroma_non_intra_rd;  // write enable for chroma non intra quantiser matrix

  wire  [1:0]rld_cmd_rd;

  wire       rld_rd_en;                     // rld fifo read enable

  wire       rld_rd_valid;                  // asserted when fifo outputs are valid

  /* quantiser ram - rld interface */

  wire       quant_rst;                     // reset quantizer matrix to default values

  wire  [5:0]quant_rd_addr;                 // address bus for reading quantizer matrix rams

  wire  [7:0]quant_rd_intra_data;           // data bus for reading quantizer matrix rams

  wire  [7:0]quant_rd_non_intra_data;       // data bus for reading quantizer matrix rams

  wire  [7:0]quant_wr_data;                 // data bus for writing quantizer matrix rams

  wire  [5:0]quant_wr_addr;                 // address bus for writing quantizer matrix rams

  wire       quant_wr_en_intra;             // write enable for intra quantiser matrix

  wire       quant_wr_en_non_intra;         // write enable for non intra quantiser matrix

  wire       quant_wr_en_chroma_intra;      // write enable for chroma intra quantiser matrix

  wire       quant_wr_en_chroma_non_intra;  // write enable for chroma non intra quantiser matrix

  wire       quant_alternate_scan;          // alternate scan

  /* idct - rld interface */

  wire [11:0]iquant_level;                  // inverse quantized dct coefficient

  wire       iquant_eob;                    // asserted at last inverse quantized dct coefficient of block

  wire       iquant_valid;                  // asserted when inverse quantized dct coefficient valid

  /* idct - idct_fifo interface */

  wire  [8:0]idct_data;

  wire       idct_eob;

  wire       idct_valid;

  /* idct_fifo - motcomp interface */

  wire             idct_fifo_almost_full;

  wire             idct_fifo_overflow;

  wire             idct_rd_dta_valid;

  wire             idct_rd_dta_empty;

  wire             idct_rd_dta_en;

  wire       [71:0]idct_rd_dta;

  /* vld - motcomp interface */

  wire         [2:0]picture_coding_type;

  wire         [1:0]picture_structure;

  wire         [1:0]motion_type;

  wire              dct_type;

  wire        [12:0]macroblock_address;

  wire              macroblock_motion_forward;

  wire              macroblock_motion_backward;

  wire         [7:0]mb_width;

  wire         [7:0]mb_height;

  wire              motion_vert_field_select_0_0;

  wire              motion_vert_field_select_0_1;

  wire              motion_vert_field_select_1_0;

  wire              motion_vert_field_select_1_1;

  wire              second_field;

  wire              update_picture_buffers;

  wire              last_frame;

  wire         [1:0]chroma_format;

  wire              motion_vector_valid;    // asserted when pmv_x_x_x, dmv_x_x valid

  wire signed [12:0]pmv_0_0_0;              // predicted motion vector

  wire signed [12:0]pmv_0_0_1;              // predicted motion vector

  wire signed [12:0]pmv_1_0_0;              // predicted motion vector

  wire signed [12:0]pmv_1_0_1;              // predicted motion vector

  wire signed [12:0]pmv_0_1_0;              // predicted motion vector

  wire signed [12:0]pmv_0_1_1;              // predicted motion vector

  wire signed [12:0]pmv_1_1_0;              // predicted motion vector

  wire signed [12:0]pmv_1_1_1;              // predicted motion vector

  wire signed [12:0]dmv_0_0;                // dual-prime motion vector

  wire signed [12:0]dmv_0_1;                // dual-prime motion vector

  wire signed [12:0]dmv_1_0;                // dual-prime motion vector

  wire signed [12:0]dmv_1_1;                // dual-prime motion vector

  wire              mvec_wr_almost_full;    // asserted if motion vector fifo fills up; used for flow control

  /* motcomp output */

  wire             motcomp_busy;            // asserted when motcomp input fifo's full

  /* vld - syncgen interface */

  wire       [13:0]horizontal_size;         // horizontal size of frame

  wire       [13:0]vertical_size;           // vertical size of frame

  wire       [13:0]display_horizontal_size; // displayable part of frame. If non-zero, always less than horizontal_size.

  wire       [13:0]display_vertical_size;   // displayable part of frame. If non-zero, always less than vertical_size.

  /* syncgen - mixer interface */

  wire       [11:0]h_pos;                   // horizontal position; 0 = left

  wire       [11:0]v_pos;                   // vertical position; 0 = top

  wire             pixel_en_gen;            // pixel enable generated by syncgen

  wire             h_sync_gen;              // h_sync generated by syncgen

  wire             v_sync_gen;              // v_sync generated by syncgen

  /* vld - syncgen interface */

  wire        [7:0]matrix_coefficients;     // determines yuv to rgb conversion factors

  /* resample - pixel queue interface */

  wire        [7:0]y_resample;              // luminance

  wire        [7:0]u_resample;              // chrominance

  wire        [7:0]v_resample;              // chrominance

  wire        [7:0]osd_resample;            // osd pixel color 

  wire        [2:0]position_resample;       // position, as in resample_codes.v

  wire             pixel_wr_en;

  wire             pixel_wr_almost_full;

  wire             pixel_wr_full;

  wire             pixel_wr_overflow;

  /* pixel queue - pixel repetition interface */

  wire        [7:0]y_pqueue;                // luminance

  wire        [7:0]u_pqueue;                // chrominance

  wire        [7:0]v_pqueue;                // chrominance

  wire        [7:0]osd_pqueue;              // osd pixel color 

  wire        [2:0]position_pqueue;         // position, as in resample_codes.v

  wire             pixel_rd_en_pqueue;

  wire             pixel_rd_empty_pqueue;

  wire             pixel_rd_valid_pqueue;

  wire             pixel_rd_underflow_pqueue;

  /* mixer - osd interface */

  wire        [7:0]y_mixer;                 // luminance

  wire        [7:0]u_mixer;                 // chrominance

  wire        [7:0]v_mixer;                 // chrominance

  wire        [7:0]osd_mixer;               // osd pixel color 

  wire             h_sync_mixer;

  wire             v_sync_mixer;

  wire             pixel_en_mixer;

  /* osd - yuv2rgb interface */

  wire             pixel_en_osd;            // pixel enable 

  wire             h_sync_osd;              // h_sync 

  wire             v_sync_osd;              // v_sync

  wire        [7:0]y_osd;                   // luminance

  wire        [7:0]u_osd;                   // chrominance

  wire        [7:0]v_osd;                   // chrominance

  /* osd - osd_clt interface */

  wire        [7:0]osd_clt_rd_addr;

  wire             osd_clt_rd_en;

  wire       [31:0]osd_clt_rd_dta;

  /* regfile - osd_clt interface */

  wire             osd_clt_wr_en;

  wire        [7:0]osd_clt_wr_addr;

  wire       [31:0]osd_clt_wr_dta;

  /* regfile - osd interface */

  wire             osd_enable;

  /* vld - regfile interface */

  wire             vld_err;

  wire        [3:0]frame_rate_code;         // par. 6.3.3, Table 6-4

  wire        [1:0]frame_rate_extension_n;  // par. 6.3.3, par. 6.3.5

  wire        [4:0]frame_rate_extension_d;  // par. 6.3.3, par. 6.3.5

  wire        [3:0]aspect_ratio_information;// par. 6.3.3

  assign           error = vld_err;

  /* regfile - syncgen interface */

  wire [11:0]horizontal_resolution;         /* horizontal resolution. number of dots per line, minus one  */

  wire [11:0]horizontal_sync_start;         /* the dot the horizontal sync pulse begins. */

  wire [11:0]horizontal_sync_end;           /* the dot the horizontal sync pulse ends. */

  wire [11:0]horizontal_length;             /* total horizontal length */

  wire [11:0]vertical_resolution;           /* vertical resolution. number of visible lines per frame (progressive) or field (interlaced), minus one */

  wire [11:0]vertical_sync_start;           /* the line number within the frame (progressive) or field (interlaced) the vertical sync pulse begins. */

  wire [11:0]vertical_sync_end;             /* the line number within the frame (progressive) or field (interlaced) the vertical sync pulse ends. */

  wire [11:0]horizontal_halfline;           /* the dot the vertical sync begins on odd frames of interlaced video. Not used in progressive mode. */

  wire [11:0]vertical_length;               /* total number of lines of a vertical frame (progressive) or field (interlaced) */

  wire       interlaced;                    /* asserted if interlaced output required. */

  wire       pixel_repetition;              /* assert for dot clock rates < 25 MHz, repeats each pixel */

  wire       clip_display_size;             /* assert to clip image to (display_horizontal_size, display_vertical_size) */

  wire       syncgen_rst;                   /* resets sync generator whenever a modeline parameter changes */

  /* regfile - picbuf  interface */

  wire  [2:0]source_select;                 /* select video out source */

  /* regfile - resample interface */

  wire       deinterlace;                   /* assert if video has to be deinterlaced */

  wire  [4:0]repeat_frame;                  /* repeat decoded images */

  wire       persistence;                   /* last decoded image persists */

  /* motcomp - resample interface */

  wire  [2:0]output_frame;                  /* frame to be displayed */

  wire       output_frame_valid;            /* asserted when output_frame valid */

  wire       output_frame_rd;               /* asserted to read next output_frame */

  wire       output_progressive_sequence;

  wire       output_progressive_frame;

  wire       output_top_field_first;

  wire       output_repeat_first_field;

  /* vld - motcomp_picbuf interface */

  wire       progressive_sequence;

  wire       progressive_frame;

  wire       top_field_first;

  wire       repeat_first_field;

  /*

   * Interface with frame store is through fifo's.

   */

  /*

   * fifo between motion compensation and frame store:

   * reading forward reference frame.

   */

  wire       fwd_wr_addr_clk_en;

  wire       fwd_wr_addr_full;

  wire       fwd_wr_addr_almost_full;

  wire       fwd_wr_addr_en;

  wire       fwd_wr_addr_ack;

  wire [21:0]fwd_wr_addr;

  wire       fwd_rd_dta_clk_en;

  wire       fwd_rd_dta_almost_empty;

  wire       fwd_rd_dta_empty;

  wire       fwd_rd_dta_en;

  wire       fwd_rd_dta_valid;

  wire [63:0]fwd_rd_dta;

  wire       fwd_rd_addr_empty;

  wire       fwd_rd_addr_en;

  wire       fwd_rd_addr_valid;

  wire [21:0]fwd_rd_addr;

  wire       fwd_wr_dta_full;

  wire       fwd_wr_dta_almost_full;

  wire       fwd_wr_dta_en;

  wire       fwd_wr_dta_ack;

  wire [63:0]fwd_wr_dta;

  /*

   * fifo between motion compensation and frame store:

   * reading backward reference frame.

   */

  wire       bwd_wr_addr_clk_en;

  wire       bwd_wr_addr_full;

  wire       bwd_wr_addr_almost_full;

  wire       bwd_wr_addr_en;

  wire       bwd_wr_addr_ack;

  wire [21:0]bwd_wr_addr;

  wire       bwd_rd_dta_clk_en;

  wire       bwd_rd_dta_empty;

  wire       bwd_rd_dta_almost_empty;

  wire       bwd_rd_dta_en;

  wire       bwd_rd_dta_valid;

  wire [63:0]bwd_rd_dta;

  wire       bwd_rd_addr_empty;

  wire       bwd_rd_addr_en;

  wire       bwd_rd_addr_valid;

  wire [21:0]bwd_rd_addr;

  wire       bwd_wr_dta_full;

  wire       bwd_wr_dta_almost_full;

  wire       bwd_wr_dta_en;

  wire       bwd_wr_dta_ack;

  wire [63:0]bwd_wr_dta;

  /*

   * fifo between motion compensation and frame store:

   * writing reconstructed frame.

   */

  wire       recon_wr_full;

  wire       recon_wr_almost_full;

  wire       recon_wr_en;

  wire       recon_wr_ack;

  wire [21:0]recon_wr_addr;

  wire [63:0]recon_wr_dta;

  wire       recon_rd_empty;

  wire       recon_rd_almost_empty;

  wire       recon_rd_en;

  wire       recon_rd_valid;

  wire [21:0]recon_rd_addr;

  wire [63:0]recon_rd_dta;

  /*

   * fifo between chroma resampling and frame store:

   * reading reconstructed frames.

   */

  wire       disp_wr_addr_full;

  wire       disp_wr_addr_almost_full;

  wire       disp_wr_addr_en;

  wire       disp_wr_addr_ack;

  wire [21:0]disp_wr_addr;

  wire       disp_rd_dta_empty;

  wire       disp_rd_dta_almost_empty;

  wire       disp_rd_dta_en;

  wire       disp_rd_dta_valid;

  wire [63:0]disp_rd_dta;

  wire       disp_rd_addr_empty;

  wire       disp_rd_addr_en;

  wire       disp_rd_addr_valid;

  wire [21:0]disp_rd_addr;

  wire       disp_wr_dta_full;

  wire       disp_wr_dta_almost_full;

  wire       disp_wr_dta_en;

  wire       disp_wr_dta_ack;

  wire [63:0]disp_wr_dta;

  /*

   * fifo between register file and frame store:

   * writing on-screen display

   */

  wire       osd_wr_almost_full;

  wire       osd_wr_full;

  wire       osd_wr_en;

  wire       osd_wr_ack;

  wire [21:0]osd_wr_addr;

  wire [63:0]osd_wr_dta;

  wire       osd_rd_almost_empty;

  wire       osd_rd_empty;

  wire       osd_rd_en;

  wire       osd_rd_valid;

  wire [21:0]osd_rd_addr;

  wire [63:0]osd_rd_dta;

  /* more overflows */

  wire       mem_req_wr_almost_full;

  wire       mem_req_wr_full;

  wire       mem_req_wr_overflow;

  wire       tag_wr_almost_full;

  wire       tag_wr_full;

  wire       tag_wr_overflow;

  wire       mem_res_wr_overflow;

  wire       vbw_wr_overflow;

  wire       vbr_wr_overflow;

  wire       dct_block_wr_overflow;

  wire       frame_idct_wr_overflow;

  wire       mvec_wr_overflow;

  wire       dst_wr_overflow;

  wire       fwd_wr_addr_overflow;

  wire       fwd_wr_dta_overflow;

  wire       bwd_wr_addr_overflow;

  wire       bwd_wr_dta_overflow;

  wire       recon_wr_overflow;

  wire       resample_wr_overflow;

  wire       disp_wr_addr_overflow;

  wire       disp_wr_dta_overflow;

  wire       osd_wr_overflow;

`include "fifo_size.v"

  /*

   * assert "busy" at power-on, to allow dual-port rams such as

   * quantizer matrices and osd lookup-table to be cleared / initialized.

   */

  reg [8:0]init_cnt;

  always @(posedge clk)

    if (~sync_rst) init_cnt <= 9'h0;

    else init_cnt <= (init_cnt == 9'h1ff) ? init_cnt : init_cnt + 9'd1;

  always @(posedge clk)

    if (~sync_rst) busy <= 1'b1;

    else busy <= vbw_wr_almost_full || ~sync_rst || (init_cnt != 9'h1ff);

  /* reset signal synchronizers */

  reset reset (

    .clk(clk),

    .mem_clk(mem_clk),

    .dot_clk(dot_clk),

    .async_rst(rst),

    .watchdog_rst(watchdog_rst),

    .clk_rst(sync_rst),

    .mem_rst(mem_rst),

    .dot_rst(dot_rst),

    .hard_rst(hard_rst)

    );

  /* register synchronizers */

  wire  [7:0]dot_matrix_coefficients;

  wire       dot_interlaced;

  wire       dot_pixel_repetition;

  wire       dot_osd_enable;

  sync_reg #(.width(8))  sync_matrix_coefficients     (dot_clk, dot_rst, matrix_coefficients, dot_matrix_coefficients);

  sync_reg #(.width(1))  sync_interlaced              (dot_clk, dot_rst, interlaced, dot_interlaced);

  sync_reg #(.width(1))  sync_pixel_repetition        (dot_clk, dot_rst, pixel_repetition, dot_pixel_repetition);

  sync_reg #(.width(1))  sync_osd_enable              (dot_clk, dot_rst, osd_enable, dot_osd_enable);

  /* test point synchronizer, for reading test point via register file */

  wire [31:0]regfile_testpoint;

  sync_reg #(.width(32)) sync_testpoint               (clk, sync_rst, testpoint[31:0], regfile_testpoint); // Only pass on bits 31..0. bits 32 and 33 are likely to be clocks and clock enables.

  /* vertical sync synchronizer, for generating interrupt at vertical sync start */

  wire       regfile_v_sync;

  sync_reg #(.width(1))  sync_v_sync                  (clk, sync_rst, v_sync_gen, regfile_v_sync);

  /* flush video buffer */

  wire       flush_vbuf;                              /* flush video buffer */

  wire       vbuf_rst;                                /* circular video buffer reset signal, synchronized and at least three clocks long */

  sync_reset sync_vbuf_reset (

    .clk(clk),

    .asyncrst(rst && ~flush_vbuf),

    .syncrst(vbuf_rst)

    );

  /* write elementary stream to circular buffer */

  vbuf_write vbuf_write (

    .clk(clk),

    .clk_en(1'b1),

    .rst(sync_rst),

    .vid_in(stream_data),                                    // program stream input

    .vid_in_wr_en(stream_valid),                             // program stream input

    .vid_out(vbw_wr_dta),                                    // to vbuf_write_fifo

    .vid_out_wr_en(vbw_wr_en)                                // to vbuf_write_fifo

    );

  /* vbuf write fifo */

  fifo_sc

    #(.addr_width(VBUF_WR_DEPTH),

    .dta_width(9'd64),

    .prog_thresh(VBUF_WR_THRESHOLD))

    vbuf_write_fifo (

    .rst(vbuf_rst),

    .clk(clk),

    .din(vbw_wr_dta),                                        // from vbuf_write

    .wr_en(vbw_wr_en),                                       // from vbuf_write

    .wr_ack(),

    .full(vbw_wr_full),

    .overflow(vbw_wr_overflow),

    .dout(vbw_rd_dta),                                       // to framestore

    .rd_en(vbw_rd_en),                                       // to framestore

    .valid(vbw_rd_valid),                                    // to framestore

    .empty(vbw_rd_empty),                                    // to framestore

    .prog_empty(vbw_rd_almost_empty),                        // to framestore

    .prog_full(vbw_wr_almost_full),                          // to framestore and output pin "busy"

    .underflow()

    );

  /* vbuf read fifo */

  fifo_sc

    #(.addr_width(VBUF_RD_DEPTH),

    .dta_width(9'd64),

    .prog_thresh(VBUF_RD_THRESHOLD))

    vbuf_read_fifo (

    .rst(vbuf_rst),

    .clk(clk),

    .din(vbr_wr_dta),                                        // from framestore

    .wr_en(vbr_wr_en),                                       // from framestore

    .wr_ack(vbr_wr_ack),                                     // to framestore

    .full(vbr_wr_full),                                      // to framestore

    .overflow(vbr_wr_overflow),                              // to probe

    .dout(vbr_rd_dta),                                       // to getbits_fifo

    .rd_en(vbr_rd_en),                                       // from getbits_fifo

    .valid(vbr_rd_valid),                                    // to getbits_fifo

    .empty(vbr_rd_empty),                                    // to probe

    .prog_empty(vbr_rd_almost_empty),                        // to framestore

    .prog_full(vbr_wr_almost_full),                          // to framestore

    .underflow()

    );

  /* read elementary stream from circular buffer, one bitfield at a time */

  getbits_fifo getbits_fifo (

    .clk(clk),

    .clk_en(1'b1),

    .rst(sync_rst),

    .vid_in(vbr_rd_dta),                                     // from vbuf_read_fifo

    .vid_in_rd_en(vbr_rd_en),                                // to vbuf_read_fifo

    .vid_in_rd_valid(vbr_rd_valid),                          // from vbuf_read_fifo

    .advance(advance),                                       // from vld

    .align(align),                                           // from vld

    .wait_state(wait_state),                                 // from vld

    .rld_wr_almost_full(rld_wr_almost_full),                 // from rld fifo