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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [osd.v] - Blame information for rev 2

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/*
2
 * osd.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * osd.v - On-Screen Display
21
 */
22
 
23
`include "timescale.v"
24
 
25
`undef DEBUG
26
//`define DEBUG 1
27
 
28
/*
29
 * The On-Screen Display (OSD) is used for menus and user interaction.
30
 * It offers a palette of 256 24-bit colors, transparency and blinking.
31
 * The osd has the same resolution as the mpeg video being shown.
32
 *
33
 * Each osd pixel is looked up in the osd color lookup table.
34
 * The osd color lookup table returns, for every 8-bit osd pixel, 32 bits:
35
 *   y (8 bit), u (8 bit), v(8 bit), m(8 bit).
36
 * y, u, and v are the luma and chroma values of the osd color.
37
 * m is the osd color mode, and determines the displayed pixel according
38
 * to the following table:
39
 *   m (mode)
40
 *   xxx00000: alpha = 0/16
41
 *   xxx00001: alpha = 1/16
42
 *   xxx00010: alpha = 2/16
43
 *   xxx00011: alpha = 3/16
44
 *   xxx00100: alpha = 4/16
45
 *   xxx00101: alpha = 5/16
46
 *   xxx00110: alpha = 6/16
47
 *   xxx00111: alpha = 7/16
48
 *   xxx01000: alpha = 8/16
49
 *   xxx01001: alpha = 9/16
50
 *   xxx01010: alpha = 10/16
51
 *   xxx01011: alpha = 11/16
52
 *   xxx01100: alpha = 12/16
53
 *   xxx01101: alpha = 13/16
54
 *   xxx01110: alpha = 14/16
55
 *   xxx01111: alpha = 15/16
56
 *   xxx11111: alpha = 16/16
57
 *   xx0xxxxx: attenuate mpeg pixel
58
 *   xx1xxxxx: alpha blend osd and mpeg pixel
59
 *   00xxxxxx: output is mpeg pixel
60
 *   01xxxxxx: output is attenuated/alpha blended pixel
61
 *   10xxxxxx: output is osd pixel
62
 *   11xxxxxx: blink; alternate between osd and attenuated/alpha blended pixel
63
 *
64
 * By combining these values, it is possible to show an OSD, either blinking
65
 * or static, on a black or a transparent background.
66
 */
67
 
68
module osd (
69
  clk, clk_en, rst,
70
  y_in, u_in, v_in, h_sync_in, v_sync_in, pixel_en_in, osd_in,
71
  y_out, u_out, v_out, h_sync_out, v_sync_out, pixel_en_out,
72
  osd_clt_rd_addr, osd_clt_rd_en, osd_clt_rd_dta,
73
  osd_enable, interlaced
74
  );
75
  input  clk;
76
  input  clk_en;
77
  input  rst;
78
 
79
  input [7:0]y_in;
80
  input [7:0]u_in;
81
  input [7:0]v_in;
82
 
83
  output reg [7:0]y_out;
84
  output reg [7:0]u_out;
85
  output reg [7:0]v_out;
86
 
87
  input pixel_en_in;
88
  input h_sync_in;
89
  input v_sync_in;
90
 
91
  output reg pixel_en_out;
92
  output reg h_sync_out;
93
  output reg v_sync_out;
94
 
95
 /* OSD pixel value */
96
  input      [7:0]osd_in;
97
 
98
 /* OSD color look-up table */
99
  output reg [7:0]osd_clt_rd_addr;
100
  output reg      osd_clt_rd_en;
101
  input     [31:0]osd_clt_rd_dta;
102
  input           osd_enable;
103
  input           interlaced;
104
 
105
  reg blink;
106
 
107
 /*
108
  * stage 0
109
  * Look up osd color
110
  */
111
  reg [7:0]y_0;
112
  reg [7:0]u_0;
113
  reg [7:0]v_0;
114
  reg      pixel_en_0;
115
  reg      h_sync_0;
116
  reg      v_sync_0;
117
 
118
  always @(posedge clk)
119
    if (~rst) osd_clt_rd_addr <= 8'b0;
120
    else if (clk_en && pixel_en_in) osd_clt_rd_addr <= osd_in;
121
    else osd_clt_rd_addr <= osd_clt_rd_addr;
122
 
123
  always @(posedge clk)
124
    if (~rst) osd_clt_rd_en <= 1'b0;
125
    else if (clk_en) osd_clt_rd_en <= pixel_en_in;
126
    else osd_clt_rd_en <= osd_clt_rd_en;
127
 
128
  always @(posedge clk)
129
    if (~rst) {y_0, u_0, v_0} <= 24'b0;
130
    else if (clk_en && pixel_en_in) {y_0, u_0, v_0} <= {y_in, u_in, v_in};
131
    else {y_0, u_0, v_0} <= {y_0, u_0, v_0};
132
 
133
  always @(posedge clk)
134
    if (~rst) {pixel_en_0, h_sync_0, v_sync_0} <= 3'b0;
135
    else if (clk_en) {pixel_en_0, h_sync_0, v_sync_0} <= {pixel_en_in, h_sync_in, v_sync_in};
136
    else {pixel_en_0, h_sync_0, v_sync_0} <= {pixel_en_0, h_sync_0, v_sync_0};
137
 
138
 /*
139
  * stage 1
140
  * Wait for osd clt lookup
141
  */
142
  reg [7:0]y_1;
143
  reg [7:0]u_1;
144
  reg [7:0]v_1;
145
  reg      pixel_en_1;
146
  reg      h_sync_1;
147
  reg      v_sync_1;
148
 
149
  always @(posedge clk)
150
    if (~rst) {y_1, u_1, v_1} <= 24'b0;
151
    else if (clk_en) {y_1, u_1, v_1} <= {y_0, u_0, v_0};
152
    else {y_1, u_1, v_1} <= {y_1, u_1, v_1};
153
 
154
  always @(posedge clk)
155
    if (~rst) {pixel_en_1, h_sync_1, v_sync_1} <= 3'b0;
156
    else if (clk_en) {pixel_en_1, h_sync_1, v_sync_1} <= {pixel_en_0, h_sync_0, v_sync_0};
157
    else {pixel_en_1, h_sync_1, v_sync_1} <= {pixel_en_1, h_sync_1, v_sync_1};
158
 
159
 /*
160
  * stage 2
161
  * Read osd color
162
  */
163
  reg [7:0]y_2;
164
  reg [7:0]u_2;
165
  reg [7:0]v_2;
166
  reg [7:0]y_blend_2;
167
  reg [7:0]u_blend_2;
168
  reg [7:0]v_blend_2;
169
  reg [7:0]osd_y_2;      /* stage 2: osd lumi */
170
  reg [7:0]osd_u_2;      /* stage 2: osd chromi */
171
  reg [7:0]osd_v_2;      /* stage 2: osd chromi */
172
  reg [3:0]osd_mode_2;   /* stage 2: osd mode: motion video, osd, blinking osd */
173
  reg [3:0]osd_transp_2; /* stage 2: osd transparency factor */
174
  reg      pixel_en_2;
175
  reg      h_sync_2;
176
  reg      v_sync_2;
177
 
178
  wire [7:0]osd_clt_y;
179
  wire [7:0]osd_clt_u;
180
  wire [7:0]osd_clt_v;
181
  wire [3:0]osd_clt_mode;
182
  wire [3:0]osd_clt_transp;
183
 
184
  assign {osd_clt_y, osd_clt_u, osd_clt_v, osd_clt_mode, osd_clt_transp} = osd_clt_rd_dta;
185
 
186
  always @(posedge clk)
187
    if (~rst) {osd_y_2, osd_u_2, osd_v_2, osd_mode_2, osd_transp_2} <= 32'b0;
188
    else if (clk_en) {osd_y_2, osd_u_2, osd_v_2, osd_mode_2, osd_transp_2} <= osd_clt_rd_dta;
189
    else {osd_y_2, osd_u_2, osd_v_2, osd_mode_2, osd_transp_2} <= {osd_y_2, osd_u_2, osd_v_2, osd_mode_2, osd_transp_2};
190
 
191
  always @(posedge clk)
192
    if (~rst) {y_2, u_2, v_2} <= 24'b0;
193
    else if (clk_en) {y_2, u_2, v_2} <= {y_1, u_1, v_1};
194
    else {y_2, u_2, v_2} <= {y_2, u_2, v_2};
195
 
196
  always @(posedge clk)
197
    if (~rst) {y_blend_2, u_blend_2, v_blend_2} <= 24'b0;
198
    else if (clk_en) {y_blend_2, u_blend_2, v_blend_2} <= osd_clt_mode[1] ? {osd_clt_y, osd_clt_u, osd_clt_v} : {8'd16, 8'd128, 8'd128}; /* (y, u, v) = (16, 128, 128) corresponds to black */
199
    else {y_blend_2, u_blend_2, v_blend_2} <= {y_blend_2, u_blend_2, v_blend_2};
200
 
201
  always @(posedge clk)
202
    if (~rst) {pixel_en_2, h_sync_2, v_sync_2} <= 3'b0;
203
    else if (clk_en) {pixel_en_2, h_sync_2, v_sync_2} <= {pixel_en_1, h_sync_1, v_sync_1};
204
    else {pixel_en_2, h_sync_2, v_sync_2} <= {pixel_en_2, h_sync_2, v_sync_2};
205
 
206
 /*
207
  * stage 3-5
208
  * Transparency. Attenuate mpeg pixel.
209
  */
210
  wire [7:0]y_5;
211
  wire [7:0]u_5;
212
  wire [7:0]v_5;
213
  wire [7:0]y_transp_5;   /* stage 5: attenuated mpeg lumi */
214
  wire [7:0]u_transp_5;   /* stage 5: attenuated mpeg chromi */
215
  wire [7:0]v_transp_5;   /* stage 5: attenuated mpeg chromi */
216
  wire [7:0]osd_y_5;      /* stage 5: osd lumi */
217
  wire [7:0]osd_u_5;      /* stage 5: osd chromi */
218
  wire [7:0]osd_v_5;      /* stage 5: osd chromi */
219
  wire [3:0]osd_mode_5;   /* stage 5: osd mode: motion video, osd, transparent osd, blinking osd */
220
  wire      pixel_en_5;
221
  wire      h_sync_5;
222
  wire      v_sync_5;
223
 
224
  alpha_blend
225
    #(.dta_width(55))
226
    alpha_blend_y (
227
    .clk(clk),
228
    .clk_en(clk_en),
229
    .rst(rst),
230
    .x_in(y_blend_2),
231
    .y_in(y_2),
232
    .dta_in({osd_y_2, osd_u_2, osd_v_2, osd_mode_2, y_2, u_2, v_2, pixel_en_2, h_sync_2, v_sync_2}),
233
    .z_out(y_transp_5),
234
    .dta_out({osd_y_5, osd_u_5, osd_v_5, osd_mode_5, y_5, u_5, v_5, pixel_en_5, h_sync_5, v_sync_5}),
235
    .alpha_1(osd_mode_2[0]),
236
    .alpha_2(osd_transp_2)
237
    );
238
 
239
  alpha_blend
240
    #(.dta_width(1))
241
    alpha_blend_u (
242
    .clk(clk),
243
    .clk_en(clk_en),
244
    .rst(rst),
245
    .x_in(u_blend_2),
246
    .y_in(u_2),
247
    .dta_in(1'b0),
248
    .z_out(u_transp_5),
249
    .alpha_1(osd_mode_2[0]),
250
    .alpha_2(osd_transp_2),
251
    .dta_out()
252
    );
253
 
254
  alpha_blend
255
    #(.dta_width(1))
256
    alpha_blend_v (
257
    .clk(clk),
258
    .clk_en(clk_en),
259
    .rst(rst),
260
    .x_in(v_blend_2),
261
    .y_in(v_2),
262
    .dta_in(1'b0),
263
    .z_out(v_transp_5),
264
    .alpha_1(osd_mode_2[0]),
265
    .alpha_2(osd_transp_2),
266
    .dta_out()
267
    );
268
 
269
 /*
270
  * stage 5
271
  * Select between mpeg pixel, attenuated mpeg pixel, osd pixel, or blinking osd.
272
  */
273
 
274
  always @(posedge clk)
275
    if (~rst) {y_out, u_out, v_out} <= 24'b0;
276
    else if (clk_en && ~pixel_en_5) {y_out, u_out, v_out} <= {8'd16, 8'd128, 8'd128};                                /* black during blanking */
277
    else if (clk_en && osd_enable)
278
      case (osd_mode_5[3:2])
279
        3'b00:  {y_out, u_out, v_out} <=         {y_5,        u_5,        v_5       }                              ; /* mpeg pixel */
280
        3'b01:  {y_out, u_out, v_out} <=         {y_transp_5, u_transp_5, v_transp_5}                              ; /* attenuated/alpha blended mpeg pixel */
281
        3'b10:  {y_out, u_out, v_out} <=                                                {osd_y_5, osd_u_5, osd_v_5}; /* osd pixel */
282
        3'b11:  {y_out, u_out, v_out} <= blink ? {y_transp_5, u_transp_5, v_transp_5} : {osd_y_5, osd_u_5, osd_v_5}; /* alternate between osd and attenuated/alpha blended mpeg pixel */
283
        default {y_out, u_out, v_out} <=         {y_5       , u_5       , v_5       }                              ; /* mpeg pixel */
284
      endcase
285
    else if (clk_en) {y_out, u_out, v_out} <= {y_5, u_5, v_5};                                                       /* osd switched off */
286
    else {y_out, u_out, v_out} <= {y_out, u_out, v_out};
287
 
288
  always @(posedge clk)
289
    if (~rst) {pixel_en_out, h_sync_out, v_sync_out} <= 3'b0;
290
    else if (clk_en) {pixel_en_out, h_sync_out, v_sync_out} <= {pixel_en_5, h_sync_5, v_sync_5};
291
    else {pixel_en_out, h_sync_out, v_sync_out} <= {pixel_en_out, h_sync_out, v_sync_out};
292
 
293
  /* Blinking */
294
 
295
  /*
296
   * count number of frames/fields.
297
   * field_cnd increases by 1 on the falling edge of vsync
298
   */
299
 
300
  reg [6:0]field_cnt;
301
 
302
  always @(posedge clk)
303
    if (~rst) field_cnt <= 0;
304
    else if (clk_en && (v_sync_1 == 1'b0) && (v_sync_2 == 1'b1)) field_cnt <= field_cnt + 1;
305
    else field_cnt <= field_cnt;
306
 
307
  always @(posedge clk)
308
    if (~rst) blink <= 0;
309
    else if (clk_en) blink <= interlaced ? field_cnt[6] : field_cnt[5]; // toggles every second or so. (Actually, every 32 frames if progressive, every 64 fields if interlaced)
310
    else blink <= blink;
311
 
312
`ifdef DEBUG
313
  always @(posedge clk)
314
    $strobe("%m\tin: %0d %0d %0d 1: %0d %0d %0d 2: %0d %0d %0d 5: %0d %0d %0d out: %0d %0d %0d enable: %d", y_in, u_in, v_in, y_1, u_1, v_1, y_2, u_2, v_2, y_5, u_5, v_5, y_out, u_out, v_out, osd_enable);
315
`endif
316
endmodule
317
 
318
/*
319
 * On-Screen Display Color Lookup Table
320
 *
321
 * Register file writes to clt,
322
 * osd reads from clt.
323
 */
324
`undef DEBUG
325
//`define DEBUG 1
326
 
327
module osd_clt (
328
  clk,
329
  rst,
330
  osd_clt_wr_en,
331
  osd_clt_wr_addr,
332
  osd_clt_wr_dta,
333
  dot_clk,
334
  dot_rst,
335
  osd_clt_rd_addr,
336
  osd_clt_rd_en,
337
  osd_clt_rd_dta);
338
 
339
  input        clk;
340
  input        rst;
341
  input        osd_clt_wr_en;
342
  input   [7:0]osd_clt_wr_addr;
343
  input  [31:0]osd_clt_wr_dta;
344
  input        dot_clk;
345
  input        dot_rst;
346
  input   [7:0]osd_clt_rd_addr;
347
  input        osd_clt_rd_en;
348
  output [31:0]osd_clt_rd_dta;
349
 
350
  reg     [7:0]clt_wr_addr;
351
  reg          clt_wr_en;
352
  reg    [31:0]clt_wr_dta;
353
 
354
  parameter [2:0]
355
    STATE_INIT  = 3'b001,
356
    STATE_CLEAR = 3'b010,
357
    STATE_RUN   = 3'b100;
358
 
359
  reg [2:0]next;
360
  reg [2:0]state;
361
 
362
  /*
363
   * state machine to initialize color-lookup table at reset
364
   */
365
 
366
  always @*
367
    case (state)
368
      STATE_INIT:  next = STATE_CLEAR;
369
      STATE_CLEAR: if (clt_wr_addr == 8'hff) next = STATE_RUN;
370
                   else next = STATE_CLEAR;
371
      STATE_RUN:   next = STATE_RUN;
372
      default:     next = STATE_INIT;
373
    endcase
374
 
375
  always @(posedge clk)
376
    if (~rst) state <= STATE_INIT;
377
    else state <= next;
378
 
379
  always @(posedge clk)
380
    if (~rst) clt_wr_en <= 1'b0;
381
    else
382
      case (state)
383
        STATE_INIT:  clt_wr_en <= 1'b0;
384
        STATE_CLEAR: clt_wr_en <= 1'b1;
385
        STATE_RUN:   clt_wr_en <= osd_clt_wr_en;
386
        default      clt_wr_en <= 1'b0;
387
      endcase
388
 
389
  always @(posedge clk)
390
    if (~rst) clt_wr_addr <= 8'b0;
391
    else
392
      case (state)
393
        STATE_INIT:  clt_wr_addr <= 8'b0;
394
        STATE_CLEAR: clt_wr_addr <= clt_wr_addr + 8'b1;
395
        STATE_RUN:   clt_wr_addr <= osd_clt_wr_addr;
396
        default      clt_wr_addr <= 8'b0;
397
      endcase
398
 
399
  always @(posedge clk)
400
    if (~rst) clt_wr_dta <= 32'b0;
401
    else
402
      case (state)
403
        STATE_INIT:  clt_wr_dta <= 32'b0;
404
        STATE_CLEAR: clt_wr_dta <= 32'b0;
405
        STATE_RUN:   clt_wr_dta <= osd_clt_wr_dta;
406
        default      clt_wr_dta <= 32'b0;
407
      endcase
408
 
409
  /* OSD color look-up table */
410
 
411
  dpram_dc
412
    #(.addr_width(8),                                         // number of bits in address bus
413
    .dta_width(32))                                           // number of bits in data bus
414
    osd_clt (
415
    .wr_rst(rst),                                             // reset, sync with write clock, active low
416
    .wr_clk(clk),                                             // write clock, rising edge trigger
417
    .wr_en(clt_wr_en),                                        // write enable, active high
418
    .wr_addr(clt_wr_addr),                                    // write address
419
    .din(clt_wr_dta),                                         // data input
420
    .rd_rst(dot_rst),                                         // reset, sync with read clock, active low
421
    .rd_clk(dot_clk),                                         // read clock, rising edge trigger
422
    .rd_en(osd_clt_rd_en),                                    // read enable, active high
423
    .rd_addr(osd_clt_rd_addr),                                // read address
424
    .dout(osd_clt_rd_dta)                                     // data output
425
    );
426
 
427
`ifdef DEBUG
428
  always @(posedge clk)
429
    $strobe("%m\tstate: %b clt_wr_en: %x clt_wr_addr: %x clt_wr_dta: %x", state, clt_wr_en, clt_wr_addr, clt_wr_dta);
430
`endif
431
endmodule
432
 
433
/*
434
 * Alpha blend x and y, using
435
 * z <= ( alpha_2 * x + ~alpha_2 * y + (alpha_1 ? x : y) + (1'b1 << (alpha_width - 1))) >> alpha_width;
436
 * where alpha_2 is 4 bits wide, alpha_width = 4.
437
 * To obtain alpha = 1, z = x set alpha_1 = 1, alpha_2 = 1111.
438
 * For values of alpha other than 1, set alpha_1 = 0.
439
 */
440
`undef DEBUG
441
//`define DEBUG 1
442
 
443
module alpha_blend (
444
  clk, clk_en, rst,
445
  x_in, y_in, alpha_1, alpha_2, dta_in, z_out, dta_out
446
  );
447
  parameter dta_width=8;
448
  input  clk;
449
  input  clk_en;
450
  input  rst;
451
 
452
  input [7:0]x_in;
453
  input [7:0]y_in;
454
  input      alpha_1;
455
  input [3:0]alpha_2;
456
  input [dta_width-1:0]dta_in;
457
 
458
  output reg [7:0]z_out;
459
  output reg [dta_width-1:0]dta_out;
460
 
461
  /*
462
   * stage 1.
463
   */
464
 
465
  reg [12:0]x_prod_1;
466
  reg [12:0]y_prod_1;
467
  reg [dta_width-1:0]dta_1;
468
 
469
  wire [3:0]alpha_2_inv = ~alpha_2;
470
 
471
  always @(posedge clk)
472
    if (~rst) x_prod_1 <= 13'd0;
473
    else if (clk_en) x_prod_1 <= x_in * alpha_2 + 14'b1000;
474
    else x_prod_1 <= x_prod_1;
475
 
476
  always @(posedge clk)
477
    if (~rst) y_prod_1 <= 13'd0;
478
    else if (clk_en) y_prod_1 <= y_in * alpha_2_inv + (alpha_1 ? x_in : y_in);
479
    else y_prod_1 <= y_prod_1;
480
 
481
  always @(posedge clk)
482
    if (~rst) dta_1 <= 0;
483
    else if (clk_en) dta_1 <= dta_in;
484
    else dta_1 <= dta_1;
485
 
486
  /*
487
   * stage 2.
488
   */
489
 
490
  reg [14:0]z_sum_2;
491
  wire [14:0]x_prod_1_ext = {1'b0, x_prod_1};
492
  wire [14:0]y_prod_1_ext = {1'b0, y_prod_1};
493
  reg [dta_width-1:0]dta_2;
494
 
495
  always @(posedge clk)
496
    if (~rst) z_sum_2 <= 15'd0;
497
    else if (clk_en) z_sum_2 <= (x_prod_1_ext + y_prod_1_ext) >> 4;
498
    else z_sum_2 <= z_sum_2;
499
 
500
  always @(posedge clk)
501
    if (~rst) dta_2 <= 0;
502
    else if (clk_en) dta_2 <= dta_1;
503
    else dta_2 <= dta_2;
504
 
505
  /*
506
   * stage 3.
507
   */
508
 
509
  always @(posedge clk)
510
    if (~rst) z_out <= 8'd0;
511
    else if (clk_en) z_out <= (z_sum_2[14:8] == 7'b0) ? z_sum_2[7:0] : 8'd255;
512
    else z_out <= z_out;
513
 
514
  always @(posedge clk)
515
    if (~rst) dta_out <= 0;
516
    else if (clk_en) dta_out <= dta_2;
517
    else dta_out <= dta_out;
518
 
519
`ifdef DEBUG
520
  always @(posedge clk)
521
    $strobe("%m\tx_in: %d  y_in: %d  alpha_1: %d  alpha_2: %d  x_prod_1: %d  y_prod_1: %d  z_sum_2: %d  z_out: %d",
522
                 x_in, y_in, alpha_1, alpha_2, x_prod_1, y_prod_1, z_sum_2, z_out);
523
`endif
524
endmodule
525
/* not truncated */

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