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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [pixel_queue.v] - Blame information for rev 2

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1 2 kdv
/*
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 * pixel_queue.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * pixel_queue - Pixel output queue
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 */
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`include "timescale.v"
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module pixel_queue(
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  clk_in, clk_in_en,
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  rst,
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  y_in, u_in, v_in, osd_in, position_in, pixel_wr_en, pixel_wr_almost_full, pixel_wr_full, pixel_wr_overflow,
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  clk_out, clk_out_en,
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  y_out, u_out, v_out, osd_out, position_out, pixel_rd_en, pixel_rd_empty, pixel_rd_valid, pixel_rd_underflow
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  );
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  input              clk_in;                   // write clock
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  input              clk_in_en;                // write clock enable
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  input              rst;                      // synchronous active low reset
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  input         [7:0]y_in;
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  input         [7:0]u_in;
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  input         [7:0]v_in;
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  input         [7:0]osd_in;
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  input         [2:0]position_in;
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  input              pixel_wr_en;
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  output             pixel_wr_almost_full;
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  output             pixel_wr_full;
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  output             pixel_wr_overflow;
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  input              clk_out;                  // read clock
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  input              clk_out_en;               // read clock enable
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  output        [7:0]y_out;
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  output        [7:0]u_out;
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  output        [7:0]v_out;
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  output        [7:0]osd_out;
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  output        [2:0]position_out;
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  input              pixel_rd_en;
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  output             pixel_rd_empty;
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  output             pixel_rd_valid;
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  output             pixel_rd_underflow;
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`include "fifo_size.v"
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  fifo_dc
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    #(.addr_width(PIXEL_DEPTH),
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    .dta_width(9'd35),
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    .prog_thresh(PIXEL_THRESHOLD),
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    .FIFO_XILINX(1))
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    pixel_fifo (
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    .rst(rst),
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    .wr_clk(clk_in),
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    .din({y_in, u_in, v_in, osd_in, position_in}),
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    .wr_en(pixel_wr_en && clk_in_en),
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    .wr_ack(),
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    .full(pixel_wr_full),
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    .overflow(pixel_wr_overflow),
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    .rd_clk(clk_out),
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    .dout({y_out, u_out, v_out, osd_out, position_out}),
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    .rd_en(pixel_rd_en && clk_out_en),
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    .valid(pixel_rd_valid),
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    .empty(pixel_rd_empty),
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    .underflow(pixel_rd_underflow),
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    .prog_full(pixel_wr_almost_full),
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    .prog_empty()
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    );
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endmodule
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/* not truncated */

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