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/*
2
 * probe.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * logical analyzer probe
21
 *
22
 * Input:
23
 *   registers from all over the place.
24
 *   testpoint_regfile, testpoint_dip, testpoint_dip_en: selects which test point to output to logic analyzer.
25
 * Output:
26
 *   testpoint: 34-channel test point. Convention: testpoint can contain up to two clocks. Any clocks are mapped on bits 32 and/or 33.
27
 *
28
 *   Note instantiating the probe makes routing/timing more difficult; don't instantiate the probe if you don't need it.
29
 */
30
 
31
`include "timescale.v"
32
 
33
// uncomment one and only one of the three following lines to instantiate testpoint
34
`define PROBE 1
35
//`define PROBE_VIDEO 1
36
//`define PROBE_MEMORY 1
37
 
38
/*
39
 * Define PROBE only when needed.
40
 * Define PROBE_VIDEO and/or PROBE_MEMORY only when really needed.
41
 */
42
 
43
module probe(clk, mem_clk, dot_clk,
44
             sync_rst, mem_rst, dot_rst,
45
             testpoint_dip, testpoint_dip_en , testpoint_regfile, testpoint,
46
             stream_data, stream_valid, busy,
47
             vbr_rd_dta, vbr_rd_en, vbr_rd_valid, advance, align,
48
             getbits, signbit, getbits_valid,
49
             dct_coeff_wr_run, dct_coeff_wr_signed_level, dct_coeff_wr_end, rld_wr_en,
50
             vld_en, motcomp_busy, error, watchdog_rst,
51
             macroblock_address, macroblock_motion_forward, macroblock_motion_backward,
52
             macroblock_intra, second_field, update_picture_buffers, last_frame, motion_vector_valid,
53
             /* fifo's @ clk */
54
             mvec_wr_almost_full, mvec_wr_overflow, dst_wr_overflow, dct_block_wr_overflow,
55
             bwd_wr_addr_almost_full, bwd_wr_addr_full, bwd_wr_addr_overflow, bwd_rd_addr_empty, bwd_wr_dta_almost_full, bwd_wr_dta_full, bwd_wr_dta_overflow,
56
             bwd_rd_dta_empty,
57
             disp_wr_addr_almost_full, disp_wr_addr_full, disp_wr_addr_overflow, disp_rd_addr_empty, disp_wr_dta_almost_full, disp_wr_dta_full, disp_wr_dta_overflow,
58
             disp_rd_dta_empty,
59
             fwd_wr_addr_almost_full, fwd_wr_addr_full, fwd_wr_addr_overflow, fwd_rd_addr_empty, fwd_wr_dta_almost_full, fwd_wr_dta_full, fwd_wr_dta_overflow,
60
             fwd_rd_dta_empty,
61
             idct_fifo_almost_full, idct_fifo_overflow, idct_rd_dta_empty, frame_idct_wr_overflow,
62
             mem_req_wr_almost_full, mem_req_wr_full, mem_req_wr_overflow,
63
             resample_wr_overflow,
64
             pixel_wr_almost_full, pixel_wr_full, pixel_wr_overflow, pixel_rd_empty,
65
             recon_wr_almost_full, recon_wr_full, recon_wr_overflow, recon_rd_empty,
66
             rld_wr_almost_full, rld_wr_overflow,
67
             tag_wr_almost_full, tag_wr_full, tag_wr_overflow,
68
             vbr_wr_almost_full, vbr_wr_full, vbr_wr_overflow, vbr_rd_empty, vbw_wr_almost_full, vbw_wr_full, vbw_wr_overflow,
69
             vbw_rd_empty,
70
             /* fifo's @ mem_clk */
71
             mem_req_rd_en, mem_req_rd_valid,
72
             mem_res_wr_en, mem_res_wr_almost_full, mem_res_wr_full, mem_res_wr_overflow,
73
             /* register file */
74
             reg_addr, reg_wr_en, reg_dta_in, reg_rd_en, reg_dta_out,
75
             /* output frame */
76
             output_frame, output_frame_valid, output_frame_rd,
77
             output_progressive_sequence, output_progressive_frame, output_top_field_first, output_repeat_first_field,
78
             /* osd writes */
79
             osd_wr_en, osd_wr_ack, osd_wr_addr, osd_wr_full, osd_wr_overflow, osd_rd_empty,
80
             /* video out */
81
             y, u, v, pixel_en, h_sync, v_sync
82
             );
83
 
84
  input            clk;                     // clock. Typically a multiple of 27 Mhz as MPEG2 timestamps have a 27 Mhz resolution.
85
  input            mem_clk;                 // memory clock. Typically 133-166 MHz.
86
  input            dot_clk;                 // video clock. Typically between 25 and 75 Mhz, depending upon MPEG2 resolution and frame rate.
87
 
88
  /* reset signals */
89
  input            sync_rst;                // reset, synchronized to clk
90
  input            mem_rst;                 // reset, synchronized to mem_clk
91
  input            dot_rst;                 // reset, synchronized to dot_clk
92
 
93
  /* logical analyzer test point */
94
  output     [33:0]testpoint;               // to logic analyzer probe
95
  input       [3:0]testpoint_regfile;       // from register file; test point select.
96
  input       [3:0]testpoint_dip;           // from from on-board dipswitches
97
  input            testpoint_dip_en;        // from from on-board dipswitches. If high, testpoint_dip overrides testpoint_regfile
98
 
99
  /* MPEG stream input */
100
  input       [7:0]stream_data;              // packetized elementary stream input
101
  input            stream_valid;             // stream_data valid
102
  input            busy;                     // input fifo almost full
103
 
104
  /* vbr fifo - getbits fifo interface */
105
  input      [63:0]vbr_rd_dta;
106
  input            vbr_rd_en;
107
  input            vbr_rd_valid;
108
 
109
  /* getbits_fifo - vld interface */
110
  input       [4:0]advance;                  // number of bits to advance the bitstream (advance <= 24)   
111
  input            align;                    // byte-align getbits and move forward one byte.
112
  input      [23:0]getbits;                  // elementary stream data. 
113
  input            signbit;                  // sign bit, used when decoding dct variable length codes.
114
  input            getbits_valid;            // getbits_valid is asserted when getbits is valid.
115
 
116
  /* vld */
117
  input            vld_en;
118
  input            error;
119
  input            motcomp_busy;
120
 
121
  /* watchdog */
122
  input            watchdog_rst;             // watchdog-generated reset signal. normally high; low during one clock cycle when watchdog timer expires.
123
 
124
  /* rld - vld interface */
125
  input       [5:0]dct_coeff_wr_run;         // dct coefficient runlength, from vlc decoding
126
  input      [11:0]dct_coeff_wr_signed_level;// dct coefficient level, 2's complement format, from vlc decoding
127
  input            dct_coeff_wr_end;         // asserted at end of block 
128
  input            rld_wr_en;                // asserted when dct_coeff_wr_run, dct_coeff_wr_signed_level and dct_coeff_wr_end are valid
129
 
130
  /* motion compensation */
131
  input      [12:0]macroblock_address;
132
  input            macroblock_motion_forward;
133
  input            macroblock_motion_backward;
134
  input            macroblock_intra;
135
  input            second_field;
136
  input            update_picture_buffers;
137
  input            last_frame;
138
  input            motion_vector_valid;
139
 
140
  /* fifo status indicators @ clk */
141
  input            bwd_wr_addr_almost_full;
142
  input            bwd_wr_addr_full;
143
  input            bwd_wr_addr_overflow;
144
  input            bwd_rd_addr_empty;
145
  input            bwd_wr_dta_almost_full;
146
  input            bwd_wr_dta_full;
147
  input            bwd_wr_dta_overflow;
148
  input            bwd_rd_dta_empty;
149
  input            disp_wr_addr_almost_full;
150
  input            disp_wr_addr_full;
151
  input            disp_wr_addr_overflow;
152
  input            disp_rd_addr_empty;
153
  input            disp_wr_dta_almost_full;
154
  input            disp_wr_dta_full;
155
  input            disp_wr_dta_overflow;
156
  input            disp_rd_dta_empty;
157
  input            fwd_wr_addr_almost_full;
158
  input            fwd_wr_addr_full;
159
  input            fwd_wr_addr_overflow;
160
  input            fwd_rd_addr_empty;
161
  input            fwd_wr_dta_almost_full;
162
  input            fwd_wr_dta_full;
163
  input            fwd_wr_dta_overflow;
164
  input            fwd_rd_dta_empty;
165
  input            idct_fifo_almost_full;
166
  input            idct_fifo_overflow;
167
  input            idct_rd_dta_empty;
168
  input            mvec_wr_almost_full;
169
  input            mvec_wr_overflow;
170
  input            dst_wr_overflow;
171
  input            dct_block_wr_overflow;
172
  input            frame_idct_wr_overflow;
173
  input            mem_req_wr_almost_full;
174
  input            mem_req_wr_full;
175
  input            mem_req_wr_overflow;
176
  input            osd_wr_full;
177
  input            osd_wr_overflow;
178
  input            osd_rd_empty;
179
  input            resample_wr_overflow;
180
  input            pixel_wr_almost_full;
181
  input            pixel_wr_full;
182
  input            pixel_wr_overflow;
183
  input            pixel_rd_empty;
184
  input            recon_wr_almost_full;
185
  input            recon_wr_full;
186
  input            recon_wr_overflow;
187
  input            recon_rd_empty;
188
  input            rld_wr_almost_full;
189
  input            rld_wr_overflow;
190
  input            tag_wr_almost_full;
191
  input            tag_wr_full;
192
  input            tag_wr_overflow;
193
  input            vbr_wr_almost_full;
194
  input            vbr_wr_full;
195
  input            vbr_wr_overflow;
196
  input            vbr_rd_empty;
197
  input            vbw_wr_almost_full;
198
  input            vbw_wr_full;
199
  input            vbw_wr_overflow;
200
  input            vbw_rd_empty;
201
  /* fifo status indicators @ mem_clk */
202
  input            mem_req_rd_en;
203
  input            mem_req_rd_valid;
204
  input            mem_res_wr_en;
205
  input            mem_res_wr_almost_full;
206
  input            mem_res_wr_full;
207
  input            mem_res_wr_overflow;
208
  /* regfile */
209
  input       [3:0]reg_addr;
210
  input      [31:0]reg_dta_in;
211
  input            reg_wr_en;
212
  input      [31:0]reg_dta_out;
213
  input            reg_rd_en;
214
  /* output frame */
215
  input       [2:0]output_frame;
216
  input            output_frame_valid;
217
  input            output_frame_rd;
218
  input            output_progressive_sequence;
219
  input            output_progressive_frame;
220
  input            output_top_field_first;
221
  input            output_repeat_first_field;
222
 
223
  /* osd writes */
224
  input            osd_wr_en;
225
  input            osd_wr_ack;
226
  input      [21:0]osd_wr_addr;
227
 
228
  /* yuv video */
229
  input       [7:0]y;                       // luminance 
230
  input       [7:0]u;                       // chrominance
231
  input       [7:0]v;                       // chrominance
232
  input            pixel_en;                // pixel enable - asserted if r, g and b valid.
233
  input            h_sync;                  // horizontal synchronisation
234
  input            v_sync;                  // vertical synchronisation
235
 
236
  /*
237
   * any clocks have to be bits 32 or 33 of testpoint, because that's where my la expects them.
238
   */
239
 
240
`ifdef PROBE
241
  reg   [3:0]testpoint_sel;
242
  reg  [32:0]testpoint_0_f;
243
  reg  [32:0]testpoint_0_7;
244
  reg  [32:0]testpoint_8_f;
245
 
246
  reg  [32:0]testpoint_0;
247
  reg  [32:0]testpoint_1;
248
  reg  [32:0]testpoint_2;
249
  reg  [32:0]testpoint_3;
250
  reg  [32:0]testpoint_4;
251
  reg  [32:0]testpoint_5;
252
  reg  [32:0]testpoint_6;
253
  reg  [32:0]testpoint_7;
254
  reg  [32:0]testpoint_8;
255
  reg  [32:0]testpoint_9;
256
  reg  [32:0]testpoint_a;
257
  reg  [32:0]testpoint_b;
258
  reg  [32:0]testpoint_c;
259
  reg  [32:0]testpoint_d;
260
  reg  [32:0]testpoint_e;
261
  reg  [32:0]testpoint_f;
262
 
263
  /*
264
   * testpoint_dip_en and testpoint_dip are dip switches.
265
   * If testpoint_dip_en is high, testpoint output is hardware selectable using testpoint_dip dip switches.
266
   * If testpoint_dip_en is low,  testpoint output is software selectable using regfile register 15.
267
   * Software can read testpoint output as well, using regfile register 15.
268
   */
269
 
270
  always @(posedge clk)
271
    testpoint_sel <= testpoint_dip_en ? testpoint_dip : testpoint_regfile;
272
 
273
  assign testpoint = {clk, testpoint_0_f};
274
 
275
  always @(posedge clk)
276
    case (testpoint_sel[2:0])
277
      3'h0:     testpoint_0_7 <= {testpoint_0[0], testpoint_0[32:1]};
278
      3'h1:     testpoint_0_7 <= {testpoint_1[0], testpoint_1[32:1]};
279
      3'h2:     testpoint_0_7 <= {testpoint_2[0], testpoint_2[32:1]};
280
      3'h3:     testpoint_0_7 <= {testpoint_3[0], testpoint_3[32:1]};
281
      3'h4:     testpoint_0_7 <= {testpoint_4[0], testpoint_4[32:1]};
282
      3'h5:     testpoint_0_7 <= {testpoint_5[0], testpoint_5[32:1]};
283
      3'h6:     testpoint_0_7 <= {testpoint_6[0], testpoint_6[32:1]};
284
      3'h7:     testpoint_0_7 <= {testpoint_7[0], testpoint_7[32:1]};
285
      default   testpoint_0_7 <= {32'hdeadbeef};
286
    endcase
287
 
288
  always @(posedge clk)
289
    case (testpoint_sel[2:0])
290
      3'h0:     testpoint_8_f <= {testpoint_8[0], testpoint_8[32:1]};
291
      3'h1:     testpoint_8_f <= {testpoint_9[0], testpoint_9[32:1]};
292
      3'h2:     testpoint_8_f <= {testpoint_b[0], testpoint_b[32:1]};
293
      3'h4:     testpoint_8_f <= {testpoint_c[0], testpoint_c[32:1]};
294
      3'h5:     testpoint_8_f <= {testpoint_d[0], testpoint_d[32:1]};
295
      3'h6:     testpoint_8_f <= {testpoint_e[0], testpoint_e[32:1]};
296
      default   testpoint_8_f <= {32'hdeadbeef};
297
    endcase
298
 
299
  always @(posedge clk)
300
    if (testpoint_sel[3]) testpoint_0_f <= testpoint_8_f;
301
    else testpoint_0_f <= testpoint_0_7;
302
 
303
  /* testpoint 0: incoming video */
304
  always @(posedge clk)
305
    if (~sync_rst) testpoint_0 <= 33'b0;
306
    else testpoint_0 <= {vbr_rd_dta[63:48], stream_data, 3'b0, watchdog_rst, busy, vbr_rd_en, vbr_rd_valid, stream_valid, sync_rst};
307
 
308
  /* testpoint 1: video buffer output  */
309
  always @(posedge clk)
310
    if (~sync_rst) testpoint_1 <= 33'b0;
311
    else testpoint_1 <= {vbr_rd_dta[63:32], vbr_rd_valid};
312
 
313
  /* testpoint 2: video buffer output  */
314
  always @(posedge clk)
315
    if (~sync_rst) testpoint_2 <= 33'b0;
316
    else testpoint_2 <= {vbr_rd_dta[31:0], vbr_rd_valid};
317
 
318
  /* testpoint 3: getbits */
319
  always @(posedge clk)
320
    if (~sync_rst) testpoint_3 <= 33'b0;
321
    else testpoint_3 <= {advance, align, getbits, signbit, getbits_valid, sync_rst};
322
 
323
  /* testpoint 4: vld */
324
  always @(posedge clk)
325
    if (~sync_rst) testpoint_4 <= 33'b0;
326
    else testpoint_4 <= {dct_coeff_wr_run, dct_coeff_wr_signed_level, dct_coeff_wr_end,
327
                         vld_en, getbits_valid, rld_wr_almost_full, motcomp_busy, rld_wr_en};
328
 
329
  /* testpoint 5,6 and 7: regfile */
330
  always @(posedge clk)
331
    if (~sync_rst) testpoint_5 <= 33'b0;
332
    else testpoint_5 <= {reg_dta_out[7:0], reg_dta_in[7:0], 2'b0, reg_wr_en, reg_rd_en, reg_addr, sync_rst};
333
 
334
  always @(posedge clk)
335
    if (~sync_rst) testpoint_6 <= 33'b0;
336
    else testpoint_6 <= {reg_dta_in, reg_wr_en};
337
 
338
  always @(posedge clk)
339
    if (~sync_rst) testpoint_7 <= 33'b0;
340
    else testpoint_7 <= {reg_dta_out, reg_rd_en};
341
 
342
  /* testpoint 8 and 9: fifo status @ clk */
343
  always @(posedge clk)
344
    if (~sync_rst) testpoint_8 <= 33'b0;
345
    else testpoint_8 <= {bwd_wr_addr_almost_full, bwd_wr_addr_full, bwd_wr_addr_overflow, bwd_rd_addr_empty,
346
                         bwd_wr_dta_almost_full, bwd_wr_dta_full, bwd_wr_dta_overflow, bwd_rd_dta_empty,
347
                         disp_wr_addr_almost_full, disp_wr_addr_full, disp_wr_addr_overflow, disp_rd_addr_empty,
348
                         disp_wr_dta_almost_full, disp_wr_dta_full, disp_wr_dta_overflow, disp_rd_dta_empty,
349
                         fwd_wr_addr_almost_full, fwd_wr_addr_full, fwd_wr_addr_overflow, fwd_rd_addr_empty,
350
                         fwd_wr_dta_almost_full, fwd_wr_dta_full, fwd_wr_dta_overflow, fwd_rd_dta_empty,
351
                         recon_wr_almost_full, recon_wr_full, recon_wr_overflow, recon_rd_empty,
352
                         sync_rst};
353
 
354
  always @(posedge clk)
355
    if (~sync_rst) testpoint_9 <= 33'b0;
356
    else testpoint_9 <= {mvec_wr_almost_full, mvec_wr_overflow,
357
                         dst_wr_overflow, resample_wr_overflow, dct_block_wr_overflow,
358
                         idct_fifo_almost_full, idct_fifo_overflow, idct_rd_dta_empty, frame_idct_wr_overflow,
359
                         mem_req_wr_almost_full, mem_req_wr_full, mem_req_wr_overflow,
360
                         osd_wr_full, osd_wr_overflow, osd_rd_empty,
361
                         pixel_wr_almost_full, pixel_wr_full, pixel_wr_overflow,
362
                         rld_wr_almost_full, rld_wr_overflow,
363
                         tag_wr_almost_full, tag_wr_full, tag_wr_overflow,
364
                         vbr_wr_almost_full, vbr_wr_full, vbr_wr_overflow, vbr_rd_empty,
365
                         vbw_wr_almost_full, vbw_wr_full, vbw_wr_overflow, vbw_rd_empty,
366
                         sync_rst};
367
 
368
  /* testpoint a: free */
369
 
370
  /* testpoint b: motion comp */
371
  always @(posedge clk)
372
    if (~sync_rst) testpoint_b <= 33'b0;
373
    else testpoint_b <= {macroblock_address, 2'b0, macroblock_motion_forward, macroblock_motion_backward,
374
                         macroblock_intra, second_field, update_picture_buffers, last_frame, motion_vector_valid};
375
 
376
  /* testpoint c: osd writes; useful to check pixel coordinates to memory address translation */
377
  always @(posedge clk)
378
    if (~sync_rst) testpoint_c <= 33'b0;
379
    else testpoint_c <= {osd_wr_overflow, osd_wr_full, osd_wr_en, osd_wr_ack, osd_wr_addr, sync_rst};
380
 
381
  /* testpoint d: output frame */
382
  always @(posedge clk)
383
    if (~sync_rst) testpoint_d <= 33'b0;
384
    else testpoint_d <= {motcomp_busy, output_frame, output_frame_valid, output_frame_rd,
385
                         output_progressive_sequence, output_progressive_frame, output_top_field_first, output_repeat_first_field, sync_rst};
386
 
387
  /* testpoint e: free */
388
  always @(posedge clk)
389
    if (~sync_rst) testpoint_e <= 33'b0;
390
    else testpoint_e <= {32'hdeadbeef, sync_rst};
391
 
392
  /* testpoint f: free */
393
`endif
394
 
395
`ifndef PROBE
396
`ifndef PROBE_VIDEO
397
`ifdef PROBE_MEMORY
398
  /* testpoint: fifo status @ mem_clk */
399
 
400
  reg  [32:0]testpoint_mem;
401
 
402
  assign testpoint = {mem_clk, testpoint_mem[0], testpoint_mem[32:1]};
403
 
404
  always @(posedge clk)
405
    if (~sync_rst) testpoint_mem <= 33'b0;
406
    else testpoint_mem <= {mem_req_rd_en, mem_req_rd_valid,
407
                           mem_res_wr_en, mem_res_wr_almost_full, mem_res_wr_full, mem_res_wr_overflow,
408
                           mem_rst};
409
 
410
`endif
411
`endif
412
`endif
413
 
414
`ifndef PROBE
415
`ifdef PROBE_VIDEO
416
`ifndef PROBE_MEMORY
417
 
418
  /* testpoint: video output @ dot_clk */
419
 
420
  reg  [32:0]testpoint_video;
421
 
422
  assign testpoint = {dot_clk, testpoint_video[0], testpoint_video[32:1]};
423
 
424
  always @(posedge clk)
425
    if (~sync_rst) testpoint_video <= 33'b0;
426
    else testpoint_video <= {pixel_rd_empty, pixel_en, h_sync, v_sync, v, u, y, dot_rst};
427
 
428
`endif
429
`endif
430
`endif
431
 
432
`ifndef PROBE
433
`ifndef PROBE_VIDEO
434
`ifndef PROBE_MEMORY
435
  assign testpoint = 34'hdeadbeef;
436
`endif
437
`endif
438
`endif
439
 
440
endmodule
441
/* not truncated */

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