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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [resample.v] - Blame information for rev 2

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1 2 kdv
/*
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 * resample.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * resample - Main chroma resampling module. Synchronizes resampling and motion compensation.
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 */
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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`undef CHECK
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`ifdef __IVERILOG__
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`define CHECK 1
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`endif
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module resample(
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  clk, rst,
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  output_frame, output_frame_valid, output_frame_rd,
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  progressive_sequence, progressive_frame, top_field_first, repeat_first_field, mb_width, mb_height, horizontal_size, vertical_size, resample_wr_overflow,
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  disp_wr_addr_full, disp_wr_addr_almost_full, disp_wr_addr_en, disp_wr_addr_ack, disp_wr_addr, disp_rd_dta_empty, disp_rd_dta_en, disp_rd_dta_valid, disp_rd_dta,
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  pixel_wr_almost_full, interlaced, deinterlace, persistence, repeat_frame,
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  y, u, v, osd_out, position_out, pixel_wr_en
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  );
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  input              clk;                      // clock
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  input              rst;                      // synchronous active low reset
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  input        [2:0]output_frame;              // frame to be displayed
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  input             output_frame_valid;        // asserted when output_frame valid
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  output            output_frame_rd;           // assert for next output frame
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  input             progressive_sequence;
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  input             progressive_frame;
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  input             top_field_first;
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  input             repeat_first_field;
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  input        [7:0]mb_width;                  // par. 6.3.3. width of the encoded luminance component of pictures in macroblocks
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  input        [7:0]mb_height;                 // par. 6.3.3. height of the encoded luminance component of frame pictures in macroblocks
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  input       [13:0]horizontal_size;           // par. 6.2.2.1, par. 6.3.3 
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  input       [13:0]vertical_size;             // par. 6.2.2.1, par. 6.3.3
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  /* reading reconstructed frame */
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  /* reading reconstructed frame: writing address */
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  input            disp_wr_addr_full;
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  input            disp_wr_addr_almost_full;
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  output           disp_wr_addr_en;
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  input            disp_wr_addr_ack;
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  output     [21:0]disp_wr_addr;
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  /* reading reconstructed frame: reading data */
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  input            disp_rd_dta_empty;
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  output           disp_rd_dta_en;
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  input            disp_rd_dta_valid;
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  input      [63:0]disp_rd_dta;
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  input            interlaced;                // asserted if display modeline is interlaced
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  input            deinterlace;               // asserted if video has to be deinterlaced
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  input            persistence;               // asserted if last shown image persists
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  input       [4:0]repeat_frame;
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  input              pixel_wr_almost_full;
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  output        [7:0]y;
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  output        [7:0]u;
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  output        [7:0]v;
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  output        [7:0]osd_out;
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  output        [2:0]position_out;
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  output             pixel_wr_en;
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  /* resample fifo */
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  wire          [2:0]resample_wr_dta;
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  wire               resample_wr_en;
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  output             resample_wr_overflow;           // to probe
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  wire               resample_wr_almost_full;
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  wire          [2:0]resample_rd_dta;
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  wire               resample_rd_en;
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  wire               resample_rd_valid;
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  wire               resample_addr_busy;
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  wire         [12:0]mb_width_ext = {5'b0, mb_width};
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`include "fifo_size.v"
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  // Generates the memory read requests for displaying a frame
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  resample_addrgen resample_addrgen (
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    .clk(clk),
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    .clk_en(1'b1),
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    .rst(rst),
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    .output_frame(output_frame),
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    .output_frame_valid(output_frame_valid),
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    .output_frame_rd(output_frame_rd),
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    .progressive_sequence(progressive_sequence),
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    .progressive_frame(progressive_frame),
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    .top_field_first(top_field_first),
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    .repeat_first_field(repeat_first_field),
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    .mb_width(mb_width),
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    .mb_height(mb_height),
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    .horizontal_size(horizontal_size),
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    .vertical_size(vertical_size),
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    .disp_wr_addr_full(disp_wr_addr_full),
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    .disp_wr_addr_en(disp_wr_addr_en),
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    .disp_wr_addr_ack(disp_wr_addr_ack),
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    .disp_wr_addr(disp_wr_addr),
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    .interlaced(interlaced),
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    .deinterlace(deinterlace),
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    .persistence(persistence),
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    .repeat_frame(repeat_frame),
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    .resample_wr_dta(resample_wr_dta),
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    .resample_wr_en(resample_wr_en),
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    .disp_wr_addr_almost_full(disp_wr_addr_almost_full),
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    .resample_wr_almost_full(resample_wr_almost_full),
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    .busy(resample_addr_busy)
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    );
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  wire        fifo_read;
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  wire        fifo_valid;
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  wire [127:0]fifo_osd;          /* osd data */
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  wire [127:0]fifo_y;            /* lumi */
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  wire  [63:0]fifo_u_upper;      /* chromi, upper row */
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  wire  [63:0]fifo_u_lower;      /* chromi, lower row */
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  wire  [63:0]fifo_v_upper;      /* chromi, upper row */
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  wire  [63:0]fifo_v_lower;      /* chromi, lower row */
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  wire   [2:0]fifo_position;     /* position of pixels, as in  resample_codes */
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  // Reads the pixels from memory fifo
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  resample_dta resample_dta (
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    .clk(clk),
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    .clk_en(1'b1),
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    .rst(rst),
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    .fifo_read(fifo_read),
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    .fifo_valid(fifo_valid),
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    .disp_rd_dta_empty(disp_rd_dta_empty),
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    .disp_rd_dta_en(disp_rd_dta_en),
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    .disp_rd_dta_valid(disp_rd_dta_valid),
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    .disp_rd_dta(disp_rd_dta),
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    .resample_rd_dta(resample_rd_dta),
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    .resample_rd_en(resample_rd_en),
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    .resample_rd_valid(resample_rd_valid),
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    .fifo_osd(fifo_osd),
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    .fifo_y(fifo_y),
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    .fifo_u_upper(fifo_u_upper),
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    .fifo_u_lower(fifo_u_lower),
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    .fifo_v_upper(fifo_v_upper),
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    .fifo_v_lower(fifo_v_lower),
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    .fifo_position(fifo_position)
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    );
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  // bilinear chroma upscaling, 4:2:0 to 4:4:4
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  resample_bilinear resample_bilinear (
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    .clk(clk),
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    .clk_en(1'b1),
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    .rst(rst),
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    .fifo_read(fifo_read),
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    .fifo_valid(fifo_valid),
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    .fifo_osd(fifo_osd),
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    .fifo_y(fifo_y),
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    .fifo_u_upper(fifo_u_upper),
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    .fifo_u_lower(fifo_u_lower),
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    .fifo_v_upper(fifo_v_upper),
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    .fifo_v_lower(fifo_v_lower),
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    .fifo_position(fifo_position),
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    .y(y),
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    .u(u),
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    .v(v),
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    .osd_out(osd_out),
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    .position_out(position_out),
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    .pixel_wr_en(pixel_wr_en),
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    .pixel_wr_almost_full(pixel_wr_almost_full)
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    );
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  // fifo between resample_addr and resample_dta
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  fifo_sc
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    #(.addr_width(RESAMPLE_DEPTH),
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    .dta_width(9'd3),
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    .prog_thresh(RESAMPLE_THRESHOLD))
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    resample_fifo (
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    .rst(rst),
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    .clk(clk),
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    .din(resample_wr_dta),
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    .wr_en(resample_wr_en),
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    .full(),
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    .wr_ack(),
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    .overflow(resample_wr_overflow),
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    .prog_full(resample_wr_almost_full),
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    .dout(resample_rd_dta),
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    .rd_en(resample_rd_en),
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    .prog_empty(),
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    .empty(),
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    .valid(resample_rd_valid),
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    .underflow()
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    );
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`ifdef CHECK
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  always @(posedge clk)
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    if (resample_wr_overflow)
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      begin
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        #0 $display("%m\t*** error: resample_fifo overflow. **");
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        $stop;
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      end
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`endif
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`ifdef DEBUG
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  always @(posedge clk)
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    $strobe("%m\toutput_frame: %d output_frame_valid: %d addr_clk_en: %d",
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                 output_frame, output_frame_valid, addr_clk_en);
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  always @(posedge clk)
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    if (disp_wr_addr_almost_full)
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      $display("%m\taddr_clk_en: disp_wr_addr_almost_full");
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`endif
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endmodule
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/* not truncated */

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