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[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [vbuf.v] - Blame information for rev 2

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1 2 kdv
/*
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 * vbuf.v
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 *
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 * Copyright (c) 2007 Koen De Vleeschauwer.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 */
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/*
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 * vbuf - Video Buffer
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 * Decoder input buffer.
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 * vbuf_write writes incoming mpeg2 stream to a circular buffer in memory.
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 * getbits_fifo reads the incoming mpeg2 stream from a circular buffer in memory.
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 */
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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/*
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 Converter from byte-parallel to 64-bits parallel
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 */
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module vbuf_write (
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  clk, clk_en, rst,
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  vid_in, vid_in_wr_en,
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  vid_out, vid_out_wr_en
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  );
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  input              clk;
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  input              clk_en;
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  input              rst;                      // synchronous active low reset
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  input         [7:0]vid_in;
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  input              vid_in_wr_en;
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  output reg   [63:0]vid_out;
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  output reg         vid_out_wr_en;
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  reg           [7:0]loop;
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  always @(posedge clk)
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    if (~rst) vid_out <= 64'b0;
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    else if (clk_en && vid_in_wr_en) vid_out <= {vid_out[55:0], vid_in};
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    else vid_out <= vid_out;
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  always @(posedge clk)
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    if (~rst) loop <= 8'b0;
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    else if (clk_en && vid_in_wr_en) loop <= {loop[6:0], &(~loop[6:0])};
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    else loop <= loop;
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  always @(posedge clk)
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    if (~rst) vid_out_wr_en <= 1'b0;
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    else if (clk_en && vid_in_wr_en) vid_out_wr_en <= loop[6];
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    else if (clk_en) vid_out_wr_en <= 1'b0;
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    else vid_out_wr_en <= vid_out_wr_en;
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`ifdef DEBUG
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  always @(posedge clk)
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    $strobe("%m\tvid_in: %h vid_in_wr_en: %d vid_out: %h vid_out_wr_en: %d loop: %8b",
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                 vid_in, vid_in_wr_en, vid_out, vid_out_wr_en, loop);
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`endif
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endmodule
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/* not truncated */

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