OpenCores
URL https://opencores.org/ocsvn/mpeg2fpga/mpeg2fpga/trunk

Subversion Repositories mpeg2fpga

[/] [mpeg2fpga/] [trunk/] [rtl/] [mpeg2/] [wrappers.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 kdv
/*
2
 * wrappers.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * Wrappers for dpram and fifos.
21
 * For each component, two versions are provided: one where read and write port share a common clock;
22
 * and one where read and write port have independent clocks.
23
 */
24
 
25
`undef DEBUG
26
//`define DEBUG 1
27
 
28
/* check prog_thresh is less than fifo size */
29
`undef CHECK_FIFO_PARAMS
30
`ifdef __IVERILOG__
31
`define CHECK_FIFO_PARAMS 1
32
`endif
33
 
34
/*
35
 dual-port ram with same clock for read and write port.
36
 */
37
 
38
`include "timescale.v"
39
 
40
module dpram_sc (
41
        rst,
42
        din,
43
        clk,
44
        wr_addr,
45
        wr_en,
46
        dout,
47
        rd_addr,
48
        rd_en
49
        );
50
 
51
  parameter dta_width=8;           /* Data bus width */
52
  parameter addr_width=8;          /* Address bus width, determines dpram size by evaluating 2^addr_width */
53
 
54
  input                 rst;       /* low active sync master reset */
55
  input                 clk;       /* clock */
56
                                   /* read port */
57
  output reg [dta_width-1:0]dout;      /* data output */
58
  input                 rd_en;     /* read enable */
59
  input [addr_width-1:0]rd_addr;   /* read address */
60
                                   /* write port */
61
  input  [dta_width-1:0]din;       /* data input */
62
  input                 wr_en;     /* write enable */
63
  input [addr_width-1:0]wr_addr;   /* read address */
64
 
65
  /*
66
   * More or less in the style given in XST User Guide v9.1, "RAMs and ROMs Coding Examples",
67
   * "Verilog Coding Example for Dual Port RAM With Enable On Each Port"
68
   */
69
 
70
  reg    [dta_width-1:0]ram[(1 << addr_width)-1:0];
71
 
72
  always @(posedge clk)
73
    if (~rst) dout <= 0;
74
    else if (rd_en) dout <= ram[rd_addr];
75
    else dout <= dout;
76
 
77
  always @(posedge clk)
78
    if (wr_en) ram[wr_addr] <= din;
79
 
80
`ifdef DEBUG
81
  always @(posedge clk)
82
    if (wr_en && rd_en && (rd_addr == wr_addr))
83
      $strobe("%m\tmemory collision error on address %x", rd_addr);
84
 `endif
85
 
86
endmodule
87
 
88
 
89
/*
90
 dual-port ram with different clocks for read and write port
91
 */
92
 
93
module dpram_dc (
94
        din,
95
        wr_rst,
96
        wr_clk,
97
        wr_addr,
98
        wr_en,
99
        dout,
100
        rd_rst,
101
        rd_clk,
102
        rd_addr,
103
        rd_en
104
        );
105
 
106
  parameter dta_width=8;           /* Data bus width */
107
  parameter addr_width=8;          /* Address bus width, determines dpram size by evaluating 2^addr_width */
108
 
109
                                   /* read port */
110
  output reg [dta_width-1:0]dout;      /* data output */
111
  input                 rd_rst;    /* low active master reset, sync with read clock */
112
  input                 rd_clk;    /* read clock */
113
  input                 rd_en;     /* read enable */
114
  input [addr_width-1:0]rd_addr;   /* read address */
115
                                   /* write port */
116
  input  [dta_width-1:0]din;       /* data input */
117
  input                 wr_rst;    /* low active master reset, sync with write clock */
118
  input                 wr_clk;    /* write clock */
119
  input                 wr_en;     /* write enable */
120
  input [addr_width-1:0]wr_addr;   /* read address */
121
 
122
  reg    [dta_width-1:0]ram[(1 << addr_width)-1:0];
123
 
124
  always @(posedge rd_clk)
125
    if (~rd_rst) dout <= 0;
126
    else if (rd_en) dout <= ram[rd_addr];
127
    else dout <= dout;
128
 
129
  always @(posedge wr_clk)
130
    if (wr_en) ram[wr_addr] <= din;
131
 
132
endmodule
133
 
134
/*
135
 fifo with common clock for read and write port.
136
 */
137
 
138
module fifo_sc (
139
        clk,
140
        rst,
141
        din,
142
        wr_en,
143
        full,
144
        wr_ack,
145
        overflow,
146
        prog_full,
147
        dout,
148
        rd_en,
149
        empty,
150
        valid,
151
        underflow,
152
        prog_empty
153
        );
154
 
155
  parameter [8:0]dta_width=9'd8;      /* Data bus width */
156
  parameter [8:0]addr_width=9'd8;     /* Address bus width, determines fifo size by evaluating 2^addr_width */
157
  parameter [8:0]prog_thresh=9'd1;    /* Programmable threshold constant for prog_empty and prog_full */
158
 
159
  parameter FIFO_XILINX=0;    /* use Xilinx FIFO primitives */
160
  parameter check_valid=1;    /* assign x's to fifo output when valid is not asserted */
161
 
162
  input          clk;
163
  input          rst;         /* low active sync master reset */
164
  /* read port */
165
  output [dta_width-1:0]dout; /* data output */
166
  input          rd_en;       /* read enable */
167
  output         empty;       /* asserted if fifo is empty; no additional reads can be performed */
168
  output         valid;       /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
169
  output         underflow;   /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
170
  output         prog_empty;  /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
171
  /* write port */
172
  input  [dta_width-1:0]din;  /* data input */
173
  input          wr_en;       /* write enable */
174
  output         full;        /* asserted if fifo is full; no additional writes can be performed */
175
  output         overflow;    /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
176
  output         wr_ack;      /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
177
  output         prog_full;   /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh */
178
 
179
  /* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
180
 
181
  generate
182
    if (FIFO_XILINX == 0)
183
      begin
184
        /* Implementation using "soft" fifo */
185
        xfifo_sc #(
186
          .dta_width(dta_width),
187
          .addr_width(addr_width),
188
          .prog_thresh(prog_thresh)
189
          )
190
        xfifo_sc (
191
          .clk(clk),
192
          .rst(rst),
193
          .din(din),
194
          .wr_en(wr_en),
195
          .full(full),
196
          .wr_ack(wr_ack),
197
          .overflow(overflow),
198
          .prog_full(prog_full),
199
          .dout(dout),
200
          .rd_en(rd_en),
201
          .empty(empty),
202
          .valid(valid),
203
          .underflow(underflow),
204
          .prog_empty(prog_empty)
205
          );
206
      end
207
    else
208
      begin
209
        /* Implementation using "hard" fifo */
210
        xilinx_fifo_sc #(
211
          .dta_width(dta_width),
212
          .addr_width(addr_width),
213
          .prog_thresh(prog_thresh)
214
          )
215
        xfifo_sc (
216
          .clk(clk),
217
          .rst(~rst),
218
          .din(din),
219
          .wr_en(wr_en),
220
          .full(full),
221
          .wr_ack(wr_ack),
222
          .overflow(overflow),
223
          .prog_full(prog_full),
224
          .dout(dout),
225
          .rd_en(rd_en),
226
          .empty(empty),
227
          .valid(valid),
228
          .underflow(underflow),
229
          .prog_empty(prog_empty)
230
          );
231
      end
232
  endgenerate
233
 
234
`ifdef CHECK_FIFO_PARAMS
235
  initial #0
236
      begin
237
        if (prog_thresh > (1<<addr_width))
238
          begin
239
            #0 $display ("%m\t*** error: inconsistent fifo parameters. addr_width: %d prog_thresh: %d. ***", addr_width, prog_thresh);
240
            $finish;
241
          end
242
      end
243
 
244
  always @(posedge clk)
245
    if (overflow)
246
      begin
247
        #0 $display ("%m\t*** error: fifo overflow. ***");
248
      end
249
/*
250
  always @(posedge clk)
251
    if (underflow)
252
      begin
253
        #0 $display ("%m\t*** warning: fifo underflow. ***");
254
      end
255
*/
256
`endif
257
 
258
endmodule
259
 
260
/*
261
 fifo with independent clock for read and write port.
262
 */
263
 
264
module fifo_dc (
265
        rst,
266
        wr_clk,
267
        din,
268
        wr_en,
269
        full,
270
        wr_ack,
271
        overflow,
272
        prog_full,
273
        rd_clk,
274
        dout,
275
        rd_en,
276
        empty,
277
        valid,
278
        underflow,
279
        prog_empty
280
        );
281
 
282
  parameter [8:0]dta_width=9'd8;      /* Data bus width */
283
  parameter [8:0]addr_width=9'd8;     /* Address bus width, determines fifo size by evaluating 2^addr_width */
284
  parameter [8:0]prog_thresh=9'd1;    /* Programmable threshold constant for prog_empty and prog_full */
285
 
286
  parameter FIFO_XILINX=1;    /* use Xilinx FIFO primitives */
287
  parameter check_valid=1;    /* assign x's to fifo output when valid is not asserted */
288
 
289
  input          rst;         /* low active sync master reset */
290
  /* read port */
291
  input          rd_clk;      /* read clock. positive edge active */
292
  output [dta_width-1:0]dout; /* data output */
293
  input          rd_en;       /* read enable */
294
  output         empty;       /* asserted if fifo is empty; no additional reads can be performed */
295
  output         valid;       /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
296
  output         underflow;   /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
297
  output         prog_empty;  /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
298
  /* write port */
299
  input          wr_clk;      /* write clock. positive edge active */
300
  input  [dta_width-1:0]din;  /* data input */
301
  input          wr_en;       /* write enable */
302
  output         full;        /* asserted if fifo is full; no additional writes can be performed */
303
  output         overflow;    /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
304
  output         wr_ack;      /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
305
  output         prog_full;   /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh  */
306
 
307
  /* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
308
 
309
  xilinx_fifo_dc #(
310
    .dta_width(dta_width),
311
    .addr_width(addr_width),
312
    .prog_thresh(prog_thresh)
313
    )
314
  xfifo_dc (
315
    .rst(~rst),
316
    .wr_clk(wr_clk),
317
    .din(din),
318
    .wr_en(wr_en),
319
    .full(full),
320
    .wr_ack(wr_ack),
321
    .overflow(overflow),
322
    .prog_full(prog_full),
323
    .rd_clk(rd_clk),
324
    .dout(dout),
325
    .rd_en(rd_en),
326
    .empty(empty),
327
    .valid(valid),
328
    .underflow(underflow),
329
    .prog_empty(prog_empty)
330
    );
331
 
332
`ifdef CHECK_FIFO_PARAMS
333
  initial #0
334
      begin
335
        if (prog_thresh > (1<<addr_width))
336
          begin
337
            #0 $display ("%m\t*** error: inconsistent fifo parameters. addr_width: %d prog_thresh: %d. ***", addr_width, prog_thresh);
338
            $finish;
339
          end
340
      end
341
 
342
  always @(posedge wr_clk)
343
    if (overflow)
344
      begin
345
        #0 $display ("%m\t*** error: fifo overflow. ***");
346
      end
347
/*
348
  always @(posedge rd_clk)
349
    if (underflow)
350
      begin
351
        #0 $display ("%m\t*** warning: fifo underflow. ***");
352
      end
353
*/
354
`endif
355
endmodule
356
/* not truncated */

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.