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/*
2
 * xilinx_fifo.v
3
 *
4
 * Copyright (c) 2007 Koen De Vleeschauwer.
5
 *
6
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
7
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
8
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
9
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
10
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
11
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
12
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
14
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
15
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
16
 * SUCH DAMAGE.
17
 */
18
 
19
/*
20
 * fifos, implemented using Xilinx Virtex5 primitives.
21
 * See "Virtex-5 Libraries Guide for HDL Designs", Xilinx v5ldl.
22
 * and "Virtex-5 User Guide", Xilinx ug190.
23
 *
24
 * Note when resetting Xilinx FIFO18/FIFO36 primitives:
25
 * "The reset signal must be high for at least three read clock and three write clock cycles." Caveat emptor.
26
 */
27
 
28
`include "timescale.v"
29
 
30
module xilinx_fifo (
31
  ALMOSTEMPTY,
32
  ALMOSTFULL,
33
  DO,
34
  EMPTY,
35
  FULL,
36
  RDERR,
37
  VALID,
38
  WRERR,
39
  WR_ACK,
40
  DI,
41
  RDCLK,
42
  RDEN,
43
  RST,
44
  WRCLK,
45
  WREN
46
  );
47
 
48
  parameter [9:0]ALMOST_FULL_OFFSET=9'h080;
49
  parameter [9:0]ALMOST_EMPTY_OFFSET=9'h080;
50
  parameter [9:0]DATA_WIDTH=9'd217;
51
  parameter [9:0]ADDR_WIDTH=9'd14;
52
  parameter DO_REG=1;
53
  parameter EN_SYN="FALSE";
54
 
55
  output ALMOSTEMPTY;
56
  output ALMOSTFULL;
57
  output [DATA_WIDTH-1:0]DO;
58
  output EMPTY;
59
  output FULL;
60
  output RDERR;
61
  output reg VALID;
62
  output WRERR;
63
  output reg WR_ACK;
64
  input [DATA_WIDTH-1:0]DI;
65
  input RDCLK;
66
  input RDEN;
67
  input RST;
68
  input WRCLK;
69
  input WREN;
70
 
71
  /* VALID and WR_ACK flags */
72
  always @(posedge WRCLK)
73
    if (RST) WR_ACK <= 1'b0;
74
    else WR_ACK <= WREN && ~FULL;
75
 
76
  always @(posedge RDCLK)
77
    if (RST) VALID <= 1'b0;
78
    else VALID <= RDEN && ~EMPTY;
79
 
80
  /* instantiate FIFO */
81
  generate
82
    if ((DATA_WIDTH <= 9'd4) && (ADDR_WIDTH <= 9'd12))
83
      begin
84
        wire [15:0]din;
85
        wire  [1:0]dinp;
86
        wire [15:0]dout;
87
        wire  [1:0]doutp;
88
 
89
        assign DO = dout[3:0];
90
        assign din = DI;
91
        assign dinp = 2'b0;
92
 
93
        // FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
94
        //         Virtex-5
95
        // Xilinx HDL Libraries Guide, version 8.2.2
96
        FIFO18 #(
97
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
98
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
99
           .DATA_WIDTH(9'd4),                           // Sets data width to 4, 9 or 18
100
           .DO_REG(DO_REG),                             // Enable output register (0 or 1) output register usage
101
                                                        //   Must be 1 if EN_SYN = "FALSE
102
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
103
                                                        //   or Synchronous ("TRUE")
104
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE"
105
        ) FIFO18_width_4 (
106
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
107
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
108
           .DO(dout),                                   // 16-bit data output
109
           .DOP(doutp),                                 // 2-bit parity data output
110
           .EMPTY(EMPTY),                               // 1-bit empty output flag
111
           .FULL(FULL),                                 // 1-bit full output flag
112
           .RDERR(RDERR),                               // 1-bit read error output
113
           .WRCOUNT(),                                  // 12-bit write count output
114
           .WRERR(WRERR),                               // 1-bit write error
115
           .DI(din),                                    // 16-bit data input
116
           .DIP(dinp),                                  // 2-bit parity input
117
           .RDCLK(RDCLK),                               // 1-bit read clock input
118
           .RDEN(RDEN),                                 // 1-bit read enable input
119
           .RST(RST),                                   // 1-bit reset input
120
           .WRCLK(WRCLK),                               // 1-bit write clock input
121
           .WREN(WREN)                                  // 1-bit write enable input
122
          );
123
      end
124
    else if ((DATA_WIDTH <= 9'd4) && (ADDR_WIDTH <= 9'd13))
125
      begin
126
        wire [31:0]din;
127
        wire [3:0]dinp;
128
        wire [31:0]dout;
129
        wire [3:0]doutp;
130
 
131
        assign DO = dout[3:0];
132
        assign din = DI;
133
        assign dinp = 4'b0;
134
 
135
        // FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
136
        //          Virtex-5
137
        // Xilinx HDL Libraries Guide, version 8.2.2
138
        FIFO36 #(
139
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
140
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
141
           .DATA_WIDTH(4),                              // Sets data width to 4, 9, 18 or 36
142
           .DO_REG(DO_REG),                             // Enable output register (0 or 1)register usage
143
                                                        //   Must be 1 if EN_SYN = "FALSE
144
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
145
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE
146
        ) FIFO36_width_4 (
147
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
148
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
149
           .DO(dout),                                   // 32-bit data output
150
           .DOP(doutp),                                 // 4-bit parity data output
151
           .EMPTY(EMPTY),                               // 1-bit empty output flag
152
           .FULL(FULL),                                 // 1-bit full output flag
153
           .RDCOUNT(),                                  // 13-bit read count output
154
           .RDERR(RDERR),                               // 1-bit read error output
155
           .WRCOUNT(),                                  // 13-bit write count output
156
           .WRERR(WRERR),                               // 1-bit write error
157
           .DI(din),                                    // FIFO data input, width determined by DATA_WIDTH
158
           .DIP(dinp),                                  // 4-bit parity input
159
           .RDCLK(RDCLK),                               // 1-bit read clock input
160
           .RDEN(RDEN),                                 // 1-bit read enable input
161
           .RST(RST),                                   // 1-bit reset input
162
           .WRCLK(WRCLK),                               // 1-bit write clock input
163
           .WREN(WREN)                                  // 1-bit write enable input
164
        );
165
      end
166
    else if ((DATA_WIDTH <= 9'd9) && (ADDR_WIDTH <= 9'd11))
167
      begin
168
        wire [15:0]din;
169
        wire  [1:0]dinp;
170
        wire [15:0]dout;
171
        wire  [1:0]doutp;
172
 
173
        wire [8:0]DIN = DI; // extend DI to 9 bit, if needed
174
 
175
        assign DO = {doutp[0], dout[7:0]};
176
        assign din = DIN[7:0];
177
        assign dinp = DIN[8];
178
 
179
        // FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
180
        //         Virtex-5
181
        // Xilinx HDL Libraries Guide, version 8.2.2
182
        FIFO18 #(
183
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
184
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
185
           .DATA_WIDTH(9),                              // Sets data width to 4, 9 or 18
186
           .DO_REG(DO_REG),                             // Enable output register (0 or 1) output register usage
187
                                                        //   Must be 1 if EN_SYN = "FALSE
188
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
189
                                                        //   or Synchronous ("TRUE")
190
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE"
191
        ) FIFO18_width_9 (
192
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
193
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
194
           .DO(dout),                                   // 16-bit data output
195
           .DOP(doutp),                                 // 2-bit parity data output
196
           .EMPTY(EMPTY),                               // 1-bit empty output flag
197
           .FULL(FULL),                                 // 1-bit full output flag
198
           .RDERR(RDERR),                               // 1-bit read error output
199
           .WRCOUNT(),                                  // 12-bit write count output
200
           .WRERR(WRERR),                               // 1-bit write error
201
           .DI(din),                                    // 16-bit data input
202
           .DIP(dinp),                                  // 2-bit parity input
203
           .RDCLK(RDCLK),                               // 1-bit read clock input
204
           .RDEN(RDEN),                                 // 1-bit read enable input
205
           .RST(RST),                                   // 1-bit reset input
206
           .WRCLK(WRCLK),                               // 1-bit write clock input
207
           .WREN(WREN)                                  // 1-bit write enable input
208
          );
209
      end
210
    else if ((DATA_WIDTH <= 9'd9) && (ADDR_WIDTH <= 9'd12))
211
      begin
212
        wire [31:0]din;
213
        wire [3:0]dinp;
214
        wire [31:0]dout;
215
        wire [3:0]doutp;
216
 
217
        wire [8:0]DIN = DI; // extend DI to 9 bit, if needed
218
 
219
        assign DO = {doutp[0], dout[7:0]};
220
        assign din = DIN[7:0];
221
        assign dinp = DIN[8];
222
 
223
        // FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
224
        //          Virtex-5
225
        // Xilinx HDL Libraries Guide, version 8.2.2
226
        FIFO36 #(
227
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
228
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
229
           .DATA_WIDTH(9),                              // Sets data width to 4, 9, 18 or 36
230
           .DO_REG(DO_REG),                             // Enable output register (0 or 1)register usage
231
                                                        //   Must be 1 if EN_SYN = "FALSE
232
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
233
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE
234
        ) FIFO36_width_9 (
235
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
236
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
237
           .DO(dout),                                   // 32-bit data output
238
           .DOP(doutp),                                 // 4-bit parity data output
239
           .EMPTY(EMPTY),                               // 1-bit empty output flag
240
           .FULL(FULL),                                 // 1-bit full output flag
241
           .RDCOUNT(),                                  // 13-bit read count output
242
           .RDERR(RDERR),                               // 1-bit read error output
243
           .WRCOUNT(),                                  // 13-bit write count output
244
           .WRERR(WRERR),                               // 1-bit write error
245
           .DI(din),                                    // FIFO data input, width determined by DATA_WIDTH
246
           .DIP(dinp),                                  // 4-bit parity input
247
           .RDCLK(RDCLK),                               // 1-bit read clock input
248
           .RDEN(RDEN),                                 // 1-bit read enable input
249
           .RST(RST),                                   // 1-bit reset input
250
           .WRCLK(WRCLK),                               // 1-bit write clock input
251
           .WREN(WREN)                                  // 1-bit write enable input
252
        );
253
      end
254
    else if ((DATA_WIDTH <= 9'd18) && (ADDR_WIDTH <= 9'd10))
255
      begin
256
        wire [15:0]din;
257
        wire  [1:0]dinp;
258
        wire [15:0]dout;
259
        wire  [1:0]doutp;
260
 
261
        wire [17:0]DIN = DI; // extend DI to 18 bit, if needed
262
 
263
        assign DO = {doutp, dout};
264
        assign {dinp, din} = DIN;
265
 
266
        // FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
267
        //         Virtex-5
268
        // Xilinx HDL Libraries Guide, version 8.2.2
269
        FIFO18 #(
270
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
271
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
272
           .DATA_WIDTH(18),                             // Sets data width to 4, 9 or 18
273
           .DO_REG(DO_REG),                             // Enable output register (0 or 1) output register usage
274
                                                        //   Must be 1 if EN_SYN = "FALSE
275
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
276
                                                        //   or Synchronous ("TRUE")
277
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE"
278
        ) FIFO18_width_18 (
279
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
280
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
281
           .DO(dout),                                   // 16-bit data output
282
           .DOP(doutp),                                 // 2-bit parity data output
283
           .EMPTY(EMPTY),                               // 1-bit empty output flag
284
           .FULL(FULL),                                 // 1-bit full output flag
285
           .RDERR(RDERR),                               // 1-bit read error output
286
           .WRCOUNT(),                                  // 12-bit write count output
287
           .WRERR(WRERR),                               // 1-bit write error
288
           .DI(din),                                    // 16-bit data input
289
           .DIP(dinp),                                  // 2-bit parity input
290
           .RDCLK(RDCLK),                               // 1-bit read clock input
291
           .RDEN(RDEN),                                 // 1-bit read enable input
292
           .RST(RST),                                   // 1-bit reset input
293
           .WRCLK(WRCLK),                               // 1-bit write clock input
294
           .WREN(WREN)                                  // 1-bit write enable input
295
          );
296
      end
297
    else if ((DATA_WIDTH <= 9'd18) && (ADDR_WIDTH <= 9'd11))
298
      begin
299
        wire [31:0]din;
300
        wire [3:0]dinp;
301
        wire [31:0]dout;
302
        wire [3:0]doutp;
303
 
304
        wire [17:0]DIN = DI; // extend DI to 18 bit, if needed
305
 
306
        assign DO = {doutp[1:0], dout[15:0]};
307
        assign din = DIN[15:0];
308
        assign dinp = DIN[17:16];
309
 
310
        // FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
311
        //          Virtex-5
312
        // Xilinx HDL Libraries Guide, version 8.2.2
313
        FIFO36 #(
314
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
315
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
316
           .DATA_WIDTH(18),                             // Sets data width to 4, 9, 18 or 36
317
           .DO_REG(DO_REG),                             // Enable output register (0 or 1)register usage
318
                                                        //   Must be 1 if EN_SYN = "FALSE
319
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
320
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE
321
        ) FIFO36_width_18 (
322
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
323
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
324
           .DO(dout),                                   // 32-bit data output
325
           .DOP(doutp),                                 // 4-bit parity data output
326
           .EMPTY(EMPTY),                               // 1-bit empty output flag
327
           .FULL(FULL),                                 // 1-bit full output flag
328
           .RDCOUNT(),                                  // 13-bit read count output
329
           .RDERR(RDERR),                               // 1-bit read error output
330
           .WRCOUNT(),                                  // 13-bit write count output
331
           .WRERR(WRERR),                               // 1-bit write error
332
           .DI(din),                                    // FIFO data input, width determined by DATA_WIDTH
333
           .DIP(dinp),                                  // 4-bit parity input
334
           .RDCLK(RDCLK),                               // 1-bit read clock input
335
           .RDEN(RDEN),                                 // 1-bit read enable input
336
           .RST(RST),                                   // 1-bit reset input
337
           .WRCLK(WRCLK),                               // 1-bit write clock input
338
           .WREN(WREN)                                  // 1-bit write enable input
339
        );
340
      end
341
    else if ((DATA_WIDTH <= 9'd36) && (ADDR_WIDTH <= 9'd9))
342
      begin
343
        wire [31:0]din;
344
        wire [31:0]dout;
345
        wire [3:0]dinp;
346
        wire [3:0]doutp;
347
 
348
        assign DO = {doutp, dout};
349
        assign {dinp, din} = DI;
350
 
351
        // FIFO18_36: 36x18k Synchronous/Asynchronous BlockRAM FIFO
352
        //             Virtex-5
353
        // Xilinx HDL Libraries Guide, version 8.2.2
354
        FIFO18_36 #(
355
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
356
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
357
           .DO_REG(DO_REG),                             // Enable output register (0 or 1)
358
                                                        //   Must be 1 if EN_SYN = "FALSE
359
           .EN_SYN(EN_SYN),                             // Specifies FIFO as Asynchronous ("FALSE")
360
                                                        //   or Synchronous ("TRUE")
361
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE
362
        ) FIFO18_36_width_36 (
363
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
364
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
365
           .DO(dout),                                   // 32-bit data output
366
           .DOP(doutp),                                 // 4-bit parity data output
367
           .EMPTY(EMPTY),                               // 1-bit empty output flag
368
           .FULL(FULL),                                 // 1-bit full output flag
369
           .RDCOUNT(),                                  // 9-bit read count output
370
           .RDERR(RDERR),                               // 1-bit read error output
371
           .WRCOUNT(),                                  // 9-bit write count output
372
           .WRERR(WRERR),                               // 1-bit write error
373
           .DI(din),                                    // 32-bit data input
374
           .DIP(dinp),                                  // 4-bit parity input
375
           .RDCLK(RDCLK),                               // 1-bit read clock input
376
           .RDEN(RDEN),                                 // 1-bit read enable input
377
           .RST(RST),                                   // 1-bit reset input
378
           .WRCLK(WRCLK),                               // 1-bit write clock input
379
           .WREN(WREN)                                  // 1-bit write enable input
380
        );
381
      end
382
    else if ((DATA_WIDTH <= 9'd36) && (ADDR_WIDTH <= 9'd10))
383
      begin
384
        wire [31:0]din;
385
        wire [3:0]dinp;
386
        wire [31:0]dout;
387
        wire [3:0]doutp;
388
 
389
        assign DO = {doutp, dout};
390
        assign {dinp, din} = DI;
391
 
392
        // FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
393
        //          Virtex-5
394
        // Xilinx HDL Libraries Guide, version 8.2.2
395
        FIFO36 #(
396
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
397
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
398
           .DATA_WIDTH(36),                             // Sets data width to 4, 9, 18 or 36
399
           .DO_REG(DO_REG),                             // Enable output register (0 or 1)register usage
400
                                                        //   Must be 1 if EN_SYN = "FALSE
401
           .EN_SYN(EN_SYN),                             // FALSE when using independent read/write clocks; TRUE when using the same clock
402
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE
403
        ) FIFO36_width_36 (
404
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
405
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
406
           .DO(dout),                                   // 32-bit data output
407
           .DOP(doutp),                                 // 4-bit parity data output
408
           .EMPTY(EMPTY),                               // 1-bit empty output flag
409
           .FULL(FULL),                                 // 1-bit full output flag
410
           .RDCOUNT(),                                  // 13-bit read count output
411
           .RDERR(RDERR),                               // 1-bit read error output
412
           .WRCOUNT(),                                  // 13-bit write count output
413
           .WRERR(WRERR),                               // 1-bit write error
414
           .DI(din),                                    // FIFO data input, width determined by DATA_WIDTH
415
           .DIP(dinp),                                  // 4-bit parity input
416
           .RDCLK(RDCLK),                               // 1-bit read clock input
417
           .RDEN(RDEN),                                 // 1-bit read enable input
418
           .RST(RST),                                   // 1-bit reset input
419
           .WRCLK(WRCLK),                               // 1-bit write clock input
420
           .WREN(WREN)                                  // 1-bit write enable input
421
        );
422
      end
423
    else if ((DATA_WIDTH <= 9'd72) && (ADDR_WIDTH <= 9'd9))
424
      begin
425
        wire [63:0]din;
426
        wire [63:0]dout;
427
        wire [7:0]dinp;
428
        wire [7:0]doutp;
429
 
430
        assign DO = {doutp, dout};
431
        assign {dinp, din} = DI;
432
 
433
        // FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO /w ECC
434
        //             Virtex-5
435
        // Xilinx HDL Libraries Guide, version 8.2.2
436
        FIFO36_72 #(
437
           .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),     // Sets almost full threshold
438
           .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),   // Sets the almost empty threshold
439
           .DO_REG(DO_REG),                             // Enable output register (0 or 1)
440
                                                        //   Must be 1 if EN_SYN = "FALSE
441
           .EN_ECC_READ("FALSE"),                       // Enable ECC decoder, "TRUE" or "FALSE
442
           .EN_ECC_WRITE("FALSE"),                      // Enable ECC encoder, "TRUE" or "FALSE
443
           .EN_SYN(EN_SYN),                             // Specifies FIFO as Asynchronous ("FALSE")
444
                                                        //   or Synchronous ("TRUE")
445
           .FIRST_WORD_FALL_THROUGH("FALSE")            // Sets the FIFO FWFT to "TRUE" or "FALSE
446
        ) FIFO36_72_width_72 (
447
           .ALMOSTEMPTY(ALMOSTEMPTY),                   // 1-bit almost empty output flag
448
           .ALMOSTFULL(ALMOSTFULL),                     // 1-bit almost full output flag
449
           .DBITERR(),                                  // 1-bit double bit error status output
450
           .DO(dout),                                   // 32-bit data output
451
           .DOP(doutp),                                 // 4-bit parity data output
452
           .ECCPARITY(),                                // 8-bit generated error correction parity
453
           .EMPTY(EMPTY),                               // 1-bit empty output flag
454
           .FULL(FULL),                                 // 1-bit full output flag
455
           .RDCOUNT(),                                  // 9-bit read count output
456
           .RDERR(RDERR),                               // 1-bit read error output
457
           .SBITERR(),                                  // 1-bit single bit error status output
458
           .WRCOUNT(),                                  // 9-bit write count output
459
           .WRERR(WRERR),                               // 1-bit write error
460
           .DI(din),                                    // 32-bit data input
461
           .DIP(dinp),                                  // 4-bit parity input
462
           .RDCLK(RDCLK),                               // 1-bit read clock input
463
           .RDEN(RDEN),                                 // 1-bit read enable input
464
           .RST(RST),                                   // 1-bit reset input
465
           .WRCLK(WRCLK),                               // 1-bit write clock input
466
           .WREN(WREN)                                  // 1-bit write enable input
467
        );
468
        // End of FIFO36_72_inst instantiation
469
      end
470
    else if ((DATA_WIDTH <= 9'd144) && (ADDR_WIDTH <= 9'd9))
471
      begin
472
        wire [143:0]din;
473
        wire [143:0]dout;
474
        assign DO = dout;
475
        assign din = DI;
476
 
477
        // FIFO144: 144x36k Synchronous/Asynchronous BlockRAM FIFO
478
        //             Virtex-5
479
        //
480
        FIFO144 #(
481
          .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
482
          .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
483
          .DO_REG(DO_REG),
484
          .EN_SYN(EN_SYN)
485
          )
486
        FIFO144_width_144 (
487
          .ALMOSTEMPTY(ALMOSTEMPTY),
488
          .ALMOSTFULL(ALMOSTFULL),
489
          .DO(dout),
490
          .EMPTY(EMPTY),
491
          .FULL(FULL),
492
          .RDERR(RDERR),
493
          .WRERR(WRERR),
494
          .DI(din),
495
          .RDCLK(RDCLK),
496
          .RDEN(RDEN),
497
          .RST(RST),
498
          .WRCLK(WRCLK),
499
          .WREN(WREN)
500
          );
501
      end
502
    else if ((DATA_WIDTH <= 9'd216) && (ADDR_WIDTH <= 9'd9))
503
      begin
504
        wire [215:0]din;
505
        wire [215:0]dout;
506
        assign DO = dout;
507
        assign din = DI;
508
 
509
        // FIFO216: 216x36k Synchronous/Asynchronous BlockRAM FIFO
510
        //             Virtex-5
511
        //
512
        FIFO216 #(
513
          .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
514
          .ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
515
          .DO_REG(DO_REG),
516
          .EN_SYN(EN_SYN)
517
          )
518
        FIFO216_width_216 (
519
          .ALMOSTEMPTY(ALMOSTEMPTY),
520
          .ALMOSTFULL(ALMOSTFULL),
521
          .DO(dout),
522
          .EMPTY(EMPTY),
523
          .FULL(FULL),
524
          .RDERR(RDERR),
525
          .WRERR(WRERR),
526
          .DI(din),
527
          .RDCLK(RDCLK),
528
          .RDEN(RDEN),
529
          .RST(RST),
530
          .WRCLK(WRCLK),
531
          .WREN(WREN)
532
          );
533
      end
534
    else
535
      begin
536
        /*
537
         * No suitable FIFO found. Generate error.
538
         */
539
        initial $display("%m: fifo parameter error. DATA_WIDTH=%0d ADDR_WIDTH=%0d ALMOST_FULL_OFFSET=%0d ALMOST_EMPTY_OFFSET=%0d", DATA_WIDTH, ADDR_WIDTH, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET);
540
        assign ALMOSTEMPTY = 1'bx;
541
        assign ALMOSTFULL = 1'bx;
542
        assign EMPTY = 1'bx;
543
        assign FULL = 1'bx;
544
        assign RDERR = 1'bx;
545
        assign WRERR = 1'bx;
546
        assign DO = {144{1'bx}};
547
        initial $stop;
548
      end
549
  endgenerate
550
 
551
`ifdef CHECK_GENERATE
552
  initial
553
    $display("%m: fifo parameters: DATA_WIDTH=%0d ADDR_WIDTH=%0d ALMOST_FULL_OFFSET=%0d ALMOST_EMPTY_OFFSET=%0d DO_REG=%0d EN_SYN=%s",
554
      DATA_WIDTH, ADDR_WIDTH, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET, DO_REG, EN_SYN);
555
`endif
556
 
557
//`ifdef CHECK_FIFO_PARAMS
558
   initial #0
559
     begin
560
       if (  ((EN_SYN == "TRUE")  && ((ALMOST_FULL_OFFSET < 13'd1) || (ALMOST_EMPTY_OFFSET < 13'd1)))
561
          || ((EN_SYN == "FALSE") && ((ALMOST_FULL_OFFSET < 13'd4) || (ALMOST_EMPTY_OFFSET < 13'd5))) )
562
         begin
563
           #0 $display ("%m\t*** error: inconsistent fifo parameters. ALMOST_FULL_OFFSET: %d ALMOST_EMPTY_OFFSET: %d. ***", ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET);
564
           $finish;
565
         end
566
     end
567
//`endif
568
 
569
endmodule
570
/* not truncated */

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