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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc9_pkg::*;
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module mpmc9_ack_gen(rst, clk, state, ch, cs, adr, cr, wr, to, taghit,
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resv_ch, resv_adr, ack, pre_ack);
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parameter N = 0;
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input rst;
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input clk;
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input [3:0] state;
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input [3:0] ch;
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input cs;
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input [31:0] adr;
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input cr;
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input wr;
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input to;
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input taghit;
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input [3:0] resv_ch [0:NAR-1];
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input [31:0] resv_adr [0:NAR-1];
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output reg ack;
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output reg pre_ack;
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integer n;
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reg [7:0] ack_pipe;
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// Setting ack output
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// Ack takes place outside of a state so that reads from different read caches
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// may occur at the same time.
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always_ff @(posedge clk)
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if (rst)
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ack_pipe <= 'd0;
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else begin
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ack_pipe <= {ack_pipe[6:0],ack_pipe[0]};
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// Reads: the ack doesn't happen until the data's been cached. If there is
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// cached data we give an ack right away.
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if (taghit)
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ack_pipe[0] <= 8'd1;
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if (state==IDLE) begin
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if (cr) begin
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ack_pipe <= 8'hFF;
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for (n = 0; n < NAR; n = n + 1)
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if ((resv_ch[n]==N) && (resv_adr[n][31:4]==adr[31:4])) begin
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ack_pipe <= 'd0;
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end
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end
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end
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// Write: an ack can be sent back as soon as the write state is reached..
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if ((state==PRESET1 && wr) || to)
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if (ch==N)
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ack_pipe <= 8'hFF;
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// Clear the ack when the circuit is de-selected.
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if (!cs)
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ack_pipe <= 'd0;
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ack <= ack_pipe[7];
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pre_ack <= ack_pipe[0];
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end
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endmodule
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