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rockee |
#!/usr/bin/env python
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# -*- coding: utf-8 -*-
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"""
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emulator.py
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===========
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An Emulator for MicroBlaze INA
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:copyright: Copyright (c) 2010 Jian Luo
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:author-email: jian.luo.cn(at_)gmail.com
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:license: LGPL, see LICENSE for details
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:revision: $Id: emulator.py 6 2010-11-21 23:18:44Z rockee $
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"""
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from random import randrange
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from myhdl import *
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operations = """
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| ADD | Rd,Ra,Rb | 000000 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra
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| RSUB | Rd,Ra,Rb | 000001 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra + 1
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| ADDC | Rd,Ra,Rb | 000010 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra + C
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| RSUBC | Rd,Ra,Rb | 000011 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra + C
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| ADDK | Rd,Ra,Rb | 000100 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra
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| RSUBK | Rd,Ra,Rb | 000101 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra + 1
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| ADDKC | Rd,Ra,Rb | 000110 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra + C
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| RSUBKC | Rd,Ra,Rb | 000111 | Rd | Ra | Rb & 00000000000 | Rd := Rb + Ra + C
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| CMP | Rd,Ra,Rb | 000101 | Rd | Ra | Rb & 00000000001 | Rd := Rb + Ra + 1
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Rd[0] := 0 if (Rb >= Ra) else
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Rd[0] := 1
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| CMPU | Rd,Ra,Rb | 000101 | Rd | Ra | Rb & 00000000011 | Rd := Rb + Ra + 1 (unsigned)
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Rd[0] := 0 if (Rb >= Ra, unsigned) else
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Rd[0] := 1
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| ADDI | Rd,Ra,Imm | 001000 | Rd | Ra | Imm | Rd := s(Imm) + Ra
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| RSUBI | Rd,Ra,Imm | 001001 | Rd | Ra | Imm | Rd := s(Imm) + Ra + 1
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| ADDIC | Rd,Ra,Imm | 001010 | Rd | Ra | Imm | Rd := s(Imm) + Ra + C
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| RSUBIC | Rd,Ra,Imm | 001011 | Rd | Ra | Imm | Rd := s(Imm) + Ra + C
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| ADDIK | Rd,Ra,Imm | 001100 | Rd | Ra | Imm | Rd := s(Imm) + Ra
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| RSUBIK | Rd,Ra,Imm | 001101 | Rd | Ra | Imm | Rd := s(Imm) + Ra + 1
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| ADDIKC | Rd,Ra,Imm | 001110 | Rd | Ra | Imm | Rd := s(Imm) + Ra + C
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| RSUBIKC | Rd,Ra,Imm | 001111 | Rd | Ra | Imm | Rd := s(Imm) + Ra + C
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#| MUL | Rd,Ra,Rb | 010000 | Rd | Ra | Rb & 00000000000 | Rd := Ra * Rb
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#| MULH | Rd,Ra,Rb | 010000 | Rd | Ra | Rb & 00000000001 | Rd := (Ra * Rb) >> 32 (signed)
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#| MULHU | Rd,Ra,Rb | 010000 | Rd | Ra | Rb & 00000000011 | Rd := (Ra * Rb) >> 32 (unsigned)
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#| MULHSU | Rd,Ra,Rb | 010000 | Rd | Ra | Rb & 00000000010 | Rd := (Ra, signed * Rb, unsigned) >> 32 (signed)
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#| BSRA | Rd,Ra,Rb | 010001 | Rd | Ra | Rb & 01000000000 | Rd := s(Ra >> Rb)
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#| BSLL | Rd,Ra,Rb | 010001 | Rd | Ra | Rb & 10000000000 | Rd := (Ra << Rb) & 0
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#| MULI | Rd,Ra,Imm | 011000 | Rd | Ra | Imm | Rd := Ra * s(Imm)
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#| BSRLI | Rd,Ra,Imm | 011001 | Rd | Ra | 00000000000 & Imm5 | Rd := 0 & (Ra >> Imm5)
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#| BSRAI | Rd,Ra,Imm | 011001 | Rd | Ra | 00000010000 & Imm5 | Rd := s(Ra >> Imm5)
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#| BSLLI | Rd,Ra,Imm | 011001 | Rd | Ra | 00000100000 & Imm5 | Rd := (Ra << Imm5) & 0
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#| IDIV | Rd,Ra,Rb | 010010 | Rd | Ra | Rb & 00000000000 | Rd := Rb/Ra
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#| IDIVU | Rd,Ra,Rb | 010010 | Rd | Ra | Rb & 00000000010 | Rd := Rb/Ra, unsigned
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#| TNEAGETD | Rd,Rb | 010011 | Rd | 00000 | Rb & 0N0TAE00000 | Rd := FSL Rb[28:31] (data read)
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#MSR[FSL] := 1 if (FSL_S_Control = 1)
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#MSR[C] := not FSL_S_Exists if N = 1
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#| TNAPUTD | Ra,Rb | 010011 | 00000 | Ra | Rb & 0N0TA000000 | FSL Rb[28:31] := Ra (data write)
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#MSR[C] := FSL_M_Full if N = 1
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#| TNECAGETD | Rd,Rb | 010011 | Rd | 00000 | Rb & 0N1TAE00000 | Rd := FSL Rb[28:31] (control read)
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#MSR[FSL] := 1 if (FSL_S_Control = 0)
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#MSR[C] := not FSL_S_Exists if N = 1
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#| TNCAPUTD | Ra,Rb | 010011 | 00000 | Ra | Rb & 0N1TA000000 | FSL Rb[28:31] := Ra (control write)
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#MSR[C] := FSL_M_Full if N = 1
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#Rd := Rb+Ra, float1
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#FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000
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#Rd := Rb-Ra, float1
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#FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000
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#Rd := Rb*Ra, float1
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#FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000
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#Rd := Rb/Ra, float1
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#FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000
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#Rd := 1 if (Rb = NaN or Ra = NaN, float1)
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#FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000
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#else
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#Rd := 0
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#Rd := 1 if (Rb < Ra, float1) else
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#FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000
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#Rd := 0
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#Rd := 1 if (Rb = Ra, float1) else
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#FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000
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#Rd := 0
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#Rd := 1 if (Rb <= Ra, float1) else
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#FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000
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#Rd := 0
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#Rd := 1 if (Rb > Ra, float1) else
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#FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000
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#Rd := 0
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#Rd := 1 if (Rb != Ra, float1) else
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#FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000
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#Rd := 0
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#Rd := 1 if (Rb >= Ra, float1) else
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#FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000
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#Rd := 0
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#Rd := float (Ra)1
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#FLT Rd,Ra 010110 Rd Ra 0 01010000000
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#Rd := int (Ra)1
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#FINT Rd,Ra 010110 Rd Ra 0 01100000000
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#Rd := sqrt (Ra)1
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#FSQRT Rd,Ra 010110 Rd Ra 0 01110000000
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#| TNEAGET | Rd,FSLx | 011011 | Rd | 00000 | 0N0TAE000000 & FSLx | Rd := FSLx (data read, blocking if N = 0)
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#MSR[FSL] := 1 if (FSLx_S_Control = 1)
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#MSR[C] := not FSLx_S_Exists if N = 1
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#| TNAPUT | Ra,FSLx | 011011 | 00000 | Ra | 1N0TA0000000 & FSLx | FSLx := Ra (data write, blocking if N = 0)
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#MSR[C] := FSLx_M_Full if N = 1
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#| TNECAGET | Rd,FSLx | 011011 | Rd | 00000 | 0N1TAE000000 & FSLx | Rd := FSLx (control read, blocking if N = 0)
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#MSR[FSL] := 1 if (FSLx_S_Control = 0)
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#MSR[C] := not FSLx_S_Exists if N = 1
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#| TNCAPUT | Ra,FSLx | 011011 | 00000 | Ra | 1N1TA0000000 & FSLx | FSLx := Ra (control write, blocking if N = 0)
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#MSR[C] := FSLx_M_Full if N = 1
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| OR | Rd,Ra,Rb | 100000 | Rd | Ra | Rb & 00000000000 | Rd := Ra or Rb
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| AND | Rd,Ra,Rb | 100001 | Rd | Ra | Rb & 00000000000 | Rd := Ra and Rb
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| XOR | Rd,Ra,Rb | 100010 | Rd | Ra | Rb & 00000000000 | Rd := Ra xor Rb
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| ANDN | Rd,Ra,Rb | 100011 | Rd | Ra | Rb & 00000000000 | Rd := Ra and Rb
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#| PCMPBF | Rd,Ra,Rb | 100000 | Rd | Ra | Rb & 10000000000 | Rd := 1 if (Rb[0:7] = Ra[0:7]) else
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Rd := 2 if (Rb[8:15] = Ra[8:15]) else
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Rd := 3 if (Rb[16:23] = Ra[16:23]) else
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Rd := 4 if (Rb[24:31] = Ra[24:31]) else
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Rd := 0
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#PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000 Rd := 1 if (Rd = Ra) else
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#Rd := 0
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#PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000 Rd := 1 if (Rd != Ra) else
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#Rd := 0
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| SRA | Rd,Ra | 100100 | Rd | Ra | 0000000000000001 | Rd := s(Ra >> 1)
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C := Ra[31]
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| SRC | Rd,Ra | 100100 | Rd | Ra | 0000000000100001 | Rd := C & (Ra >> 1)
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C := Ra[31]
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| SRL | Rd,Ra | 100100 | Rd | Ra | 0000000001000001 | Rd := 0 & (Ra >> 1)
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C := Ra[31]
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| SEXT8 | Rd,Ra | 100100 | Rd | Ra | 0000000001100000 | Rd := s(Ra[24:31])
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| SEXT16 | Rd,Ra | 100100 | Rd | Ra | 0000000001100001 | Rd := s(Ra[16:31])
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#WIC Ra,Rb 100100 00000 Ra Rb 01101000 ICache_Line[Ra >> 4].Tag := 0 if
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#(C_ICACHE_LINE_LEN = 4)
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#ICache_Line[Ra >> 5].Tag := 0 if
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#(C_ICACHE_LINE_LEN = 8)
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#WDC Ra,Rb 100100 00000 Ra Rb 01100100 DCache_Line[Ra >> 4].Tag := 0 if
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#(C_DCACHE_LINE_LEN = 4)
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#DCache_Line[Ra >> 5].Tag := 0 if
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#(C_DCACHE_LINE_LEN = 8)
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#| MTS | Sd,Ra | 100101 | 00000 | Ra | 11 & Sd | SPR[Sd] := Ra, where:
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#• SPR[0x0001] is MSR
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#• SPR[0x0007] is FSR
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#• SPR[0x1000] is PID
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#• SPR[0x1001] is ZPR
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#• SPR[0x1002] is TLBX
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#• SPR[0x1003] is TLBLO
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#• SPR[0x1004] is TLBHI
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#• SPR[0x1005] is TLBSX
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#| MFS | Rd,Sa | 100101 | Rd | 00000 | 10 & Sa | Rd := SPR[Sa], where:
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#• SPR[0x0000] is PC
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#• SPR[0x0001] is MSR
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#• SPR[0x0003] is EAR
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#• SPR[0x0005] is ESR
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#• SPR[0x0007] is FSR
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#• SPR[0x000B] is BTR
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#• SPR[0x000D] is EDR
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#• SPR[0x1000] is PID
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#• SPR[0x1001] is ZPR
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#• SPR[0x1002] is TLBX
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#• SPR[0x1003] is TLBLO
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#• SPR[0x1004] is TLBHI
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#• SPR[0x2000 to 0x200B] is PVR[0 to 11]
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#| MSRCLR | Rd,Imm | 100101 | Rd | 00001 | 00 & Imm14 | Rd := MSR
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#MSR := MSR and Imm14
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#| MSRSET | Rd,Imm | 100101 | Rd | 00000 | 00 & Imm14 | Rd := MSR
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#MSR := MSR or Imm14
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| BR | Rb | 100110 | 00000 | 00000 | Rb & 00000000000 | PC := PC + Rb
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| BRD | Rb | 100110 | 00000 | 10000 | Rb & 00000000000 | PC := PC + Rb
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| BRLD | Rd,Rb | 100110 | Rd | 10100 | Rb & 00000000000 | PC := PC + Rb
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Rd := PC
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| BRA | Rb | 100110 | 00000 | 01000 | Rb & 00000000000 | PC := Rb
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| BRAD | Rb | 100110 | 00000 | 11000 | Rb & 00000000000 | PC := Rb
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| BRALD | Rd,Rb | 100110 | Rd | 11100 | Rb & 00000000000 | PC := Rb
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Rd := PC
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| BRK | Rd,Rb | 100110 | Rd | 01100 | Rb & 00000000000 | PC := Rb
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Rd := PC
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MSR[BIP] := 1
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| BEQ | Ra,Rb | 100111 | 00000 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra = 0
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| BNE | Ra,Rb | 100111 | 00001 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra != 0
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| BLT | Ra,Rb | 100111 | 00010 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra < 0
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| 182 |
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| BLE | Ra,Rb | 100111 | 00011 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra <= 0
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| 183 |
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| BGT | Ra,Rb | 100111 | 00100 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra > 0
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| 184 |
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| BGE | Ra,Rb | 100111 | 00101 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra >= 0
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| 185 |
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| BEQD | Ra,Rb | 100111 | 10000 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra = 0
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| 186 |
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| BNED | Ra,Rb | 100111 | 10001 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra != 0
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| 187 |
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| BLTD | Ra,Rb | 100111 | 10010 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra < 0
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| 188 |
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| BLED | Ra,Rb | 100111 | 10011 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra <= 0
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| 189 |
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| BGTD | Ra,Rb | 100111 | 10100 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra > 0
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| 190 |
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| BGED | Ra,Rb | 100111 | 10101 | Ra | Rb & 00000000000 | PC := PC + Rb if Ra >= 0
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| 191 |
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| ORI | Rd,Ra,Imm | 101000 | Rd | Ra | Imm | Rd := Ra or s(Imm)
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| 192 |
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| ANDI | Rd,Ra,Imm | 101001 | Rd | Ra | Imm | Rd := Ra and s(Imm)
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| 193 |
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| XORI | Rd,Ra,Imm | 101010 | Rd | Ra | Imm | Rd := Ra xor s(Imm)
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| 194 |
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| ANDNI | Rd,Ra,Imm | 101011 | Rd | Ra | Imm | Rd := Ra and s(Imm)
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| 195 |
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| 196 |
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| 197 |
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| IMM | Imm | 101100 | 00000 | 00000 | Imm | Imm[0:15] := Imm
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| 198 |
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| RTSD | Ra,Imm | 101101 | 10000 | Ra | Imm | PC := Ra + s(Imm)
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| 199 |
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| RTID | Ra,Imm | 101101 | 10001 | Ra | Imm | PC := Ra + s(Imm)
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| 200 |
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MSR[IE] := 1
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| 201 |
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| RTBD | Ra,Imm | 101101 | 10010 | Ra | Imm | PC := Ra + s(Imm)
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| 202 |
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MSR[BIP] := 0
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| 203 |
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| RTED | Ra,Imm | 101101 | 10100 | Ra | Imm | PC := Ra + s(Imm)
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| 204 |
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MSR[EE] := 1, MSR[EIP] := 0
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| 205 |
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ESR := 0
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| 206 |
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| BRI | Imm | 101110 | 00000 | 00000 | Imm | PC := PC + s(Imm)
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| 207 |
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| BRID | Imm | 101110 | 00000 | 10000 | Imm | PC := PC + s(Imm)
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| 208 |
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| BRLID | Rd,Imm | 101110 | Rd | 10100 | Imm | PC := PC + s(Imm)
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| 209 |
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Rd := PC
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| 210 |
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| BRAI | Imm | 101110 | 00000 | 01000 | Imm | PC := s(Imm)
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| 211 |
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| BRAID | Imm | 101110 | 00000 | 11000 | Imm | PC := s(Imm)
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| 212 |
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| BRALID | Rd,Imm | 101110 | Rd | 11100 | Imm | PC := s(Imm)
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| 213 |
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Rd := PC
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| 214 |
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| BRKI | Rd,Imm | 101110 | Rd | 01100 | Imm | PC := s(Imm)
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| 215 |
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Rd := PC
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| 216 |
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MSR[BIP] := 1
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| 217 |
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| BEQI | Ra,Imm | 101111 | 00000 | Ra | Imm | PC := PC + s(Imm) if Ra = 0
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| 218 |
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| BNEI | Ra,Imm | 101111 | 00001 | Ra | Imm | PC := PC + s(Imm) if Ra != 0
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| 219 |
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| BLTI | Ra,Imm | 101111 | 00010 | Ra | Imm | PC := PC + s(Imm) if Ra < 0
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| 220 |
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| BLEI | Ra,Imm | 101111 | 00011 | Ra | Imm | PC := PC + s(Imm) if Ra <= 0
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| 221 |
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| BGTI | Ra,Imm | 101111 | 00100 | Ra | Imm | PC := PC + s(Imm) if Ra > 0
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| 222 |
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| BGEI | Ra,Imm | 101111 | 00101 | Ra | Imm | PC := PC + s(Imm) if Ra >= 0
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| 223 |
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| BEQID | Ra,Imm | 101111 | 10000 | Ra | Imm | PC := PC + s(Imm) if Ra = 0
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| 224 |
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| BNEID | Ra,Imm | 101111 | 10001 | Ra | Imm | PC := PC + s(Imm) if Ra != 0
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| 225 |
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| BLTID | Ra,Imm | 101111 | 10010 | Ra | Imm | PC := PC + s(Imm) if Ra < 0
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| 226 |
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| BLEID | Ra,Imm | 101111 | 10011 | Ra | Imm | PC := PC + s(Imm) if Ra <= 0
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| 227 |
|
|
| BGTID | Ra,Imm | 101111 | 10100 | Ra | Imm | PC := PC + s(Imm) if Ra > 0
|
| 228 |
|
|
| BGEID | Ra,Imm | 101111 | 10101 | Ra | Imm | PC := PC + s(Imm) if Ra >= 0
|
| 229 |
|
|
| LBU | Rd,Ra,Rb | 110000 | Rd | Ra | Rb & 00000000000 | Addr := Ra + Rb
|
| 230 |
|
|
Rd[0:23] := 0
|
| 231 |
|
|
Rd[24:31] := *Addr[0:7]
|
| 232 |
|
|
| LHU | Rd,Ra,Rb | 110001 | Rd | Ra | Rb & 00000000000 | Addr := Ra + Rb
|
| 233 |
|
|
Rd[0:15] := 0
|
| 234 |
|
|
Rd[16:31] := *Addr[0:15]
|
| 235 |
|
|
| LW | Rd,Ra,Rb | 110010 | Rd | Ra | Rb & 00000000000 | Addr := Ra + Rb
|
| 236 |
|
|
Rd := *Addr
|
| 237 |
|
|
| SB | Rd,Ra,Rb | 110100 | Rd | Ra | Rb & 00000000000 | Addr := Ra + Rb
|
| 238 |
|
|
*Addr[0:8] := Rd[24:31]
|
| 239 |
|
|
| SH | Rd,Ra,Rb | 110101 | Rd | Ra | Rb & 00000000000 | Addr := Ra + Rb
|
| 240 |
|
|
*Addr[0:16] := Rd[16:31]
|
| 241 |
|
|
| SW | Rd,Ra,Rb | 110110 | Rd | Ra | Rb & 00000000000 | Addr := Ra + Rb
|
| 242 |
|
|
*Addr := Rd
|
| 243 |
|
|
| LBUI | Rd,Ra,Imm | 111000 | Rd | Ra | Imm | Addr := Ra + s(Imm)
|
| 244 |
|
|
Rd[0:23] := 0
|
| 245 |
|
|
Rd[24:31] := *Addr[0:7]
|
| 246 |
|
|
| LHUI | Rd,Ra,Imm | 111001 | Rd | Ra | Imm | Addr := Ra + s(Imm)
|
| 247 |
|
|
Rd[0:15] := 0
|
| 248 |
|
|
Rd[16:31] := *Addr[0:15]
|
| 249 |
|
|
| LWI | Rd,Ra,Imm | 111010 | Rd | Ra | Imm | Addr := Ra + s(Imm)
|
| 250 |
|
|
Rd := *Addr
|
| 251 |
|
|
| SBI | Rd,Ra,Imm | 111100 | Rd | Ra | Imm | Addr := Ra + s(Imm)
|
| 252 |
|
|
*Addr[0:7] := Rd[24:31]
|
| 253 |
|
|
| SHI | Rd,Ra,Imm | 111101 | Rd | Ra | Imm | Addr := Ra + s(Imm)
|
| 254 |
|
|
*Addr[0:15] := Rd[16:31]
|
| 255 |
|
|
| SWI | Rd,Ra,Imm | 111110 | Rd | Ra | Imm | Addr := Ra + s(Imm)
|
| 256 |
|
|
*Addr := Rd
|
| 257 |
|
|
"""
|
| 258 |
|
|
|
| 259 |
|
|
OPC_SFT = 26
|
| 260 |
|
|
OPC_MSK = 0x3f
|
| 261 |
|
|
REG_MSK = 0x1f
|
| 262 |
|
|
RD_SFT = 21
|
| 263 |
|
|
RA_SFT = 16
|
| 264 |
|
|
RB_SFT = 11
|
| 265 |
|
|
IMM_MSK = 0xffff
|
| 266 |
|
|
|
| 267 |
|
|
# mask
|
| 268 |
|
|
OPC_IMM = 0x08
|
| 269 |
|
|
ADDSUB_K = 0x04
|
| 270 |
|
|
ADDSUB_C = 0x02
|
| 271 |
|
|
SUB_CMP = 0x01
|
| 272 |
|
|
SUB_CMPU = 0x02
|
| 273 |
|
|
|
| 274 |
|
|
import sys
|
| 275 |
|
|
|
| 276 |
|
|
QUIET=1
|
| 277 |
|
|
def log(string, params, file=sys.stdout):
|
| 278 |
|
|
if QUIET:
|
| 279 |
|
|
return
|
| 280 |
|
|
params.update(
|
| 281 |
|
|
rd = params['r'][params['d']],
|
| 282 |
|
|
ra = params['r'][params['a']],
|
| 283 |
|
|
rb = params['r'][params['b']],
|
| 284 |
|
|
)
|
| 285 |
|
|
print >>file, string.format(**params)
|
| 286 |
|
|
|
| 287 |
|
|
def log_gpr(params, file=sys.stdout):
|
| 288 |
|
|
if QUIET:
|
| 289 |
|
|
return
|
| 290 |
|
|
print >>file, '\tGPRF:\t',
|
| 291 |
|
|
for i, v in enumerate(params['r']):
|
| 292 |
|
|
print >>file, '%8x' % v,
|
| 293 |
|
|
if i%8 == 7:
|
| 294 |
|
|
print >>file, '\n\t\t',
|
| 295 |
|
|
print >>file, ''
|
| 296 |
|
|
|
| 297 |
|
|
def log_spr(params, file=sys.stdout):
|
| 298 |
|
|
if QUIET:
|
| 299 |
|
|
#print '{pc:x}'.format(**params)
|
| 300 |
|
|
return
|
| 301 |
|
|
|
| 302 |
|
|
print >>file, '{steps}:\tPC={pc:#x}\tCarry={m[0]:d}'.format(**params)
|
| 303 |
|
|
|
| 304 |
|
|
__max = 0x7fffffff
|
| 305 |
|
|
__min = 0x80000000
|
| 306 |
|
|
|
| 307 |
|
|
def _signed32(v):
|
| 308 |
|
|
return (v & __max) - (v & __min)
|
| 309 |
|
|
|
| 310 |
|
|
def _signed16(v):
|
| 311 |
|
|
return (v % (2**15)) - (v & (1<<15))
|
| 312 |
|
|
|
| 313 |
|
|
_umax = 0xffffffff
|
| 314 |
|
|
_max = _signed32(__max)
|
| 315 |
|
|
_min = _signed32(__min)
|
| 316 |
|
|
|
| 317 |
|
|
class MyBlazeEmulator(object):
|
| 318 |
|
|
|
| 319 |
6 |
rockee |
def __init__(self, filename='rom.vmem', max_steps=1000):
|
| 320 |
2 |
rockee |
ram = read_vmem(filename)
|
| 321 |
|
|
print 'size=%d' % len(ram)
|
| 322 |
6 |
rockee |
fetch(ram, max_steps=max_steps)
|
| 323 |
2 |
rockee |
|
| 324 |
|
|
def addi(d, a, i, k, c, r, m, **kw):
|
| 325 |
|
|
x = _signed32(r[a]) + _signed32(i) + (bool(c) & m[0])
|
| 326 |
|
|
r[d] = _signed32(x)
|
| 327 |
|
|
m[0] = m[0] if k else not (_min <= x <= _max)
|
| 328 |
|
|
|
| 329 |
|
|
def add(b, r, i=None, **kw):
|
| 330 |
|
|
addi(i=r[b], r=r, **kw)
|
| 331 |
|
|
|
| 332 |
|
|
def rsubi(d, a, i, k, c, r, m, **kw):
|
| 333 |
|
|
x = _signed32(i) - _signed32(r[a]) - (bool(c) & m[0])
|
| 334 |
|
|
r[d] = _signed32(x)
|
| 335 |
|
|
m[0] = m[0] if k else not (_min <= x <= _max)
|
| 336 |
|
|
|
| 337 |
|
|
def rsub(b, r, i=None, **kw):
|
| 338 |
|
|
rsubi(i=r[b], r=r, **kw)
|
| 339 |
|
|
|
| 340 |
|
|
def cmp(d, a, b, u, r, m, **kw):
|
| 341 |
|
|
rsub(d=d, a=a, b=b, k=True, c=False, r=r, m=m, **kw)
|
| 342 |
|
|
#if u:
|
| 343 |
|
|
#if (r[a] & _umax) > (r[b] & _umax):
|
| 344 |
|
|
#r[d] |= __min
|
| 345 |
|
|
#else:
|
| 346 |
|
|
#r[d] &= __max
|
| 347 |
|
|
#r[d] = _signed32(r[d])
|
| 348 |
|
|
if u and (r[a] & __min) ^ (r[b] & __min):
|
| 349 |
|
|
msb = r[a] & __min
|
| 350 |
|
|
r[d] = _signed32((r[d]&__max) | msb)
|
| 351 |
|
|
|
| 352 |
|
|
def sra(d, a, r, m, **kw):
|
| 353 |
|
|
msb = (bool(r[a]&__min)) << 31
|
| 354 |
|
|
m[0] = r[d] & 1
|
| 355 |
|
|
r[d] = _signed32(msb | (r[d] >> 1))
|
| 356 |
|
|
|
| 357 |
|
|
def src(d, r, m, **kw):
|
| 358 |
|
|
msb = m[0] << 31
|
| 359 |
|
|
m[0] = r[d] & 1
|
| 360 |
|
|
r[d] = _signed32(msb | (r[d] >> 1))
|
| 361 |
|
|
|
| 362 |
|
|
def srl(d, r, m, **kw):
|
| 363 |
|
|
m[0] = r[d] & 1
|
| 364 |
|
|
r[d] = _signed32((r[d] >> 1))
|
| 365 |
|
|
|
| 366 |
|
|
def sext8(d, a, r, **kw):
|
| 367 |
|
|
if (r[a] & 0x80):
|
| 368 |
|
|
r[d] = _signed32(0xffffff00 | r[a])
|
| 369 |
|
|
else:
|
| 370 |
|
|
r[d] = _signed32(0xff & r[a])
|
| 371 |
|
|
|
| 372 |
|
|
def sext16(d, a, r, **kw):
|
| 373 |
|
|
if (r[a] & 0x8000):
|
| 374 |
|
|
r[d] = _signed32(0xffff0000 | r[a])
|
| 375 |
|
|
else:
|
| 376 |
|
|
r[d] = _signed32(0xffff & r[a])
|
| 377 |
|
|
|
| 378 |
|
|
def bri(d, i, ab, ln, pc, r, **kw):
|
| 379 |
|
|
if ln:
|
| 380 |
|
|
r[d] = pc
|
| 381 |
|
|
return i if ab else pc + i
|
| 382 |
|
|
|
| 383 |
|
|
def br(b, r, i=None, **kw):
|
| 384 |
|
|
return bri(i=r[b], r=r, **kw)
|
| 385 |
|
|
|
| 386 |
|
|
def logici(d, a, i, op, r, **kw):
|
| 387 |
|
|
ra = r[a]
|
| 388 |
|
|
r[d] = _signed32([ra | i, ra & i, ra ^ i, ~ra & i][op])
|
| 389 |
|
|
|
| 390 |
|
|
def logic(b, r, i=None, **kw):
|
| 391 |
|
|
logici(i=r[b], r=r, **kw)
|
| 392 |
|
|
|
| 393 |
|
|
def bcci(a, i, op, pc, r, **kw):
|
| 394 |
|
|
ra = _signed32(r[a])
|
| 395 |
|
|
branch = [ra == 0,
|
| 396 |
|
|
ra != 0,
|
| 397 |
|
|
ra < 0,
|
| 398 |
|
|
ra <= 0,
|
| 399 |
|
|
ra > 0,
|
| 400 |
|
|
ra >= 0][op]
|
| 401 |
|
|
return pc+i if branch else None
|
| 402 |
|
|
|
| 403 |
|
|
def bcc(b, r, i=None, **kw):
|
| 404 |
|
|
return bcc(i=r[b], r=r, **kw)
|
| 405 |
|
|
|
| 406 |
|
|
def loadi(d, a, i, op, r, ram, **kw):
|
| 407 |
|
|
addr = r[a] + i
|
| 408 |
|
|
if op == 0:
|
| 409 |
|
|
r[d] = ram[addr]
|
| 410 |
|
|
elif op == 1:
|
| 411 |
|
|
r[d] = (ram[addr]<<8) + ram[addr+1]
|
| 412 |
|
|
else:
|
| 413 |
|
|
r[d] = _signed32((ram[addr]<<24) +(ram[addr+1]<<16)
|
| 414 |
|
|
+(ram[addr+2]<<8) +ram[addr+3])
|
| 415 |
|
|
#print 'load@r[%d]: %s' % (d,r[d])
|
| 416 |
|
|
|
| 417 |
|
|
def load(b, r, i=None, **kw):
|
| 418 |
|
|
loadi(i=r[b], r=r, **kw)
|
| 419 |
|
|
|
| 420 |
|
|
def storei(d, a, i, op, r, ram, **kw):
|
| 421 |
|
|
addr = r[a] + i
|
| 422 |
|
|
if addr<0:
|
| 423 |
6 |
rockee |
# UART Emulation
|
| 424 |
2 |
rockee |
if addr == -64:
|
| 425 |
|
|
sys.stdout.write(chr(r[d] & 0xff))
|
| 426 |
|
|
sys.stdout.flush()
|
| 427 |
|
|
#else:
|
| 428 |
|
|
#print 'store@%#x <- r[%d]=%d' % (addr&_umax, d, r[d])
|
| 429 |
|
|
return
|
| 430 |
|
|
if op == 0:
|
| 431 |
|
|
ram[addr] = r[d] & 0xff
|
| 432 |
|
|
elif op == 1:
|
| 433 |
|
|
ram[addr] = (r[d] >> 8) & 0xff
|
| 434 |
|
|
ram[addr+1] = r[d] & 0xff
|
| 435 |
|
|
else:
|
| 436 |
|
|
ram[addr] = (r[d] >> 24) & 0xff
|
| 437 |
|
|
ram[addr+1] = (r[d] >> 16) & 0xff
|
| 438 |
|
|
ram[addr+2] = (r[d] >> 8) & 0xff
|
| 439 |
|
|
ram[addr+3] = r[d] & 0xff
|
| 440 |
|
|
|
| 441 |
|
|
def store(b, r, i=None, **kw):
|
| 442 |
|
|
storei(i=r[b], r=r, **kw)
|
| 443 |
|
|
|
| 444 |
|
|
def dec_store(opcode, **kw):
|
| 445 |
|
|
op = opcode & 0x03
|
| 446 |
|
|
kw.update(
|
| 447 |
|
|
op_name = ['sb', 'sh', 'sw'][op],
|
| 448 |
|
|
op = op,
|
| 449 |
|
|
)
|
| 450 |
|
|
if opcode & OPC_IMM:
|
| 451 |
|
|
storei(**kw)
|
| 452 |
|
|
log('\t\t{op_name}i\tr{d}({rd}), r{a}({ra}), {i}', kw)
|
| 453 |
|
|
else:
|
| 454 |
|
|
store(**kw)
|
| 455 |
|
|
log('\t\t{op_name}\tr{d}({rd}), r{a}({ra}), r{b}({rb})', kw)
|
| 456 |
|
|
|
| 457 |
|
|
def dec_load(opcode, **kw):
|
| 458 |
|
|
op = opcode & 0x03
|
| 459 |
|
|
kw.update(
|
| 460 |
|
|
op_name = ['lbu', 'lhu', 'lw'][op],
|
| 461 |
|
|
op = op,
|
| 462 |
|
|
)
|
| 463 |
|
|
if opcode & OPC_IMM:
|
| 464 |
|
|
loadi(**kw)
|
| 465 |
|
|
log('\t\t{op_name}i\tr{d}({rd}), r{a}({ra}), {i}', kw)
|
| 466 |
|
|
else:
|
| 467 |
|
|
load(**kw)
|
| 468 |
|
|
log('\t\t{op_name}\tr{d}({rd}), r{a}({ra}), r{b}({rb})', kw)
|
| 469 |
|
|
|
| 470 |
|
|
|
| 471 |
|
|
def dec_add(opcode, **kw):
|
| 472 |
|
|
kw.update(
|
| 473 |
|
|
k = ['','k'][bool(opcode & ADDSUB_K)],
|
| 474 |
|
|
c = ['','c'][bool(opcode & ADDSUB_C)],
|
| 475 |
|
|
)
|
| 476 |
|
|
if opcode & OPC_IMM:
|
| 477 |
|
|
addi(**kw)
|
| 478 |
|
|
log('\t\taddi{k}{c}\tr{d}({rd}), r{a}({ra}), {i}', kw)
|
| 479 |
|
|
else:
|
| 480 |
|
|
add(**kw)
|
| 481 |
|
|
log('\t\tadd{k}{c}\tr{d}({rd}), r{a}({ra}), r{b}({rb})', kw)
|
| 482 |
|
|
|
| 483 |
|
|
def dec_sub(opcode, **kw):
|
| 484 |
|
|
i = kw['i']
|
| 485 |
|
|
kw.update(
|
| 486 |
|
|
k = ['','k'][bool(opcode & ADDSUB_K)],
|
| 487 |
|
|
c = ['','c'][bool(opcode & ADDSUB_C)],
|
| 488 |
|
|
u = ['','u'][bool(i & SUB_CMPU)],
|
| 489 |
|
|
)
|
| 490 |
|
|
if opcode & OPC_IMM:
|
| 491 |
|
|
rsubi(**kw)
|
| 492 |
|
|
log('\t\trsubi{k}{c}\tr{d}({rd}), r{a}({ra}), {i}', kw)
|
| 493 |
|
|
elif not i & SUB_CMP:
|
| 494 |
|
|
rsub(**kw)
|
| 495 |
|
|
log('\t\trsub{k}{c}\tr{d}({rd}), r{a}({ra}), r{b}({rb})', kw)
|
| 496 |
|
|
else:
|
| 497 |
|
|
cmp(**kw)
|
| 498 |
|
|
log('\t\tcmp{u}\tr{d}({rd}), r{a}({ra}), r{b}({rb})', kw)
|
| 499 |
|
|
|
| 500 |
|
|
def dec_logic(opcode, **kw):
|
| 501 |
|
|
op = opcode & 0x03
|
| 502 |
|
|
kw.update(
|
| 503 |
|
|
op=op,
|
| 504 |
|
|
op_name=['or', 'and', 'xor', 'andn'][op]
|
| 505 |
|
|
)
|
| 506 |
|
|
if opcode & OPC_IMM:
|
| 507 |
|
|
logici(**kw)
|
| 508 |
|
|
log('\t\t{op_name}i\tr{d}({rd}), r{a}({ra}), {i}', kw)
|
| 509 |
|
|
else:
|
| 510 |
|
|
logic(**kw)
|
| 511 |
|
|
log('\t\t{op_name}\tr{d}({rd}), r{a}({ra}), r{b}({rb})', kw)
|
| 512 |
|
|
|
| 513 |
|
|
EXT_MAPPING = dict(
|
| 514 |
|
|
sra = (0b0000001, 0b1111111, sra),
|
| 515 |
|
|
src = (0b0100001, 0b1111111, src),
|
| 516 |
|
|
srl = (0b1000001, 0b1111111, srl),
|
| 517 |
|
|
sext8 = (0b1100000, 0b1111111, sext8),
|
| 518 |
|
|
sext16= (0b1100001, 0b1111111, sext16),
|
| 519 |
|
|
)
|
| 520 |
|
|
|
| 521 |
|
|
def dec_extended(opcode, **kw):
|
| 522 |
|
|
i = kw['i']
|
| 523 |
|
|
for op_name, (value, mask, func) in EXT_MAPPING.items():
|
| 524 |
|
|
if (i & mask) == value:
|
| 525 |
|
|
func(**kw)
|
| 526 |
|
|
kw['op_name'] = op_name
|
| 527 |
|
|
log('\t\t{op_name}\tr{d}({rd}), r{a}({ra})', kw)
|
| 528 |
|
|
|
| 529 |
|
|
def dec_ret(**kw):
|
| 530 |
|
|
a = kw['a']
|
| 531 |
|
|
r = kw['r']
|
| 532 |
|
|
i = kw['i']
|
| 533 |
|
|
next = r[a] + i
|
| 534 |
|
|
log('\t\trtsd\tr{a}({ra}), {i}', kw)
|
| 535 |
|
|
return next, True
|
| 536 |
|
|
|
| 537 |
|
|
def dec_br(opcode, **kw):
|
| 538 |
|
|
a = kw['a']
|
| 539 |
|
|
dl = ['', 'd'][bool(a & 0b10000)]
|
| 540 |
|
|
kw.update(
|
| 541 |
|
|
ln = ['', 'l'][bool(a & 0b00100)],
|
| 542 |
|
|
ab = ['', 'a'][bool(a & 0b01000)],
|
| 543 |
|
|
dl = dl,
|
| 544 |
|
|
)
|
| 545 |
|
|
if opcode & OPC_IMM:
|
| 546 |
|
|
next = bri(**kw)
|
| 547 |
|
|
if kw['ln']:
|
| 548 |
|
|
log('\t\tbr{ab}li{dl}\tr{d}({rd}), {i}', kw)
|
| 549 |
|
|
else:
|
| 550 |
|
|
log('\t\tbr{ab}i{dl}\t{i}', kw)
|
| 551 |
|
|
else:
|
| 552 |
|
|
next = br(**kw)
|
| 553 |
|
|
if kw['ln']:
|
| 554 |
|
|
log('\t\tbr{ab}l{dl}\tr{d}({rd}), {i}', kw)
|
| 555 |
|
|
else:
|
| 556 |
|
|
log('\t\tbr{ab}{dl}\t{i}', kw)
|
| 557 |
|
|
return next, bool(dl)
|
| 558 |
|
|
|
| 559 |
|
|
def dec_bcc(opcode, **kw):
|
| 560 |
|
|
d = kw['d']
|
| 561 |
|
|
a = kw['a']
|
| 562 |
|
|
b = kw['b']
|
| 563 |
|
|
i = kw['i']
|
| 564 |
|
|
r = kw['r']
|
| 565 |
|
|
op = d & 0b111
|
| 566 |
|
|
dl = ['', 'd'][bool(d & 0b10000)]
|
| 567 |
|
|
kw.update(
|
| 568 |
|
|
op_name = ['beq', 'bne', 'blt', 'ble', 'bgt', 'bge'][op],
|
| 569 |
|
|
op = op,
|
| 570 |
|
|
dl = dl,
|
| 571 |
|
|
)
|
| 572 |
|
|
#print dl, d
|
| 573 |
|
|
if opcode & OPC_IMM:
|
| 574 |
|
|
next = bcci(**kw)
|
| 575 |
|
|
log('\t\t{op_name}i{dl}\tr{a}({ra}), {i}', kw)
|
| 576 |
|
|
else:
|
| 577 |
|
|
next = bcc(**kw)
|
| 578 |
|
|
log('\t\t{op_name}{dl}\tr{a}({ra}), r{b}({rb})', kw)
|
| 579 |
|
|
if next:
|
| 580 |
|
|
return next, bool(dl)
|
| 581 |
|
|
|
| 582 |
|
|
def dec_imm(i, imm, **kw):
|
| 583 |
|
|
imm[0] = i
|
| 584 |
|
|
kw.update(i=i)
|
| 585 |
|
|
log('\t\timm\t{i}', kw)
|
| 586 |
|
|
|
| 587 |
|
|
# value, mask
|
| 588 |
|
|
OPGROUP_MAPPING = dict(
|
| 589 |
|
|
DEC_ADD = ( 0b0, 0b110001, dec_add),
|
| 590 |
|
|
DEC_SUB = ( 0b1, 0b110001, dec_sub),
|
| 591 |
|
|
DEC_LOG = (0b100000, 0b110100, dec_logic),
|
| 592 |
|
|
DEC_IMM = (0b101100, 0b111111, dec_imm),
|
| 593 |
|
|
DEC_EXT = (0b100100, 0b111111, dec_extended),
|
| 594 |
|
|
DEC_RET = (0b101101, 0b111111, dec_ret),
|
| 595 |
|
|
DEC_BR = (0b100110, 0b110111, dec_br),
|
| 596 |
|
|
DEC_BCC = (0b100111, 0b110111, dec_bcc),
|
| 597 |
|
|
DEC_LD = (0b110000, 0b110100, dec_load),
|
| 598 |
|
|
DEC_ST = (0b110100, 0b110100, dec_store),
|
| 599 |
|
|
)
|
| 600 |
|
|
|
| 601 |
|
|
def decode(instruction, pc, r, m, imm, ram, steps):
|
| 602 |
|
|
opcode = (instruction >> OPC_SFT) & OPC_MSK
|
| 603 |
|
|
|
| 604 |
|
|
# Process immediate
|
| 605 |
|
|
i = instruction & IMM_MSK
|
| 606 |
|
|
if imm[0] is not None:
|
| 607 |
|
|
i += imm[0]<<16
|
| 608 |
|
|
imm[0] = None
|
| 609 |
|
|
i = _signed32(i)
|
| 610 |
|
|
else:
|
| 611 |
|
|
#if (i & 0x8000):
|
| 612 |
|
|
#i |= 0xffff0000
|
| 613 |
|
|
#else:
|
| 614 |
|
|
#i &= 0xffff
|
| 615 |
|
|
i = _signed16(i)
|
| 616 |
|
|
|
| 617 |
|
|
kw = dict(
|
| 618 |
|
|
instruction=instruction,
|
| 619 |
|
|
opcode = opcode,
|
| 620 |
|
|
d = (instruction >> RD_SFT) & REG_MSK,
|
| 621 |
|
|
a = (instruction >> RA_SFT) & REG_MSK,
|
| 622 |
|
|
b = (instruction >> RB_SFT) & REG_MSK,
|
| 623 |
|
|
i = i,
|
| 624 |
|
|
pc = pc,
|
| 625 |
|
|
r = r,
|
| 626 |
|
|
m = m,
|
| 627 |
|
|
imm = imm,
|
| 628 |
|
|
ram = ram,
|
| 629 |
|
|
steps = steps,
|
| 630 |
|
|
)
|
| 631 |
|
|
for value, mask, func in OPGROUP_MAPPING.values():
|
| 632 |
|
|
if (opcode & mask) == value:
|
| 633 |
|
|
log_spr(kw)
|
| 634 |
|
|
result = func(**kw)
|
| 635 |
|
|
log_gpr(kw)
|
| 636 |
|
|
return result
|
| 637 |
|
|
|
| 638 |
|
|
def fetch(ram, pc=0, max_steps=-1, single=False):
|
| 639 |
|
|
r = [0]*32 # gprf
|
| 640 |
|
|
m = [0]*32 # msr
|
| 641 |
|
|
imm = [None] # immediate
|
| 642 |
|
|
steps = 0
|
| 643 |
|
|
delayed = False
|
| 644 |
|
|
while steps != max_steps:
|
| 645 |
|
|
instruction = (ram[pc]<<24) +(ram[pc+1]<<16) +(ram[pc+2]<<8) +ram[pc+3]
|
| 646 |
|
|
kw = dict(
|
| 647 |
|
|
r=r,m=m,imm=imm,pc=pc,
|
| 648 |
|
|
ram=ram,
|
| 649 |
|
|
instruction=instruction,
|
| 650 |
|
|
steps=steps,
|
| 651 |
|
|
)
|
| 652 |
|
|
result = decode(**kw)
|
| 653 |
|
|
if result is not None:
|
| 654 |
|
|
next, delay = result
|
| 655 |
|
|
#print next, delay
|
| 656 |
|
|
|
| 657 |
|
|
if single:
|
| 658 |
|
|
raw_input('Press [Any-Key] to continue ;)')
|
| 659 |
|
|
steps += 1
|
| 660 |
|
|
|
| 661 |
|
|
if delayed:
|
| 662 |
|
|
pc = branch_target
|
| 663 |
|
|
delayed = False
|
| 664 |
|
|
#print 'delayed'
|
| 665 |
|
|
elif result is None:
|
| 666 |
|
|
pc += 4
|
| 667 |
|
|
delayed = False
|
| 668 |
|
|
#print 'normal'
|
| 669 |
|
|
elif delay:
|
| 670 |
|
|
pc += 4
|
| 671 |
|
|
delayed = True
|
| 672 |
|
|
branch_target = next
|
| 673 |
|
|
#print 'delay'
|
| 674 |
|
|
else:
|
| 675 |
|
|
pc = next
|
| 676 |
|
|
delayed = False
|
| 677 |
|
|
#print 'branch'
|
| 678 |
|
|
#print '%x, %s' % (pc, delay)
|
| 679 |
|
|
|
| 680 |
|
|
def read_vmem(filename, bank=4, width=8):
|
| 681 |
|
|
print filename
|
| 682 |
|
|
source = open(filename).readlines()
|
| 683 |
|
|
ram = []
|
| 684 |
|
|
for line in source:
|
| 685 |
|
|
value = int(line.strip(), 16)
|
| 686 |
|
|
for i in range(bank):
|
| 687 |
|
|
ram.append((value >> (width*(bank-1-i))) % (2**width))
|
| 688 |
|
|
return ram
|
| 689 |
|
|
|
| 690 |
|
|
|
| 691 |
|
|
|
| 692 |
|
|
import sys
|
| 693 |
|
|
if __name__ == '__main__':
|
| 694 |
6 |
rockee |
MyBlazeEmulator(sys.argv[1], max_steps=2000)
|
| 695 |
2 |
rockee |
|
| 696 |
|
|
### EOF ###
|
| 697 |
|
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
| 698 |
|
|
|
