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Release 10.1.03 - xst K.39 (lin64)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to /home/daniel/Sources/myblaze/system/uart_test_top/xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Parameter xsthdpdir set to /home/daniel/Sources/myblaze/system/uart_test_top/xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Reading design: SysTop.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "SysTop.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "SysTop"
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Output Format : NGC
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Target Device : xc3s500e-4-fg320
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---- Source Options
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Top Module Name : SysTop
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 24
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Library Search Order : SysTop.lso
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Keep Hierarchy : NO
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Netlist Hierarchy : as_optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../rtl/SysTop.v" in library work
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Module compiled
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No errors in compilation
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Analysis of file <"SysTop.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 667: reading initialization file "rom0.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 680: reading initialization file "rom1.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 693: reading initialization file "rom2.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 706: reading initialization file "rom3.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 732: reading initialization file "rom0.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 745: reading initialization file "rom1.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 758: reading initialization file "rom2.vmem".
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INFO:Xst:2546 - "../../rtl/SysTop.v" line 771: reading initialization file "rom3.vmem".
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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INFO:Xst:1433 - Contents of array may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Calling function .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000001 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register in unit has a constant value of 0000 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic.
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INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic.
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Synthesizing Unit .
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Related source file is "../../rtl/SysTop.v".
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 235 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 236 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 237 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 238 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 239 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 240 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 241 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 242 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 243 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 244 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 245 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 246 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 247 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 248 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 249 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 250 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 251 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 252 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 253 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 254 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 255 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 256 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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| 257 |
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 2048x8-bit dual-port RAM for signal .
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Found 32x32-bit dual-port RAM for signal .
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Found 32x32-bit dual-port RAM for signal .
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Found 32x32-bit dual-port RAM for signal .
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Register equivalent to has been removed
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Using one-hot encoding for signal .
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Using one-hot encoding for signal .
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Using one-hot encoding for signal .
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Using one-hot encoding for signal .
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Using one-hot encoding for signal .
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|
|
INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 1343 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
|
| 279 |
|
|
- add an 'INIT' attribute on signal (optimization is then done without any risk)
|
| 280 |
|
|
- use the attribute 'signal_encoding user' to avoid onehot optimization
|
| 281 |
|
|
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
|
| 282 |
|
|
Using one-hot encoding for signal .
|
| 283 |
|
|
Using one-hot encoding for signal .
|
| 284 |
|
|
Using one-hot encoding for signal .
|
| 285 |
|
|
Found 1-bit register for signal .
|
| 286 |
|
|
Found 1-bit register for signal .
|
| 287 |
|
|
Found 16-bit adder for signal <$add0000> created at line 813.
|
| 288 |
|
|
Found 4-bit adder for signal <$add0001> created at line 1557.
|
| 289 |
|
|
Found 4-bit adder for signal <$add0002> created at line 1559.
|
| 290 |
|
|
Found 4-bit adder for signal <$add0003> created at line 1599.
|
| 291 |
|
|
Found 4-bit adder for signal <$add0004> created at line 1655.
|
| 292 |
|
|
Found 4-bit adder for signal <$add0005> created at line 1657.
|
| 293 |
|
|
Found 4-bit adder for signal <$add0006> created at line 1697.
|
| 294 |
|
|
Found 20-bit adder for signal <$add0007> created at line 1757.
|
| 295 |
|
|
Found 1-bit register for signal .
|
| 296 |
|
|
Found 1-bit register for signal .
|
| 297 |
|
|
Found 16-bit register for signal .
|
| 298 |
|
|
Found 32-bit register for signal .
|
| 299 |
|
|
Found 1-bit register for signal .
|
| 300 |
|
|
Found 16-bit register for signal .
|
| 301 |
|
|
Found 5-bit register for signal .
|
| 302 |
|
|
Found 1-bit register for signal .
|
| 303 |
|
|
Found 32-bit register for signal .
|
| 304 |
|
|
Found 1-bit register for signal .
|
| 305 |
|
|
Found 1-bit register for signal .
|
| 306 |
|
|
Found 16-bit register for signal .
|
| 307 |
|
|
Found 3-bit register for signal .
|
| 308 |
|
|
Found 32-bit register for signal .
|
| 309 |
|
|
Found 1-bit register for signal .
|
| 310 |
|
|
Found 1-bit register for signal .
|
| 311 |
|
|
Found 5-bit register for signal .
|
| 312 |
|
|
Found 1-bit register for signal .
|
| 313 |
|
|
Found 16-bit register for signal .
|
| 314 |
|
|
Found 32-bit register for signal .
|
| 315 |
|
|
Found 32-bit register for signal .
|
| 316 |
|
|
Found 32-bit register for signal .
|
| 317 |
|
|
Found 32-bit register for signal .
|
| 318 |
|
|
Found 1-bit register for signal .
|
| 319 |
|
|
Found 5-bit register for signal .
|
| 320 |
|
|
Found 1-bit register for signal .
|
| 321 |
|
|
Found 3-bit register for signal .
|
| 322 |
|
|
Found 7-bit register for signal .
|
| 323 |
|
|
Found 4-bit register for signal .
|
| 324 |
|
|
Found 4-bit register for signal .
|
| 325 |
|
|
Found 8-bit register for signal .
|
| 326 |
|
|
Found 4-bit register for signal .
|
| 327 |
|
|
Found 1-bit register for signal .
|
| 328 |
|
|
Found 1-bit register for signal .
|
| 329 |
|
|
Found 32-bit register for signal .
|
| 330 |
|
|
Found 5-bit register for signal .
|
| 331 |
|
|
Found 1-bit register for signal .
|
| 332 |
|
|
Found 32-bit register for signal .
|
| 333 |
|
|
Found 1-bit register for signal .
|
| 334 |
|
|
Found 1-bit register for signal .
|
| 335 |
|
|
Found 16-bit register for signal .
|
| 336 |
|
|
Found 5-bit register for signal .
|
| 337 |
|
|
Found 5-bit register for signal .
|
| 338 |
|
|
Found 1-bit register for signal .
|
| 339 |
|
|
Found 3-bit register for signal .
|
| 340 |
|
|
Found 20-bit register for signal .
|
| 341 |
|
|
Found 32-bit register for signal .
|
| 342 |
|
|
Found 28-bit comparator greatequal for signal created at line 1725.
|
| 343 |
|
|
Found 32-bit comparator less for signal created at line 1721.
|
| 344 |
|
|
Found 32-bit register for signal .
|
| 345 |
|
|
Found 5-bit comparator equal for signal created at line 962.
|
| 346 |
|
|
Found 5-bit comparator equal for signal created at line 962.
|
| 347 |
|
|
Found 5-bit comparator equal for signal created at line 967.
|
| 348 |
|
|
Found 32-bit register for signal .
|
| 349 |
|
|
Found 5-bit comparator equal for signal created at line 274.
|
| 350 |
|
|
Found 5-bit comparator equal for signal created at line 308.
|
| 351 |
|
|
Found 5-bit comparator equal for signal created at line 342.
|
| 352 |
|
|
Found 5-bit comparator equal for signal created at line 420.
|
| 353 |
|
|
Found 5-bit comparator equal for signal created at line 432.
|
| 354 |
|
|
Found 5-bit comparator equal for signal created at line 444.
|
| 355 |
|
|
Found 5-bit comparator equal for signal created at line 456.
|
| 356 |
|
|
Found 5-bit comparator equal for signal created at line 468.
|
| 357 |
|
|
Found 5-bit comparator equal for signal created at line 503.
|
| 358 |
|
|
Found 16-bit down counter for signal .
|
| 359 |
|
|
Found 4-bit register for signal .
|
| 360 |
|
|
Found 4-bit register for signal .
|
| 361 |
|
|
Found 1-bit register for signal .
|
| 362 |
|
|
Found 8-bit register for signal .
|
| 363 |
|
|
Found 4-bit register for signal .
|
| 364 |
|
|
Found 4-bit register for signal .
|
| 365 |
|
|
Found 9-bit register for signal .
|
| 366 |
|
|
Found 1-bit register for signal .
|
| 367 |
|
|
Found 1-bit register for signal .
|
| 368 |
|
|
Found 16-bit down counter for signal .
|
| 369 |
|
|
Found 4-bit register for signal .
|
| 370 |
|
|
Found 4-bit register for signal .
|
| 371 |
|
|
Found 1-bit register for signal .
|
| 372 |
|
|
Found 1-bit register for signal .
|
| 373 |
|
|
Found 1-bit register for signal .
|
| 374 |
|
|
Found 8-bit register for signal .
|
| 375 |
|
|
Found 4-bit register for signal .
|
| 376 |
|
|
Found 4-bit subtractor for signal created at line 1601.
|
| 377 |
|
|
Found 4-bit register for signal .
|
| 378 |
|
|
Found 1-bit register for signal .
|
| 379 |
|
|
Found 1-bit register for signal .
|
| 380 |
|
|
Found 9-bit register for signal .
|
| 381 |
|
|
Found 1-bit register for signal .
|
| 382 |
|
|
Found 1-bit register for signal .
|
| 383 |
|
|
Summary:
|
| 384 |
|
|
inferred 11 RAM(s).
|
| 385 |
|
|
inferred 2 Counter(s).
|
| 386 |
|
|
inferred 645 D-type flip-flop(s).
|
| 387 |
|
|
inferred 10 Adder/Subtractor(s).
|
| 388 |
|
|
inferred 14 Comparator(s).
|
| 389 |
|
|
inferred 192 Multiplexer(s).
|
| 390 |
|
|
Unit synthesized.
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
=========================================================================
|
| 394 |
|
|
HDL Synthesis Report
|
| 395 |
|
|
|
| 396 |
|
|
Macro Statistics
|
| 397 |
|
|
# RAMs : 11
|
| 398 |
|
|
2048x8-bit dual-port RAM : 8
|
| 399 |
|
|
32x32-bit dual-port RAM : 3
|
| 400 |
|
|
# Adders/Subtractors : 10
|
| 401 |
|
|
16-bit adder : 1
|
| 402 |
|
|
20-bit adder : 1
|
| 403 |
|
|
34-bit adder : 1
|
| 404 |
|
|
4-bit adder : 6
|
| 405 |
|
|
4-bit subtractor : 1
|
| 406 |
|
|
# Counters : 2
|
| 407 |
|
|
16-bit down counter : 2
|
| 408 |
|
|
# Registers : 77
|
| 409 |
|
|
1-bit register : 29
|
| 410 |
|
|
16-bit register : 5
|
| 411 |
|
|
20-bit register : 1
|
| 412 |
|
|
3-bit register : 3
|
| 413 |
|
|
32-bit register : 10
|
| 414 |
|
|
4-bit register : 10
|
| 415 |
|
|
5-bit register : 6
|
| 416 |
|
|
7-bit register : 1
|
| 417 |
|
|
8-bit register : 11
|
| 418 |
|
|
9-bit register : 1
|
| 419 |
|
|
# Comparators : 14
|
| 420 |
|
|
28-bit comparator greatequal : 1
|
| 421 |
|
|
32-bit comparator less : 1
|
| 422 |
|
|
5-bit comparator equal : 12
|
| 423 |
|
|
# Multiplexers : 6
|
| 424 |
|
|
32-bit 4-to-1 multiplexer : 6
|
| 425 |
|
|
# Xors : 2
|
| 426 |
|
|
1-bit xor2 : 1
|
| 427 |
|
|
32-bit xor2 : 1
|
| 428 |
|
|
|
| 429 |
|
|
=========================================================================
|
| 430 |
|
|
|
| 431 |
|
|
=========================================================================
|
| 432 |
|
|
* Advanced HDL Synthesis *
|
| 433 |
|
|
=========================================================================
|
| 434 |
|
|
|
| 435 |
|
|
Loading device for application Rf_Device from file '3s500e.nph' in environment /home/daniel/Applications/Xilinx/10.1/ISE.
|
| 436 |
|
|
|
| 437 |
|
|
Synthesizing (advanced) Unit .
|
| 438 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 439 |
|
|
-----------------------------------------------------------------------
|
| 440 |
|
|
| ram_type | Distributed | |
|
| 441 |
|
|
-----------------------------------------------------------------------
|
| 442 |
|
|
| Port A |
|
| 443 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 444 |
|
|
| clkA | connected to signal | rise |
|
| 445 |
|
|
| weA | connected to signal _0> | high |
|
| 446 |
|
|
| addrA | connected to signal | |
|
| 447 |
|
|
| diA | connected to signal | |
|
| 448 |
|
|
-----------------------------------------------------------------------
|
| 449 |
|
|
| Port B |
|
| 450 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 451 |
|
|
| addrB | connected to signal | |
|
| 452 |
|
|
| doB | connected to internal node | |
|
| 453 |
|
|
-----------------------------------------------------------------------
|
| 454 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 455 |
|
|
-----------------------------------------------------------------------
|
| 456 |
|
|
| ram_type | Block | |
|
| 457 |
|
|
-----------------------------------------------------------------------
|
| 458 |
|
|
| Port A |
|
| 459 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 460 |
|
|
| mode | write-first | |
|
| 461 |
|
|
| clkA | connected to signal | rise |
|
| 462 |
|
|
| weA | connected to signal _0> | high |
|
| 463 |
|
|
| addrA | connected to signal | |
|
| 464 |
|
|
| diA | connected to signal | |
|
| 465 |
|
|
-----------------------------------------------------------------------
|
| 466 |
|
|
| optimization | speed | |
|
| 467 |
|
|
-----------------------------------------------------------------------
|
| 468 |
|
|
| Port B |
|
| 469 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 470 |
|
|
| mode | read-first | |
|
| 471 |
|
|
| clkB | connected to signal | rise |
|
| 472 |
|
|
| enB | connected to signal | high |
|
| 473 |
|
|
| addrB | connected to signal | |
|
| 474 |
|
|
| doB | connected to signal > | |
|
| 475 |
|
|
-----------------------------------------------------------------------
|
| 476 |
|
|
| optimization | speed | |
|
| 477 |
|
|
-----------------------------------------------------------------------
|
| 478 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 479 |
|
|
-----------------------------------------------------------------------
|
| 480 |
|
|
| ram_type | Distributed | |
|
| 481 |
|
|
-----------------------------------------------------------------------
|
| 482 |
|
|
| Port A |
|
| 483 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 484 |
|
|
| clkA | connected to signal | rise |
|
| 485 |
|
|
| weA | connected to signal _0> | high |
|
| 486 |
|
|
| addrA | connected to signal | |
|
| 487 |
|
|
| diA | connected to signal | |
|
| 488 |
|
|
-----------------------------------------------------------------------
|
| 489 |
|
|
| Port B |
|
| 490 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 491 |
|
|
| addrB | connected to signal | |
|
| 492 |
|
|
| doB | connected to internal node | |
|
| 493 |
|
|
-----------------------------------------------------------------------
|
| 494 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 495 |
|
|
-----------------------------------------------------------------------
|
| 496 |
|
|
| ram_type | Block | |
|
| 497 |
|
|
-----------------------------------------------------------------------
|
| 498 |
|
|
| Port A |
|
| 499 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 500 |
|
|
| mode | write-first | |
|
| 501 |
|
|
| clkA | connected to signal | rise |
|
| 502 |
|
|
| weA | connected to signal _0> | high |
|
| 503 |
|
|
| addrA | connected to signal | |
|
| 504 |
|
|
| diA | connected to signal | |
|
| 505 |
|
|
-----------------------------------------------------------------------
|
| 506 |
|
|
| optimization | speed | |
|
| 507 |
|
|
-----------------------------------------------------------------------
|
| 508 |
|
|
| Port B |
|
| 509 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 510 |
|
|
| mode | read-first | |
|
| 511 |
|
|
| clkB | connected to signal | rise |
|
| 512 |
|
|
| enB | connected to signal | high |
|
| 513 |
|
|
| addrB | connected to signal | |
|
| 514 |
|
|
| doB | connected to signal > | |
|
| 515 |
|
|
-----------------------------------------------------------------------
|
| 516 |
|
|
| optimization | speed | |
|
| 517 |
|
|
-----------------------------------------------------------------------
|
| 518 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 519 |
|
|
-----------------------------------------------------------------------
|
| 520 |
|
|
| ram_type | Distributed | |
|
| 521 |
|
|
-----------------------------------------------------------------------
|
| 522 |
|
|
| Port A |
|
| 523 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 524 |
|
|
| clkA | connected to signal | rise |
|
| 525 |
|
|
| weA | connected to signal _0> | high |
|
| 526 |
|
|
| addrA | connected to signal | |
|
| 527 |
|
|
| diA | connected to signal | |
|
| 528 |
|
|
-----------------------------------------------------------------------
|
| 529 |
|
|
| Port B |
|
| 530 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 531 |
|
|
| addrB | connected to signal | |
|
| 532 |
|
|
| doB | connected to internal node | |
|
| 533 |
|
|
-----------------------------------------------------------------------
|
| 534 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 535 |
|
|
-----------------------------------------------------------------------
|
| 536 |
|
|
| ram_type | Block | |
|
| 537 |
|
|
-----------------------------------------------------------------------
|
| 538 |
|
|
| Port A |
|
| 539 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 540 |
|
|
| mode | write-first | |
|
| 541 |
|
|
| clkA | connected to signal | rise |
|
| 542 |
|
|
| weA | connected to signal _0> | high |
|
| 543 |
|
|
| addrA | connected to signal | |
|
| 544 |
|
|
| diA | connected to signal | |
|
| 545 |
|
|
-----------------------------------------------------------------------
|
| 546 |
|
|
| optimization | speed | |
|
| 547 |
|
|
-----------------------------------------------------------------------
|
| 548 |
|
|
| Port B |
|
| 549 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 550 |
|
|
| mode | read-first | |
|
| 551 |
|
|
| clkB | connected to signal | rise |
|
| 552 |
|
|
| enB | connected to signal | high |
|
| 553 |
|
|
| addrB | connected to signal | |
|
| 554 |
|
|
| doB | connected to signal > | |
|
| 555 |
|
|
-----------------------------------------------------------------------
|
| 556 |
|
|
| optimization | speed | |
|
| 557 |
|
|
-----------------------------------------------------------------------
|
| 558 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 559 |
|
|
-----------------------------------------------------------------------
|
| 560 |
|
|
| ram_type | Distributed | |
|
| 561 |
|
|
-----------------------------------------------------------------------
|
| 562 |
|
|
| Port A |
|
| 563 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 564 |
|
|
| clkA | connected to signal | rise |
|
| 565 |
|
|
| weA | connected to signal | high |
|
| 566 |
|
|
| addrA | connected to signal | |
|
| 567 |
|
|
| diA | connected to signal | |
|
| 568 |
|
|
-----------------------------------------------------------------------
|
| 569 |
|
|
| Port B |
|
| 570 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 571 |
|
|
| addrB | connected to signal | |
|
| 572 |
|
|
| doB | connected to internal node | |
|
| 573 |
|
|
-----------------------------------------------------------------------
|
| 574 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 575 |
|
|
-----------------------------------------------------------------------
|
| 576 |
|
|
| ram_type | Block | |
|
| 577 |
|
|
-----------------------------------------------------------------------
|
| 578 |
|
|
| Port A |
|
| 579 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 580 |
|
|
| mode | write-first | |
|
| 581 |
|
|
| clkA | connected to signal | rise |
|
| 582 |
|
|
| weA | connected to signal | high |
|
| 583 |
|
|
| addrA | connected to signal | |
|
| 584 |
|
|
| diA | connected to signal | |
|
| 585 |
|
|
-----------------------------------------------------------------------
|
| 586 |
|
|
| optimization | speed | |
|
| 587 |
|
|
-----------------------------------------------------------------------
|
| 588 |
|
|
| Port B |
|
| 589 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 590 |
|
|
| mode | read-first | |
|
| 591 |
|
|
| clkB | connected to signal | rise |
|
| 592 |
|
|
| enB | connected to signal | high |
|
| 593 |
|
|
| addrB | connected to signal | |
|
| 594 |
|
|
| doB | connected to signal | |
|
| 595 |
|
|
-----------------------------------------------------------------------
|
| 596 |
|
|
| optimization | speed | |
|
| 597 |
|
|
-----------------------------------------------------------------------
|
| 598 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 599 |
|
|
-----------------------------------------------------------------------
|
| 600 |
|
|
| ram_type | Distributed | |
|
| 601 |
|
|
-----------------------------------------------------------------------
|
| 602 |
|
|
| Port A |
|
| 603 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 604 |
|
|
| clkA | connected to signal | rise |
|
| 605 |
|
|
| weA | connected to signal _0> | high |
|
| 606 |
|
|
| addrA | connected to signal | |
|
| 607 |
|
|
| diA | connected to signal | |
|
| 608 |
|
|
-----------------------------------------------------------------------
|
| 609 |
|
|
| Port B |
|
| 610 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 611 |
|
|
| addrB | connected to signal | |
|
| 612 |
|
|
| doB | connected to internal node | |
|
| 613 |
|
|
-----------------------------------------------------------------------
|
| 614 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 615 |
|
|
-----------------------------------------------------------------------
|
| 616 |
|
|
| ram_type | Block | |
|
| 617 |
|
|
-----------------------------------------------------------------------
|
| 618 |
|
|
| Port A |
|
| 619 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 620 |
|
|
| mode | write-first | |
|
| 621 |
|
|
| clkA | connected to signal | rise |
|
| 622 |
|
|
| weA | connected to signal _0> | high |
|
| 623 |
|
|
| addrA | connected to signal | |
|
| 624 |
|
|
| diA | connected to signal | |
|
| 625 |
|
|
-----------------------------------------------------------------------
|
| 626 |
|
|
| optimization | speed | |
|
| 627 |
|
|
-----------------------------------------------------------------------
|
| 628 |
|
|
| Port B |
|
| 629 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 630 |
|
|
| mode | read-first | |
|
| 631 |
|
|
| clkB | connected to signal | rise |
|
| 632 |
|
|
| enB | connected to signal | high |
|
| 633 |
|
|
| addrB | connected to signal | |
|
| 634 |
|
|
| doB | connected to signal > | |
|
| 635 |
|
|
-----------------------------------------------------------------------
|
| 636 |
|
|
| optimization | speed | |
|
| 637 |
|
|
-----------------------------------------------------------------------
|
| 638 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 639 |
|
|
-----------------------------------------------------------------------
|
| 640 |
|
|
| ram_type | Distributed | |
|
| 641 |
|
|
-----------------------------------------------------------------------
|
| 642 |
|
|
| Port A |
|
| 643 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 644 |
|
|
| clkA | connected to signal | rise |
|
| 645 |
|
|
| weA | connected to signal | high |
|
| 646 |
|
|
| addrA | connected to signal | |
|
| 647 |
|
|
| diA | connected to signal | |
|
| 648 |
|
|
-----------------------------------------------------------------------
|
| 649 |
|
|
| Port B |
|
| 650 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 651 |
|
|
| addrB | connected to internal node | |
|
| 652 |
|
|
| doB | connected to internal node | |
|
| 653 |
|
|
-----------------------------------------------------------------------
|
| 654 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 655 |
|
|
-----------------------------------------------------------------------
|
| 656 |
|
|
| ram_type | Block | |
|
| 657 |
|
|
-----------------------------------------------------------------------
|
| 658 |
|
|
| Port A |
|
| 659 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 660 |
|
|
| mode | write-first | |
|
| 661 |
|
|
| clkA | connected to signal | rise |
|
| 662 |
|
|
| weA | connected to signal | high |
|
| 663 |
|
|
| addrA | connected to signal | |
|
| 664 |
|
|
| diA | connected to signal | |
|
| 665 |
|
|
-----------------------------------------------------------------------
|
| 666 |
|
|
| optimization | speed | |
|
| 667 |
|
|
-----------------------------------------------------------------------
|
| 668 |
|
|
| Port B |
|
| 669 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 670 |
|
|
| mode | read-first | |
|
| 671 |
|
|
| clkB | connected to signal | rise |
|
| 672 |
|
|
| enB | connected to signal | high |
|
| 673 |
|
|
| addrB | connected to internal node | |
|
| 674 |
|
|
| doB | connected to signal | |
|
| 675 |
|
|
-----------------------------------------------------------------------
|
| 676 |
|
|
| optimization | speed | |
|
| 677 |
|
|
-----------------------------------------------------------------------
|
| 678 |
|
|
INFO:Xst - HDL ADVISOR - Asynchronous or synchronous initialization of the register prevents it from being combined with the RAM for implementation as read-only block RAM.
|
| 679 |
|
|
-----------------------------------------------------------------------
|
| 680 |
|
|
| ram_type | Distributed | |
|
| 681 |
|
|
-----------------------------------------------------------------------
|
| 682 |
|
|
| Port A |
|
| 683 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 684 |
|
|
| clkA | connected to signal | rise |
|
| 685 |
|
|
| weA | connected to signal | high |
|
| 686 |
|
|
| addrA | connected to signal | |
|
| 687 |
|
|
| diA | connected to signal | |
|
| 688 |
|
|
-----------------------------------------------------------------------
|
| 689 |
|
|
| Port B |
|
| 690 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 691 |
|
|
| addrB | connected to signal | |
|
| 692 |
|
|
| doB | connected to internal node | |
|
| 693 |
|
|
-----------------------------------------------------------------------
|
| 694 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 695 |
|
|
-----------------------------------------------------------------------
|
| 696 |
|
|
| ram_type | Block | |
|
| 697 |
|
|
-----------------------------------------------------------------------
|
| 698 |
|
|
| Port A |
|
| 699 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 700 |
|
|
| mode | write-first | |
|
| 701 |
|
|
| clkA | connected to signal | rise |
|
| 702 |
|
|
| weA | connected to signal | high |
|
| 703 |
|
|
| addrA | connected to signal | |
|
| 704 |
|
|
| diA | connected to signal | |
|
| 705 |
|
|
-----------------------------------------------------------------------
|
| 706 |
|
|
| optimization | speed | |
|
| 707 |
|
|
-----------------------------------------------------------------------
|
| 708 |
|
|
| Port B |
|
| 709 |
|
|
| aspect ratio | 32-word x 32-bit | |
|
| 710 |
|
|
| mode | read-first | |
|
| 711 |
|
|
| clkB | connected to signal | rise |
|
| 712 |
|
|
| enB | connected to signal | high |
|
| 713 |
|
|
| addrB | connected to signal | |
|
| 714 |
|
|
| doB | connected to signal | |
|
| 715 |
|
|
-----------------------------------------------------------------------
|
| 716 |
|
|
| optimization | speed | |
|
| 717 |
|
|
-----------------------------------------------------------------------
|
| 718 |
|
|
INFO:Xst - The RAM appears to be read-only. If that was not your intent please check the write enable description.
|
| 719 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 720 |
|
|
-----------------------------------------------------------------------
|
| 721 |
|
|
| ram_type | Block | |
|
| 722 |
|
|
-----------------------------------------------------------------------
|
| 723 |
|
|
| Port A |
|
| 724 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 725 |
|
|
| mode | write-first | |
|
| 726 |
|
|
| clkA | connected to signal | rise |
|
| 727 |
|
|
| weA | connected to signal | high |
|
| 728 |
|
|
| addrA | connected to signal | |
|
| 729 |
|
|
| diA | connected to signal | |
|
| 730 |
|
|
-----------------------------------------------------------------------
|
| 731 |
|
|
| optimization | speed | |
|
| 732 |
|
|
-----------------------------------------------------------------------
|
| 733 |
|
|
| Port B |
|
| 734 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 735 |
|
|
| mode | read-first | |
|
| 736 |
|
|
| clkB | connected to signal | rise |
|
| 737 |
|
|
| enB | connected to signal | high |
|
| 738 |
|
|
| addrB | connected to signal | |
|
| 739 |
|
|
| doB | connected to signal > | |
|
| 740 |
|
|
-----------------------------------------------------------------------
|
| 741 |
|
|
| optimization | speed | |
|
| 742 |
|
|
-----------------------------------------------------------------------
|
| 743 |
|
|
INFO:Xst - The RAM appears to be read-only. If that was not your intent please check the write enable description.
|
| 744 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 745 |
|
|
-----------------------------------------------------------------------
|
| 746 |
|
|
| ram_type | Block | |
|
| 747 |
|
|
-----------------------------------------------------------------------
|
| 748 |
|
|
| Port A |
|
| 749 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 750 |
|
|
| mode | write-first | |
|
| 751 |
|
|
| clkA | connected to signal | rise |
|
| 752 |
|
|
| weA | connected to signal | high |
|
| 753 |
|
|
| addrA | connected to signal | |
|
| 754 |
|
|
| diA | connected to signal | |
|
| 755 |
|
|
-----------------------------------------------------------------------
|
| 756 |
|
|
| optimization | speed | |
|
| 757 |
|
|
-----------------------------------------------------------------------
|
| 758 |
|
|
| Port B |
|
| 759 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 760 |
|
|
| mode | read-first | |
|
| 761 |
|
|
| clkB | connected to signal | rise |
|
| 762 |
|
|
| enB | connected to signal | high |
|
| 763 |
|
|
| addrB | connected to signal | |
|
| 764 |
|
|
| doB | connected to signal > | |
|
| 765 |
|
|
-----------------------------------------------------------------------
|
| 766 |
|
|
| optimization | speed | |
|
| 767 |
|
|
-----------------------------------------------------------------------
|
| 768 |
|
|
INFO:Xst - The RAM appears to be read-only. If that was not your intent please check the write enable description.
|
| 769 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 770 |
|
|
-----------------------------------------------------------------------
|
| 771 |
|
|
| ram_type | Block | |
|
| 772 |
|
|
-----------------------------------------------------------------------
|
| 773 |
|
|
| Port A |
|
| 774 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 775 |
|
|
| mode | write-first | |
|
| 776 |
|
|
| clkA | connected to signal | rise |
|
| 777 |
|
|
| weA | connected to signal | high |
|
| 778 |
|
|
| addrA | connected to signal | |
|
| 779 |
|
|
| diA | connected to signal | |
|
| 780 |
|
|
-----------------------------------------------------------------------
|
| 781 |
|
|
| optimization | speed | |
|
| 782 |
|
|
-----------------------------------------------------------------------
|
| 783 |
|
|
| Port B |
|
| 784 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 785 |
|
|
| mode | read-first | |
|
| 786 |
|
|
| clkB | connected to signal | rise |
|
| 787 |
|
|
| enB | connected to signal | high |
|
| 788 |
|
|
| addrB | connected to signal | |
|
| 789 |
|
|
| doB | connected to signal > | |
|
| 790 |
|
|
-----------------------------------------------------------------------
|
| 791 |
|
|
| optimization | speed | |
|
| 792 |
|
|
-----------------------------------------------------------------------
|
| 793 |
|
|
INFO:Xst - The RAM appears to be read-only. If that was not your intent please check the write enable description.
|
| 794 |
|
|
INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s):
|
| 795 |
|
|
-----------------------------------------------------------------------
|
| 796 |
|
|
| ram_type | Block | |
|
| 797 |
|
|
-----------------------------------------------------------------------
|
| 798 |
|
|
| Port A |
|
| 799 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 800 |
|
|
| mode | write-first | |
|
| 801 |
|
|
| clkA | connected to signal | rise |
|
| 802 |
|
|
| weA | connected to signal | high |
|
| 803 |
|
|
| addrA | connected to signal | |
|
| 804 |
|
|
| diA | connected to signal | |
|
| 805 |
|
|
-----------------------------------------------------------------------
|
| 806 |
|
|
| optimization | speed | |
|
| 807 |
|
|
-----------------------------------------------------------------------
|
| 808 |
|
|
| Port B |
|
| 809 |
|
|
| aspect ratio | 2048-word x 8-bit | |
|
| 810 |
|
|
| mode | read-first | |
|
| 811 |
|
|
| clkB | connected to signal | rise |
|
| 812 |
|
|
| enB | connected to signal | high |
|
| 813 |
|
|
| addrB | connected to signal | |
|
| 814 |
|
|
| doB | connected to signal > | |
|
| 815 |
|
|
-----------------------------------------------------------------------
|
| 816 |
|
|
| optimization | speed | |
|
| 817 |
|
|
-----------------------------------------------------------------------
|
| 818 |
|
|
Unit synthesized (advanced).
|
| 819 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 820 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 821 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 822 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 823 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 824 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 825 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 826 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 827 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 828 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 829 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 830 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 831 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 832 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 833 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 834 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 835 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 836 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 837 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 838 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 839 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 840 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 841 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 842 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 843 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 844 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 845 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 846 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 847 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 848 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 849 |
|
|
WARNING:Xst:2677 - Node of sequential type is unconnected in block .
|
| 850 |
|
|
|
| 851 |
|
|
=========================================================================
|
| 852 |
|
|
Advanced HDL Synthesis Report
|
| 853 |
|
|
|
| 854 |
|
|
Macro Statistics
|
| 855 |
|
|
# RAMs : 11
|
| 856 |
|
|
2048x8-bit dual-port block RAM : 8
|
| 857 |
|
|
32x32-bit dual-port block RAM : 3
|
| 858 |
|
|
# Adders/Subtractors : 4
|
| 859 |
|
|
16-bit adder : 1
|
| 860 |
|
|
34-bit adder : 1
|
| 861 |
|
|
4-bit adder : 1
|
| 862 |
|
|
4-bit subtractor : 1
|
| 863 |
|
|
# Counters : 1
|
| 864 |
|
|
16-bit down counter : 1
|
| 865 |
|
|
# Registers : 377
|
| 866 |
|
|
Flip-Flops : 377
|
| 867 |
|
|
# Comparators : 14
|
| 868 |
|
|
28-bit comparator greatequal : 1
|
| 869 |
|
|
32-bit comparator less : 1
|
| 870 |
|
|
5-bit comparator equal : 12
|
| 871 |
|
|
# Multiplexers : 6
|
| 872 |
|
|
32-bit 4-to-1 multiplexer : 6
|
| 873 |
|
|
# Xors : 2
|
| 874 |
|
|
1-bit xor2 : 1
|
| 875 |
|
|
32-bit xor2 : 1
|
| 876 |
|
|
|
| 877 |
|
|
=========================================================================
|
| 878 |
|
|
|
| 879 |
|
|
=========================================================================
|
| 880 |
|
|
* Low Level Synthesis *
|
| 881 |
|
|
=========================================================================
|
| 882 |
|
|
|
| 883 |
|
|
Optimizing unit ...
|
| 884 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
| 885 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
| 886 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
| 887 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
| 888 |
|
|
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
|
| 889 |
|
|
|
| 890 |
|
|
Mapping all equations...
|
| 891 |
|
|
Building and optimizing final netlist ...
|
| 892 |
|
|
Found area constraint ratio of 100 (+ 5) on block SysTop, actual ratio is 15.
|
| 893 |
|
|
FlipFlop core_mm_alu_result_1 has been replicated 1 time(s)
|
| 894 |
|
|
FlipFlop core_mm_mem_read has been replicated 1 time(s)
|
| 895 |
|
|
FlipFlop core_mm_transfer_size_1 has been replicated 1 time(s)
|
| 896 |
|
|
FlipFlop core_mm_transfer_size_2 has been replicated 1 time(s)
|
| 897 |
|
|
|
| 898 |
|
|
Final Macro Processing ...
|
| 899 |
|
|
|
| 900 |
|
|
=========================================================================
|
| 901 |
|
|
Final Register Report
|
| 902 |
|
|
|
| 903 |
|
|
Macro Statistics
|
| 904 |
|
|
# Registers : 392
|
| 905 |
|
|
Flip-Flops : 392
|
| 906 |
|
|
|
| 907 |
|
|
=========================================================================
|
| 908 |
|
|
|
| 909 |
|
|
=========================================================================
|
| 910 |
|
|
* Partition Report *
|
| 911 |
|
|
=========================================================================
|
| 912 |
|
|
|
| 913 |
|
|
Partition Implementation Status
|
| 914 |
|
|
-------------------------------
|
| 915 |
|
|
|
| 916 |
|
|
No Partitions were found in this design.
|
| 917 |
|
|
|
| 918 |
|
|
-------------------------------
|
| 919 |
|
|
|
| 920 |
|
|
=========================================================================
|
| 921 |
|
|
* Final Report *
|
| 922 |
|
|
=========================================================================
|
| 923 |
|
|
Final Results
|
| 924 |
|
|
RTL Top Level Output File Name : SysTop.ngr
|
| 925 |
|
|
Top Level Output File Name : SysTop
|
| 926 |
|
|
Output Format : NGC
|
| 927 |
|
|
Optimization Goal : Speed
|
| 928 |
|
|
Keep Hierarchy : NO
|
| 929 |
|
|
|
| 930 |
|
|
Design Statistics
|
| 931 |
|
|
# IOs : 14
|
| 932 |
|
|
|
| 933 |
|
|
Cell Usage :
|
| 934 |
|
|
# BELS : 1495
|
| 935 |
|
|
# GND : 1
|
| 936 |
|
|
# INV : 18
|
| 937 |
|
|
# LUT1 : 15
|
| 938 |
|
|
# LUT2 : 114
|
| 939 |
|
|
# LUT2_D : 4
|
| 940 |
|
|
# LUT2_L : 1
|
| 941 |
|
|
# LUT3 : 249
|
| 942 |
|
|
# LUT3_D : 14
|
| 943 |
|
|
# LUT3_L : 22
|
| 944 |
|
|
# LUT4 : 679
|
| 945 |
|
|
# LUT4_D : 56
|
| 946 |
|
|
# LUT4_L : 112
|
| 947 |
|
|
# MUXCY : 89
|
| 948 |
|
|
# MUXF5 : 58
|
| 949 |
|
|
# VCC : 1
|
| 950 |
|
|
# XORCY : 62
|
| 951 |
|
|
# FlipFlops/Latches : 392
|
| 952 |
|
|
# FDE : 13
|
| 953 |
|
|
# FDR : 15
|
| 954 |
|
|
# FDRE : 358
|
| 955 |
|
|
# FDS : 3
|
| 956 |
|
|
# FDSE : 3
|
| 957 |
|
|
# RAMS : 11
|
| 958 |
|
|
# RAMB16_S36_S36 : 3
|
| 959 |
|
|
# RAMB16_S9_S9 : 8
|
| 960 |
|
|
# Clock Buffers : 1
|
| 961 |
|
|
# BUFGP : 1
|
| 962 |
|
|
# IO Buffers : 11
|
| 963 |
|
|
# IBUF : 1
|
| 964 |
|
|
# OBUF : 10
|
| 965 |
|
|
=========================================================================
|
| 966 |
|
|
|
| 967 |
|
|
Device utilization summary:
|
| 968 |
|
|
---------------------------
|
| 969 |
|
|
|
| 970 |
|
|
Selected Device : 3s500efg320-4
|
| 971 |
|
|
|
| 972 |
|
|
Number of Slices: 678 out of 4656 14%
|
| 973 |
|
|
Number of Slice Flip Flops: 391 out of 9312 4%
|
| 974 |
|
|
Number of 4 input LUTs: 1284 out of 9312 13%
|
| 975 |
|
|
Number of IOs: 14
|
| 976 |
|
|
Number of bonded IOBs: 12 out of 232 5%
|
| 977 |
|
|
IOB Flip Flops: 1
|
| 978 |
|
|
Number of BRAMs: 11 out of 20 55%
|
| 979 |
|
|
Number of GCLKs: 1 out of 24 4%
|
| 980 |
|
|
|
| 981 |
|
|
---------------------------
|
| 982 |
|
|
Partition Resource Summary:
|
| 983 |
|
|
---------------------------
|
| 984 |
|
|
|
| 985 |
|
|
No Partitions were found in this design.
|
| 986 |
|
|
|
| 987 |
|
|
---------------------------
|
| 988 |
|
|
|
| 989 |
|
|
|
| 990 |
|
|
=========================================================================
|
| 991 |
|
|
TIMING REPORT
|
| 992 |
|
|
|
| 993 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
| 994 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
| 995 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
| 996 |
|
|
|
| 997 |
|
|
Clock Information:
|
| 998 |
|
|
------------------
|
| 999 |
|
|
-----------------------------------+------------------------+-------+
|
| 1000 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 1001 |
|
|
-----------------------------------+------------------------+-------+
|
| 1002 |
|
|
clock | BUFGP | 403 |
|
| 1003 |
|
|
-----------------------------------+------------------------+-------+
|
| 1004 |
|
|
|
| 1005 |
|
|
Asynchronous Control Signals Information:
|
| 1006 |
|
|
----------------------------------------
|
| 1007 |
|
|
No asynchronous control signals found in this design
|
| 1008 |
|
|
|
| 1009 |
|
|
Timing Summary:
|
| 1010 |
|
|
---------------
|
| 1011 |
|
|
Speed Grade: -4
|
| 1012 |
|
|
|
| 1013 |
|
|
Minimum period: 13.802ns (Maximum Frequency: 72.453MHz)
|
| 1014 |
|
|
Minimum input arrival time before clock: 5.419ns
|
| 1015 |
|
|
Maximum output required time after clock: 4.283ns
|
| 1016 |
|
|
Maximum combinational path delay: No path found
|
| 1017 |
|
|
|
| 1018 |
|
|
Timing Detail:
|
| 1019 |
|
|
--------------
|
| 1020 |
|
|
All values displayed in nanoseconds (ns)
|
| 1021 |
|
|
|
| 1022 |
|
|
=========================================================================
|
| 1023 |
|
|
Timing constraint: Default period analysis for Clock 'clock'
|
| 1024 |
|
|
Clock period: 13.802ns (frequency: 72.453MHz)
|
| 1025 |
|
|
Total number of paths / destination ports: 247273 / 1133
|
| 1026 |
|
|
-------------------------------------------------------------------------
|
| 1027 |
|
|
Delay: 13.802ns (Levels of Logic = 39)
|
| 1028 |
|
|
Source: core_exeu_ex_r_reg_write (FF)
|
| 1029 |
|
|
Destination: core_exeu_ex_r_alu_result_31 (FF)
|
| 1030 |
|
|
Source Clock: clock rising
|
| 1031 |
|
|
Destination Clock: clock rising
|
| 1032 |
|
|
|
| 1033 |
|
|
Data Path: core_exeu_ex_r_reg_write to core_exeu_ex_r_alu_result_31
|
| 1034 |
|
|
Gate Net
|
| 1035 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 1036 |
|
|
---------------------------------------- ------------
|
| 1037 |
|
|
FDRE:C->Q 6 0.591 0.844 core_exeu_ex_r_reg_write (core_exeu_ex_r_reg_write)
|
| 1038 |
|
|
LUT3:I0->O 1 0.704 0.499 _old_SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_result_3240_1 (_old_SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_result_32401)
|
| 1039 |
|
|
LUT3:I1->O 14 0.704 1.004 _old_SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_result_3282 (SYSTOP_CORE_EXEU_COMB_MYHDL36_forward_condition_1_MYHDL36_forward_condition)
|
| 1040 |
|
|
LUT4:I3->O 19 0.704 1.085 Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_a_421101_1 (Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_a_421101)
|
| 1041 |
|
|
MUXF5:S->O 1 0.739 0.424 Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_a_421241_SW0 (N309)
|
| 1042 |
|
|
LUT4:I3->O 4 0.704 0.622 _old_SYSTOP_CORE_EXEU_COMB_alu_src_a_44<0> (_old_SYSTOP_CORE_EXEU_COMB_alu_src_a_44<0>)
|
| 1043 |
|
|
LUT4:I2->O 1 0.704 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<1> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<1>)
|
| 1044 |
|
|
MUXCY:S->O 1 0.464 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<1> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<1>)
|
| 1045 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<2> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<2>)
|
| 1046 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>)
|
| 1047 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>)
|
| 1048 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>)
|
| 1049 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>)
|
| 1050 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>)
|
| 1051 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>)
|
| 1052 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>)
|
| 1053 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>)
|
| 1054 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>)
|
| 1055 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>)
|
| 1056 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>)
|
| 1057 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>)
|
| 1058 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>)
|
| 1059 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>)
|
| 1060 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>)
|
| 1061 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>)
|
| 1062 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>)
|
| 1063 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>)
|
| 1064 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>)
|
| 1065 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>)
|
| 1066 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>)
|
| 1067 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24>)
|
| 1068 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>)
|
| 1069 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26>)
|
| 1070 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>)
|
| 1071 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28>)
|
| 1072 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>)
|
| 1073 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30>)
|
| 1074 |
|
|
MUXCY:CI->O 1 0.059 0.000 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31> (Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31>)
|
| 1075 |
|
|
XORCY:CI->O 1 0.804 0.424 Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor<32> (SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<31>)
|
| 1076 |
|
|
LUT4:I3->O 1 0.704 0.000 _old_SYSTOP_CORE_EXEU_COMB_r_alu_result_59<31>77 (core_exeu_ex_comb_r_alu_result<31>)
|
| 1077 |
|
|
FDRE:D 0.308 core_exeu_ex_r_alu_result_31
|
| 1078 |
|
|
----------------------------------------
|
| 1079 |
|
|
Total 13.802ns (8.900ns logic, 4.902ns route)
|
| 1080 |
|
|
(64.5% logic, 35.5% route)
|
| 1081 |
|
|
|
| 1082 |
|
|
=========================================================================
|
| 1083 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
|
| 1084 |
|
|
Total number of paths / destination ports: 600 / 496
|
| 1085 |
|
|
-------------------------------------------------------------------------
|
| 1086 |
|
|
Offset: 5.419ns (Levels of Logic = 2)
|
| 1087 |
|
|
Source: reset (PAD)
|
| 1088 |
|
|
Destination: uart_enable16_counter_0 (FF)
|
| 1089 |
|
|
Destination Clock: clock rising
|
| 1090 |
|
|
|
| 1091 |
|
|
Data Path: reset to uart_enable16_counter_0
|
| 1092 |
|
|
Gate Net
|
| 1093 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 1094 |
|
|
---------------------------------------- ------------
|
| 1095 |
|
|
IBUF:I->O 396 1.218 1.552 reset_IBUF (reset_IBUF)
|
| 1096 |
|
|
LUT2:I0->O 16 0.704 1.034 uart_enable16_counter_or00001 (uart_enable16_counter_or0000)
|
| 1097 |
|
|
FDR:R 0.911 uart_enable16_counter_0
|
| 1098 |
|
|
----------------------------------------
|
| 1099 |
|
|
Total 5.419ns (2.833ns logic, 2.586ns route)
|
| 1100 |
|
|
(52.3% logic, 47.7% route)
|
| 1101 |
|
|
|
| 1102 |
|
|
=========================================================================
|
| 1103 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
|
| 1104 |
|
|
Total number of paths / destination ports: 10 / 10
|
| 1105 |
|
|
-------------------------------------------------------------------------
|
| 1106 |
|
|
Offset: 4.283ns (Levels of Logic = 1)
|
| 1107 |
|
|
Source: txd_line2 (FF)
|
| 1108 |
|
|
Destination: txd_line2 (PAD)
|
| 1109 |
|
|
Source Clock: clock rising
|
| 1110 |
|
|
|
| 1111 |
|
|
Data Path: txd_line2 to txd_line2
|
| 1112 |
|
|
Gate Net
|
| 1113 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 1114 |
|
|
---------------------------------------- ------------
|
| 1115 |
|
|
FDR:C->Q 1 0.591 0.420 txd_line2 (txd_line2_OBUF)
|
| 1116 |
|
|
OBUF:I->O 3.272 txd_line2_OBUF (txd_line2)
|
| 1117 |
|
|
----------------------------------------
|
| 1118 |
|
|
Total 4.283ns (3.863ns logic, 0.420ns route)
|
| 1119 |
|
|
(90.2% logic, 9.8% route)
|
| 1120 |
|
|
|
| 1121 |
|
|
=========================================================================
|
| 1122 |
|
|
|
| 1123 |
|
|
|
| 1124 |
|
|
Total REAL time to Xst completion: 24.00 secs
|
| 1125 |
|
|
Total CPU time to Xst completion: 24.43 secs
|
| 1126 |
|
|
|
| 1127 |
|
|
-->
|
| 1128 |
|
|
|
| 1129 |
|
|
|
| 1130 |
|
|
Total memory usage is 421724 kilobytes
|
| 1131 |
|
|
|
| 1132 |
|
|
Number of errors : 0 ( 0 filtered)
|
| 1133 |
|
|
Number of warnings : 102 ( 0 filtered)
|
| 1134 |
|
|
Number of infos : 58 ( 0 filtered)
|
| 1135 |
|
|
|
