URL https://opencores.org/ocsvn/neo430/neo430/trunk

Subversion Repositories neo430

[/] [neo430/] [trunk/] [neo430/] [sim/] [ISIM/] [neo430_tb.wcfg] - Blame information for rev 198

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      Global
      label
   
   
      clk_i
      clk_i
   
   
      clk_gen[7:0]
      clk_gen[7:0]
   
   
      rst_i
      rst_i
   
   
      rst_gen[3:0]
      rst_gen[3:0]
      BINARYRADIX
   
   
      ext_rst
      ext_rst
   
   
      sys_rst
      sys_rst
   
   
      CPU - Control
      label
   
   
      irq_i[3:0]
      irq_i[3:0]
   
   
      irq_buf[3:0]
      irq_buf[3:0]
   
   
      irq_ack
      irq_ack
   
   
      irq_start
      irq_start
   
   
      am[3:0]
      am[3:0]
      BINARYRADIX
   
   
      ir[15:0]
      ir[15:0]
   
   
      state
      state
   
   
      ctrl_o[28:0]
      ctrl_o[28:0]
   
   
      CPU - RF
      label
   
   
      sreg[15:0]
      sreg[15:0]
   
   
      reg_file[15:0][15:0]
      reg_file[15:0][15:0]
   
   
      CPU - ALU
      label
   
   
      op_a_ff[15:0]
      op_a_ff[15:0]
      HEXRADIX
   
   
      op_b_ff[15:0]
      op_b_ff[15:0]
      HEXRADIX
   
   
      alu_res[15:0]
      alu_res[15:0]
      HEXRADIX
   
   
      CPU - Address Generator
      label
   
   
      mem_addr_reg[15:0]
      mem_addr_reg[15:0]
   
   
      mem_addr_o[15:0]
      mem_addr_o[15:0]
      HEXRADIX
   
   
      irq_sel_i[1:0]
      irq_sel_i[1:0]
   
   
      imm_i[15:0]
      imm_i[15:0]
   
   
      CPU - BUS Interface
      label
   
   
      dio_swap
      dio_swap
   
   
      io_acc
      io_acc
   
   
      mem_rd_o
      mem_rd_o
   
   
      mem_wr_o[1:0]
      mem_wr_o[1:0]
   
   
      mem_addr_o[15:0]
      mem_addr_o[15:0]
      HEXRADIX
   
   
      mem_data_o[15:0]
      mem_data_o[15:0]
   
   
      mem_data_i[15:0]
      mem_data_i[15:0]
   
   
      Main Memory
      label
   
   
      imem_up_en
      imem_up_en
   
   
      IO: UART
      label
   
   
      uart_txd_o
      uart_txd_o
   
   
      uart_rxd_i
      uart_rxd_i
   
   
      uart_irq_o
      uart_irq_o
   
   
      ctrl[15:0]
      ctrl[15:0]
   
   
      uart_tx_busy
      uart_tx_busy
   
   
      uart_tx_done
      uart_tx_done
   
   
      uart_rx_busy
      uart_rx_busy
   
   
      uart_rx_busy_ff
      uart_rx_busy_ff
   
   
      uart_rx_avail[1:0]
      uart_rx_avail[1:0]
   
   
      IO: SPI
      label
   
   
      data_i[15:0]
      data_i[15:0]
   
   
      data_o[15:0]
      data_o[15:0]
   
   
      spi_sclk_o
      spi_sclk_o
   
   
      spi_mosi_o
      spi_mosi_o
   
   
      spi_miso_i
      spi_miso_i
   
   
      spi_cs_o[5:0]
      spi_cs_o[5:0]
   
   
      spi_irq_o
      spi_irq_o
   
   
      wr_en
      wr_en
   
   
      rd_en
      rd_en
   
   
      ctrl[15:0]
      ctrl[15:0]
   
   
      spi_busy
      spi_busy
   
   
      spi_state0
      spi_state0
   
   
      spi_state1
      spi_state1
   
   
      spi_rtx_sreg[15:0]
      spi_rtx_sreg[15:0]
   
   
      spi_bitcnt[4:0]
      spi_bitcnt[4:0]
   
   
      IO: Timer
      label
   
   
      ctrl[10:0]
      ctrl[10:0]
   
   
      thres[15:0]
      thres[15:0]
      HEXRADIX
   
   
      prsc_tick
      prsc_tick
   
   
      cnt[15:0]
      cnt[15:0]
   
   
      irq_o
      irq_o
   
   
      nco_prsc_tick
      nco_prsc_tick
   
   
      nco_tuning_word[15:0]
      nco_tuning_word[15:0]
   
   
      nco_phase_accu[16:0]
      nco_phase_accu[16:0]
   
   
      timer_fg_o
      timer_fg_o
   
   
      IO: GPIO
      label
   
   
      gpio_o[15:0]
      gpio_o[15:0]
   
   
      gpio_i[15:0]
      gpio_i[15:0]
   
   
      irq_o
      irq_o
   
   
      IO: Watchdog
      label
   
   
      enable
      enable
   
   
      cnt[16:0]
      cnt[16:0]
   
   
      IO: Wishbone Bus Interface
      label
   
   
      enable
      enable
   
   
      pending
      pending
   
   
      wb_adr_o[31:0]
      wb_adr_o[31:0]
   
   
      wb_dat_i[31:0]
      wb_dat_i[31:0]
   
   
      wb_dat_o[31:0]
      wb_dat_o[31:0]
   
   
      wb_we_o
      wb_we_o
   
   
      wb_sel_o[3:0]
      wb_sel_o[3:0]
      BINARYRADIX
   
   
      wb_stb_o
      wb_stb_o
   
   
      wb_cyc_o
      wb_cyc_o
   
   
      wb_ack_i
      wb_ack_i
   
   
      Sysconfig
      label
   
   
      info_addr[2:0]
      info_addr[2:0]
   
   
      rden
      rden
   
   
      acc_en
      acc_en
   
   
      sysinfo_mem[0:7][15:0]
      sysinfo_mem[0:7][15:0]
   
   
      IO: MulDiv
      label
   
   
      rden_i
      rden_i
   
   
      wr_en
      wr_en
   
   
      opa[15:0]
      opa[15:0]
      SIGNEDDECRADIX
   
   
      opb[15:0]
      opb[15:0]
      SIGNEDDECRADIX
   
   
      resx[15:0]
      resx[15:0]
   
   
      resy[15:0]
      resy[15:0]
   
   
      func_rst
      func_rst
   
   
      ctrl_state
      ctrl_state
   
   
      operation
      operation
   
   
      start
      start
   
   
      run
      run
   
   
      remainder[15:0]
      remainder[15:0]
      SIGNEDDECRADIX
   
   
      quotient[15:0]
      quotient[15:0]
      SIGNEDDECRADIX
   
   
      product[31:0]
      product[31:0]
      SIGNEDDECRADIX
   
   
      IO: CRC
      label
   
   
      wren
      wren
   
   
      idata[7:0]
      idata[7:0]
   
   
      start
      start
   
   
      mode
      mode
   
   
      cnt[2:0]
      cnt[2:0]
   
   
      run
      run
   
   
      crc_bit
      crc_bit
   
   
      poly[31:0]
      poly[31:0]
   
   
      crc_sr[31:0]
      crc_sr[31:0]
   
   
      IO: PWM
      label
   
   
      pwm_o[3:0]
      pwm_o[3:0]
   
   
      pwm_ch[0:3][7:0]
      pwm_ch[0:3][7:0]
   
   
      IO: TWI
      label
   
   
      wr_en
      wr_en
   
   
      rd_en
      rd_en
   
   
      twi_clk
      twi_clk
   
   
      arbiter[2:0]
      arbiter[2:0]
      BINARYRADIX
   
   
      ctrl[8:0]
      ctrl[8:0]
   
   
      twi_bitcnt[3:0]
      twi_bitcnt[3:0]
   
   
      twi_rtx_sreg[8:0]
      twi_rtx_sreg[8:0]
   
   
      twi_sda_io
      twi_sda_io
   
   
      twi_scl_io
      twi_scl_io
   
   
      IO: EXIRQ
      label
   
   
      ext_irq_i[7:0]
      ext_irq_i[7:0]
   
   
      ext_ack_o[7:0]
      ext_ack_o[7:0]
   
   
      acc_en
      acc_en
   
   
      wren
      wren
   
   
      rden
      rden
   
   
      enable
      enable
   
   
      state
      state
   
   
      irq_raw[7:0]
      irq_raw[7:0]
   
   
      irq_enable[7:0]
      irq_enable[7:0]
   
   
      ack_mask[7:0]
      ack_mask[7:0]
   
   
      irq_valid[7:0]
      irq_valid[7:0]
   
   
      irq_buf[7:0]
      irq_buf[7:0]
   
   
      irq_src_reg[2:0]
      irq_src_reg[2:0]
   
   
      sw_trig
      sw_trig
   
   
      sw_irq[7:0]
      sw_irq[7:0]
   
   
      cpu_irq_o
      cpu_irq_o
   


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Subversion Repositories neo430

[/] [neo430/] [trunk/] [neo430/] [sim/] [ISIM/] [neo430_tb.wcfg] - Blame information for rev 198

Line No.	Rev	Author	Line
1	198	zero_gravi
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25			`Global`
26			`label`
27
28
29			`clk_i`
30			`clk_i`
31
32
33			`clk_gen[7:0]`
34			`clk_gen[7:0]`
35
36
37			`rst_i`
38			`rst_i`
39
40
41			`rst_gen[3:0]`
42			`rst_gen[3:0]`
43			`BINARYRADIX`
44
45
46			`ext_rst`
47			`ext_rst`
48
49
50			`sys_rst`
51			`sys_rst`
52
53
54			`CPU - Control`
55			`label`
56
57
58			`irq_i[3:0]`
59			`irq_i[3:0]`
60
61
62			`irq_buf[3:0]`
63			`irq_buf[3:0]`
64
65
66			`irq_ack`
67			`irq_ack`
68
69
70			`irq_start`
71			`irq_start`
72
73
74			`am[3:0]`
75			`am[3:0]`
76			`BINARYRADIX`
77
78
79			`ir[15:0]`
80			`ir[15:0]`
81
82
83			`state`
84			`state`
85
86
87			`ctrl_o[28:0]`
88			`ctrl_o[28:0]`
89
90
91			`CPU - RF`
92			`label`
93
94
95			`sreg[15:0]`
96			`sreg[15:0]`
97
98
99			`reg_file[15:0][15:0]`
100			`reg_file[15:0][15:0]`
101
102
103			`CPU - ALU`
104			`label`
105
106
107			`op_a_ff[15:0]`
108			`op_a_ff[15:0]`
109			`HEXRADIX`
110
111
112			`op_b_ff[15:0]`
113			`op_b_ff[15:0]`
114			`HEXRADIX`
115
116
117			`alu_res[15:0]`
118			`alu_res[15:0]`
119			`HEXRADIX`
120
121
122			`CPU - Address Generator`
123			`label`
124
125
126			`mem_addr_reg[15:0]`
127			`mem_addr_reg[15:0]`
128
129
130			`mem_addr_o[15:0]`
131			`mem_addr_o[15:0]`
132			`HEXRADIX`
133
134
135			`irq_sel_i[1:0]`
136			`irq_sel_i[1:0]`
137
138
139			`imm_i[15:0]`
140			`imm_i[15:0]`
141
142
143			`CPU - BUS Interface`
144			`label`
145
146
147			`dio_swap`
148			`dio_swap`
149
150
151			`io_acc`
152			`io_acc`
153
154
155			`mem_rd_o`
156			`mem_rd_o`
157
158
159			`mem_wr_o[1:0]`
160			`mem_wr_o[1:0]`
161
162
163			`mem_addr_o[15:0]`
164			`mem_addr_o[15:0]`
165			`HEXRADIX`
166
167
168			`mem_data_o[15:0]`
169			`mem_data_o[15:0]`
170
171
172			`mem_data_i[15:0]`
173			`mem_data_i[15:0]`
174
175
176			`Main Memory`
177			`label`
178
179
180			`imem_up_en`
181			`imem_up_en`
182
183
184			`IO: UART`
185			`label`
186
187
188			`uart_txd_o`
189			`uart_txd_o`
190
191
192			`uart_rxd_i`
193			`uart_rxd_i`
194
195
196			`uart_irq_o`
197			`uart_irq_o`
198
199
200			`ctrl[15:0]`
201			`ctrl[15:0]`
202
203
204			`uart_tx_busy`
205			`uart_tx_busy`
206
207
208			`uart_tx_done`
209			`uart_tx_done`
210
211
212			`uart_rx_busy`
213			`uart_rx_busy`
214
215
216			`uart_rx_busy_ff`
217			`uart_rx_busy_ff`
218
219
220			`uart_rx_avail[1:0]`
221			`uart_rx_avail[1:0]`
222
223
224			`IO: SPI`
225			`label`
226
227
228			`data_i[15:0]`
229			`data_i[15:0]`
230
231
232			`data_o[15:0]`
233			`data_o[15:0]`
234
235
236			`spi_sclk_o`
237			`spi_sclk_o`
238
239
240			`spi_mosi_o`
241			`spi_mosi_o`
242
243
244			`spi_miso_i`
245			`spi_miso_i`
246
247
248			`spi_cs_o[5:0]`
249			`spi_cs_o[5:0]`
250
251
252			`spi_irq_o`
253			`spi_irq_o`
254
255
256			`wr_en`
257			`wr_en`
258
259
260			`rd_en`
261			`rd_en`
262
263
264			`ctrl[15:0]`
265			`ctrl[15:0]`
266
267
268			`spi_busy`
269			`spi_busy`
270
271
272			`spi_state0`
273			`spi_state0`
274
275
276			`spi_state1`
277			`spi_state1`
278
279
280			`spi_rtx_sreg[15:0]`
281			`spi_rtx_sreg[15:0]`
282
283
284			`spi_bitcnt[4:0]`
285			`spi_bitcnt[4:0]`
286
287
288			`IO: Timer`
289			`label`
290
291
292			`ctrl[10:0]`
293			`ctrl[10:0]`
294
295
296			`thres[15:0]`
297			`thres[15:0]`
298			`HEXRADIX`
299
300
301			`prsc_tick`
302			`prsc_tick`
303
304
305			`cnt[15:0]`
306			`cnt[15:0]`
307
308
309			`irq_o`
310			`irq_o`
311
312
313			`nco_prsc_tick`
314			`nco_prsc_tick`
315
316
317			`nco_tuning_word[15:0]`
318			`nco_tuning_word[15:0]`
319
320
321			`nco_phase_accu[16:0]`
322			`nco_phase_accu[16:0]`
323
324
325			`timer_fg_o`
326			`timer_fg_o`
327
328
329			`IO: GPIO`
330			`label`
331
332
333			`gpio_o[15:0]`
334			`gpio_o[15:0]`
335
336
337			`gpio_i[15:0]`
338			`gpio_i[15:0]`
339
340
341			`irq_o`
342			`irq_o`
343
344
345			`IO: Watchdog`
346			`label`
347
348
349			`enable`
350			`enable`
351
352
353			`cnt[16:0]`
354			`cnt[16:0]`
355
356
357			`IO: Wishbone Bus Interface`
358			`label`
359
360
361			`enable`
362			`enable`
363
364
365			`pending`
366			`pending`
367
368
369			`wb_adr_o[31:0]`
370			`wb_adr_o[31:0]`
371
372
373			`wb_dat_i[31:0]`
374			`wb_dat_i[31:0]`
375
376
377			`wb_dat_o[31:0]`
378			`wb_dat_o[31:0]`
379
380
381			`wb_we_o`
382			`wb_we_o`
383
384
385			`wb_sel_o[3:0]`
386			`wb_sel_o[3:0]`
387			`BINARYRADIX`
388
389
390			`wb_stb_o`
391			`wb_stb_o`
392
393
394			`wb_cyc_o`
395			`wb_cyc_o`
396
397
398			`wb_ack_i`
399			`wb_ack_i`
400
401
402			`Sysconfig`
403			`label`
404
405
406			`info_addr[2:0]`
407			`info_addr[2:0]`
408
409
410			`rden`
411			`rden`
412
413
414			`acc_en`
415			`acc_en`
416
417
418			`sysinfo_mem[0:7][15:0]`
419			`sysinfo_mem[0:7][15:0]`
420
421
422			`IO: MulDiv`
423			`label`
424
425
426			`rden_i`
427			`rden_i`
428
429
430			`wr_en`
431			`wr_en`
432
433
434			`opa[15:0]`
435			`opa[15:0]`
436			`SIGNEDDECRADIX`
437
438
439			`opb[15:0]`
440			`opb[15:0]`
441			`SIGNEDDECRADIX`
442
443
444			`resx[15:0]`
445			`resx[15:0]`
446
447
448			`resy[15:0]`
449			`resy[15:0]`
450
451
452			`func_rst`
453			`func_rst`
454
455
456			`ctrl_state`
457			`ctrl_state`
458
459
460			`operation`
461			`operation`
462
463
464			`start`
465			`start`
466
467
468			`run`
469			`run`
470
471
472			`remainder[15:0]`
473			`remainder[15:0]`
474			`SIGNEDDECRADIX`
475
476
477			`quotient[15:0]`
478			`quotient[15:0]`
479			`SIGNEDDECRADIX`
480
481
482			`product[31:0]`
483			`product[31:0]`
484			`SIGNEDDECRADIX`
485
486
487			`IO: CRC`
488			`label`
489
490
491			`wren`
492			`wren`
493
494
495			`idata[7:0]`
496			`idata[7:0]`
497
498
499			`start`
500			`start`
501
502
503			`mode`
504			`mode`
505
506
507			`cnt[2:0]`
508			`cnt[2:0]`
509
510
511			`run`
512			`run`
513
514
515			`crc_bit`
516			`crc_bit`
517
518
519			`poly[31:0]`
520			`poly[31:0]`
521
522
523			`crc_sr[31:0]`
524			`crc_sr[31:0]`
525
526
527			`IO: PWM`
528			`label`
529
530
531			`pwm_o[3:0]`
532			`pwm_o[3:0]`
533
534
535			`pwm_ch[0:3][7:0]`
536			`pwm_ch[0:3][7:0]`
537
538
539			`IO: TWI`
540			`label`
541
542
543			`wr_en`
544			`wr_en`
545
546
547			`rd_en`
548			`rd_en`
549
550
551			`twi_clk`
552			`twi_clk`
553
554
555			`arbiter[2:0]`
556			`arbiter[2:0]`
557			`BINARYRADIX`
558
559
560			`ctrl[8:0]`
561			`ctrl[8:0]`
562
563
564			`twi_bitcnt[3:0]`
565			`twi_bitcnt[3:0]`
566
567
568			`twi_rtx_sreg[8:0]`
569			`twi_rtx_sreg[8:0]`
570
571
572			`twi_sda_io`
573			`twi_sda_io`
574
575
576			`twi_scl_io`
577			`twi_scl_io`
578
579
580			`IO: EXIRQ`
581			`label`
582
583
584			`ext_irq_i[7:0]`
585			`ext_irq_i[7:0]`
586
587
588			`ext_ack_o[7:0]`
589			`ext_ack_o[7:0]`
590
591
592			`acc_en`
593			`acc_en`
594
595
596			`wren`
597			`wren`
598
599
600			`rden`
601			`rden`
602
603
604			`enable`
605			`enable`
606
607
608			`state`
609			`state`
610
611
612			`irq_raw[7:0]`
613			`irq_raw[7:0]`
614
615
616			`irq_enable[7:0]`
617			`irq_enable[7:0]`
618
619
620			`ack_mask[7:0]`
621			`ack_mask[7:0]`
622
623
624			`irq_valid[7:0]`
625			`irq_valid[7:0]`
626
627
628			`irq_buf[7:0]`
629			`irq_buf[7:0]`
630
631
632			`irq_src_reg[2:0]`
633			`irq_src_reg[2:0]`
634
635
636			`sw_trig`
637			`sw_trig`
638
639
640			`sw_irq[7:0]`
641			`sw_irq[7:0]`
642
643
644			`cpu_irq_o`
645			`cpu_irq_o`
646
647