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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V-compliant)
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[![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32)
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[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
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## Table of Content
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [**Getting Started**](#Getting-Started)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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## Introduction
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The **NEORV32 processor** is a customizable full-scale mikrocontroller-like processor system based on the RISC-V-compliant
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`rv32i` NEORV32 CPU with optional `M`, `E`, `C` and `U`, `Zicsr` and `Zifencei` extensions and optional physical memory protection (PMP).
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The CPU was built from scratch and is compliant to the *Unprivileged ISA Specification Version 2.2* and a subset of the *Privileged Architecture
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Specification Version 1.12-draft*.
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The **processor** is intended as auxiliary processor within a larger SoC designs or as stand-alone
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custom microcontroller. Its top entity can be directly synthesized for any FPGA without modifications and
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provides a full-scale RISC-V based microcontroller with common peripherals like GPIO, serial interfaces for
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UART, I²C and SPI, timers, external bus interface and embedded memories. All optional features beyond the
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base CPU can be enabled and configured via VHDL generics.
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Alternatively, you can use the **NEORV32 CPU** as stand-alone central processing unit and build your own microcontroller
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or processor system around it.
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This project comes with a complete software ecosystem that features core libraries for high-level
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usage of the provided functions and peripherals, application makefiles, a runtime environment and
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several example programs. All software source files provide a doxygen-based documentary.
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The project is intended to work "out of the box". Just synthesize the test setup from this project,
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upload it to your FPGA board of choice and start playing with the NEORV32. If you do not want to
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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###  Key Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `rv32Zifencei` and PMP (physical memory protection) extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Highly configurable CPU and processor setup
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### Design Principles
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 * From zero to main(): Completely open source and documented.
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 * Plain VHDL without technology-specific parts like attributes, macros or primitives.
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 * Easy to use – working out of the box.
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 * Clean synchronous design, no wacky combinatorial interfaces.
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 * The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project component                                                               | CI status | Note     |
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|:--------------------------------------------------------------------------------|:----------|:---------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32)                       | [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) | [![sw doc](https://img.shields.io/badge/SW%20documentation-gh--pages-blue)](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt)          | [![Build Status](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [![Build Status](https://travis-ci.com/stnolting/neorv32_riscv_compliance.svg?branch=master)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### Non RISC-V-Compliant Issues
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `mcause` CSR is read-only
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The physical memory protection (**PMP**) only supports `NAPOT` mode and only up to 8 regions
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### Custom CPU Extensions
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The custom extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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### To-Do / Wish List
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- Add AXI / AXI-Lite bridges
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Synthesis results for more platforms
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Make a 64-bit branch someday
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## Features
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### Processor Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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Highly customizable processor configuration:
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional internal bootloader with UART console and automatic SPI flash boot option
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- Optional machine system timer (MTIME), RISC-V-compliant
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- Optional universal asynchronous receiver and transmitter (UART)
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- Optional 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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- Optional two wire serial interface controller (TWI), compatible to the I²C standard
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- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- Optional watchdog timer (WDT)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- Optional GARO-based true random number generator (TRNG)
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- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- System configuration information memory to check hardware configuration by software (SYSINFO)
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### CPU Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_cpu.png)
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The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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**General**:
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  * Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch)
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  * Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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  * No hardware support of unaligned accesses - they will trigger an exception
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  * Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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**RV32I base instruction set** (`I` extension):
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  * ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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  * Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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  * Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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  * System instructions: `ECALL` `EBREAK` `FENCE`
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**Compressed instructions** (`C` extension):
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  * ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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  * Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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  * Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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  * Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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**Embedded CPU version** (`E` extension):
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  * Reduced register file (only the 16 lowest registers)
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**Integer multiplication and division hardware** (`M` extension):
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  * Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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  * Division instructions: `DIV` `DIVU` `REM` `REMU`
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**Privileged architecture / CSR access** (`Zicsr` extension):
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  * Privilege levels: `M-mode` (Machine mode)
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  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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  * System instructions: `MRET` `WFI`
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  * Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
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  * Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid`
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  * Supported exceptions and interrupts:
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    * Misaligned instruction address
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    * Instruction access fault
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    * Illegal instruction
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    * Breakpoint (via `ebreak` instruction)
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    * Load address misaligned
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    * Load access fault
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    * Store address misaligned
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    * Store access fault
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    * Environment call from M-mode (via `ecall` instruction)
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    * Machine timer interrupt `mti` (via processor's MTIME unit)
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    * Machine software interrupt `msi` (via external signal)
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    * Machine external interrupt `mei` (via external signal)
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    * Four fast interrupt requests (custom extension)
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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  * Privilege levels: `M-mode` (Machine mode) + `U-Mode` (User mode)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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  * System instructions: `FENCEI`
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**Physical memory protection** (`PMP`, requires `Zicsr` extension):
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  * Additional machine CSRs: `pmpcfgx` `pmpaddrx`
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## FPGA Implementation Results
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (no PMP). No constraints were used at all.
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### CPU
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Results generated for hardware version: `1.3.0.0`
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| CPU Configuration                | LEs        | FFs      | Memory bits | DSPs | f_max   |
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|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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| `rv32i`                          |       1122 |      481 |       2048  |    0 | 110 MHz |
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| `rv32i`   + `Zicsr` + `Zifencei` |       1891 |      819 |       2048  |    0 | 100 MHz |
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| `rv32im`  + `Zicsr` + `Zifencei` |       2496 |     1067 |       2048  |    0 | 100 MHz |
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| `rv32imc` + `Zicsr` + `Zifencei` |       2734 |     1066 |       2048  |    0 | 100 MHz |
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| `rv32emc` + `Zicsr` + `Zifencei` |       2722 |     1066 |       1024  |    0 | 100 MHz |
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### Processor-Internal Peripherals and Memories
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Results generated for hardware version: `1.3.0.0`
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| Module    | Description                                     | LEs | FFs | Memory bits | DSPs |
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|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| BOOT ROM  | Bootloader ROM (4kB)                            |   4 |   1 |      32 768 |    0 |
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| BUSSWITCH | Mux for CPU I & D interfaces                    |  62 |   8 |           0 |    0 |
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| DEVNULL   | Dummy device                                    |   3 |   1 |           0 |    0 |
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| DMEM      | Processor-internal data memory (8kB)            |  12 |   2 |      65 536 |    0 |
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| GPIO      | General purpose input/output ports              |  40 |  33 |           0 |    0 |
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| IMEM      | Processor-internal instruction memory (16kb)    |   7 |   2 |     131 072 |    0 |
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| MTIME     | Machine system timer                            | 266 | 166 |           0 |    0 |
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| PWM       | Pulse-width modulation controller               |  72 |  69 |           0 |    0 |
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| SPI       | Serial peripheral interface                     | 198 | 125 |           0 |    0 |
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| SYSINFO   | System configuration information memory         |  10 |   9 |           0 |    0 |
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| TRNG      | True random number generator                    | 105 |  93 |           0 |    0 |
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| TWI       | Two-wire interface                              |  75 |  44 |           0 |    0 |
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| UART      | Universal asynchronous receiver/transmitter     | 153 | 108 |           0 |    0 |
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| WDT       | Watchdog timer                                  |  59 |  45 |           0 |    0 |
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### Exemplary FPGA Setups
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Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
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no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
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processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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to FPGA pins - except for the Wishbone bus and the interrupt signals.
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Results generated for hardware version: `1.3.0.0`
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| Vendor  | FPGA                              | Board            | Toolchain               | Impl. strategy |CPU                               | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency      |
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|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:|
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| Intel   | Cyclone IV `EP4CE22F17C6N`        | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced       | `rv32imc` + `Zicsr` + `Zifencei` | 3934 (18%) | 1799  (8%) | 0 (0%) | 231424 (38%) |          - |        - |        100 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0     | Radiant 2.1 (LSE)       | timing         | `rv32ic`  + `Zicsr` + `Zifencei` | 4895 (92%) | 1636 (31%) | 0 (0%) |            - |   12 (40%) | 4 (100%) | *c* 22.875 MHz |
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| Xilinx  | Artix-7 `XC7A35TICSG324-1L`       | Arty A7-35T      | Vivado 2019.2           | default        | `rv32imc` + `Zicsr` + `Zifencei` | 2432 (12%) | 1852  (4%) | 0 (0%) |            - |    8 (16%) |        - |    *c* 100 MHz |
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**Notes**
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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bootloader to store and automatically boot an application program after reset (both tested successfully).
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## Performance
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### CoreMark Benchmark
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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Results generated for hardware version: `1.3.0.0`
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274
~~~
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**Configuration**
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Hardware:    32kB IMEM, 16kB DMEM, 100MHz clock
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CoreMark:    2000 iterations, MEM_METHOD is MEM_STACK
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Compiler:    RISCV32-GCC 10.1.0
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Peripherals: UART for printing the results
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~~~
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| CPU                              | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
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|:---------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
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| `rv32i`   + `Zicsr` + `Zifencei` |    21 600 bytes |        `-O2` |          27.02 |        0.2702 |
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| `rv32im`  + `Zicsr` + `Zifencei` |    20 976 bytes |        `-O2` |          57.14 |        0.5714 |
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| `rv32imc` + `Zicsr` + `Zifencei` |    16 348 bytes |        `-O2` |          57.14 |        0.5714 |
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### Instruction Cycles
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The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
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CPU extensions.
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Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
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`M` extension use a bit-serial approach and require several cycles for completion.
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The following table shows the performance results for successfully running 2000 CoreMark
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iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
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dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
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by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`.
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Results generated for hardware version: `1.3.0.0`
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| CPU                              | Required Clock Cycles | Executed Instructions | Average CPI |
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|:---------------------------------|----------------------:|----------------------:|:-----------:|
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| `rv32i`   + `Zicsr` + `Zifencei` |         7 433 933 906 |         1 494 298 800 |        4.97 |
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| `rv32im`  + `Zicsr` + `Zifencei` |         3 589 861 906 |           628 281 454 |        5.71 |
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| `rv32imc` + `Zicsr` + `Zifencei` |         3 587 131 226 |           628 282 016 |        5.70 |
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## Top Entities
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The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
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(except for the TWI signals, which are of type *std_logic*).
319
 
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The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
321
 
322
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
323 2 zero_gravi
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
324
 
325 14 zero_gravi
Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
326
 
327
### Processor
328
 
329 2 zero_gravi
```vhdl
330
entity neorv32_top is
331
  generic (
332
    -- General --
333 12 zero_gravi
    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
334 8 zero_gravi
    BOOTLOADER_USE               : boolean := true;   -- implement processor-internal bootloader?
335
    CSR_COUNTERS_USE             : boolean := true;   -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
336 12 zero_gravi
    USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
337 2 zero_gravi
    -- RISC-V CPU Extensions --
338 14 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
339 8 zero_gravi
    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
340 14 zero_gravi
    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
341 15 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
342 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
343
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?
344 15 zero_gravi
    -- Physical Memory Protection (PMP) --
345
    PMP_USE                      : boolean := false;  -- implement PMP?
346
    PMP_NUM_REGIONS              : natural := 4;      -- number of regions (max 16)
347
    PMP_GRANULARITY              : natural := 15;     -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
348 2 zero_gravi
    -- Memory configuration: Instruction memory --
349 8 zero_gravi
    MEM_ISPACE_BASE              : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
350
    MEM_ISPACE_SIZE              : natural := 16*1024; -- total size of instruction memory space in byte
351 14 zero_gravi
    MEM_INT_IMEM_USE             : boolean := true;   -- implement processor-internal instruction memory
352 8 zero_gravi
    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
353 14 zero_gravi
    MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
354 2 zero_gravi
    -- Memory configuration: Data memory --
355 8 zero_gravi
    MEM_DSPACE_BASE              : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
356
    MEM_DSPACE_SIZE              : natural := 8*1024; -- total size of data memory space in byte
357
    MEM_INT_DMEM_USE             : boolean := true;   -- implement processor-internal data memory
358
    MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
359 2 zero_gravi
    -- Memory configuration: External memory interface --
360 8 zero_gravi
    MEM_EXT_USE                  : boolean := false;  -- implement external memory bus interface?
361
    MEM_EXT_REG_STAGES           : natural := 2;      -- number of interface register stages (0,1,2)
362 14 zero_gravi
    MEM_EXT_TIMEOUT              : natural := 15;     -- cycles after which a valid bus access will timeout
363 2 zero_gravi
    -- Processor peripherals --
364 8 zero_gravi
    IO_GPIO_USE                  : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
365
    IO_MTIME_USE                 : boolean := true;   -- implement machine system timer (MTIME)?
366
    IO_UART_USE                  : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
367
    IO_SPI_USE                   : boolean := true;   -- implement serial peripheral interface (SPI)?
368
    IO_TWI_USE                   : boolean := true;   -- implement two-wire interface (TWI)?
369
    IO_PWM_USE                   : boolean := true;   -- implement pulse-width modulation unit (PWM)?
370
    IO_WDT_USE                   : boolean := true;   -- implement watch dog timer (WDT)?
371
    IO_TRNG_USE                  : boolean := false;  -- implement true random number generator (TRNG)?
372
    IO_DEVNULL_USE               : boolean := true    -- implement dummy device (DEVNULL)?
373 2 zero_gravi
  );
374
  port (
375
    -- Global control --
376 14 zero_gravi
    clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
377
    rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
378 2 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_USE = true) --
379 14 zero_gravi
    wb_adr_o   : out std_ulogic_vector(31 downto 0); -- address
380
    wb_dat_i   : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
381
    wb_dat_o   : out std_ulogic_vector(31 downto 0); -- write data
382
    wb_we_o    : out std_ulogic; -- read/write
383
    wb_sel_o   : out std_ulogic_vector(03 downto 0); -- byte enable
384
    wb_stb_o   : out std_ulogic; -- strobe
385
    wb_cyc_o   : out std_ulogic; -- valid cycle
386
    wb_ack_i   : in  std_ulogic := '0'; -- transfer acknowledge
387
    wb_err_i   : in  std_ulogic := '0'; -- transfer error
388 12 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_USE = true) --
389 14 zero_gravi
    fence_o    : out std_ulogic; -- indicates an executed FENCE operation
390
    fencei_o   : out std_ulogic; -- indicates an executed FENCEI operation
391 2 zero_gravi
    -- GPIO (available if IO_GPIO_USE = true) --
392 14 zero_gravi
    gpio_o     : out std_ulogic_vector(15 downto 0); -- parallel output
393
    gpio_i     : in  std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
394 2 zero_gravi
    -- UART (available if IO_UART_USE = true) --
395 14 zero_gravi
    uart_txd_o : out std_ulogic; -- UART send data
396
    uart_rxd_i : in  std_ulogic := '0'; -- UART receive data
397 2 zero_gravi
    -- SPI (available if IO_SPI_USE = true) --
398 14 zero_gravi
    spi_sck_o  : out std_ulogic; -- SPI serial clock
399
    spi_sdo_o  : out std_ulogic; -- controller data out, peripheral data in
400
    spi_sdi_i  : in  std_ulogic := '0'; -- controller data in, peripheral data out
401
    spi_csn_o  : out std_ulogic_vector(07 downto 0); -- SPI CS
402 2 zero_gravi
    -- TWI (available if IO_TWI_USE = true) --
403 14 zero_gravi
    twi_sda_io : inout std_logic := 'H'; -- twi serial data line
404
    twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
405 2 zero_gravi
    -- PWM (available if IO_PWM_USE = true) --
406 14 zero_gravi
    pwm_o      : out std_ulogic_vector(03 downto 0); -- pwm channels
407
    -- Interrupts --
408
    msw_irq_i  : in  std_ulogic := '0'; -- machine software interrupt
409
    mext_irq_i : in  std_ulogic := '0'  -- machine external interrupt
410 2 zero_gravi
  );
411
end neorv32_top;
412
```
413
 
414 14 zero_gravi
### CPU
415 2 zero_gravi
 
416 14 zero_gravi
```vhdl
417
entity neorv32_cpu is
418
  generic (
419
    -- General --
420
    CSR_COUNTERS_USE             : boolean := true;  -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
421
    HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
422
    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
423
    -- RISC-V CPU Extensions --
424
    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
425
    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
426
    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
427 15 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
428 14 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
429
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
430 15 zero_gravi
    -- Physical Memory Protection (PMP) --
431
    PMP_USE                      : boolean := false; -- implement PMP?
432
    PMP_NUM_REGIONS              : natural := 4;     -- number of regions (max 16)
433
    PMP_GRANULARITY              : natural := 15;    -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
434 14 zero_gravi
    -- Bus Interface --
435
    BUS_TIMEOUT                  : natural := 15     -- cycles after which a valid bus access will timeout
436
  );
437
  port (
438
    -- global control --
439
    clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
440
    rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
441
    -- instruction bus interface --
442
    i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
443
    i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
444
    i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
445
    i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
446
    i_bus_we_o     : out std_ulogic; -- write enable
447
    i_bus_re_o     : out std_ulogic; -- read enable
448
    i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
449
    i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
450
    i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
451
    i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
452
    -- data bus interface --
453
    d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
454
    d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
455
    d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
456
    d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
457
    d_bus_we_o     : out std_ulogic; -- write enable
458
    d_bus_re_o     : out std_ulogic; -- read enable
459
    d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
460
    d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
461
    d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
462
    d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
463
    -- system time input from MTIME --
464
    time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
465
    -- interrupts (risc-v compliant) --
466
    msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
467
    mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
468
    mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
469
    -- fast interrupts (custom) --
470
    firq_i         : in  std_ulogic_vector(3 downto 0) := (others => '0')
471
  );
472
end neorv32_cpu;
473
```
474 2 zero_gravi
 
475 14 zero_gravi
 
476
 
477 2 zero_gravi
## Getting Started
478
 
479
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
480
 
481
[![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
482
 
483
 
484 14 zero_gravi
### Toolchain
485 2 zero_gravi
 
486
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
487
and build the toolchain by yourself, or you can download a prebuilt one and install it.
488
 
489 14 zero_gravi
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
490
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
491 2 zero_gravi
 
492 14 zero_gravi
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain.
493
Make sure to use the `ilp32` or `ilp32e` ABI.
494 2 zero_gravi
 
495 15 zero_gravi
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
496
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
497 2 zero_gravi
 
498
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
499
 
500
 
501 11 zero_gravi
### Dowload the NEORV32 and Create a Hardware Project
502 2 zero_gravi
 
503 12 zero_gravi
Get the sources of the NEORV32 Processor project. You can either download a [release](https://github.com/stnolting/neorv32/releases)
504
or get the most recent version of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip) or using `git clone` (suggested for easy project updates via `git pull`):
505
 
506 2 zero_gravi
    $ git clone https://github.com/stnolting/neorv32.git
507
 
508 12 zero_gravi
Create a new project with your FPGA design tool of choice and add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
509
folder to this project. Make sure to add them to a **new library** called `neorv32`.
510 2 zero_gravi
 
511 11 zero_gravi
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
512
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
513
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
514 12 zero_gravi
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART, clock, reset and some GPIO output sginals are
515 11 zero_gravi
propagated (basically, its a FPGA "hello world" example):
516 2 zero_gravi
 
517
```vhdl
518 9 zero_gravi
  entity neorv32_test_setup is
519
    port (
520
      -- Global control --
521
      clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
522
      rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
523
      -- GPIO --
524
      gpio_o     : out std_ulogic_vector(7 downto 0); -- parallel output
525
      -- UART --
526
      uart_txd_o : out std_ulogic; -- UART send data
527
      uart_rxd_i : in  std_ulogic := '0' -- UART receive data
528
    );
529
  end neorv32_test_setup;
530 2 zero_gravi
```
531
 
532
 
533
### Compiling and Uploading One of the Example Projects
534
 
535 11 zero_gravi
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
536 2 zero_gravi
`sw/example/blink_led` and run:
537
 
538
    neorv32/sw/example/blink_led$ make check
539
 
540 9 zero_gravi
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
541
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
542
executable `neorv32_exe.bin` in the same folder.
543 2 zero_gravi
 
544
    neorv32/sw/example/blink_led$ make clean_all compile
545
 
546
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
547
uses the following default UART configuration:
548
 
549
- 19200 Baud
550
- 8 data bits
551
- 1 stop bit
552
- No parity bits
553
- No transmission / flow control protocol (raw bytes only)
554
- Newline on `\r\n` (carriage return & newline)
555
 
556 9 zero_gravi
Use the bootloader console to upload the `neorv32_exe.bin` file and run your application image.
557 2 zero_gravi
 
558 9 zero_gravi
```
559
  << NEORV32 Bootloader >>
560
 
561
  BLDV: Jul  6 2020
562
  HWV:  1.0.1.0
563
  CLK:  0x0134FD90 Hz
564 13 zero_gravi
  USER: 0x0001CE40
565 9 zero_gravi
  MISA: 0x42801104
566
  CONF: 0x03FF0035
567
  IMEM: 0x00010000 bytes @ 0x00000000
568
  DMEM: 0x00010000 bytes @ 0x80000000
569
 
570
  Autoboot in 8s. Press key to abort.
571
  Aborted.
572
 
573
  Available CMDs:
574
   h: Help
575
   r: Restart
576
   u: Upload
577
   s: Store to flash
578
   l: Load from flash
579
   e: Execute
580
  CMD:> u
581
  Awaiting neorv32_exe.bin... OK
582
  CMD:> e
583
  Booting...
584
 
585
  Blinking LED demo program
586
```
587 2 zero_gravi
 
588 9 zero_gravi
Going further: Take a look at the _Let's Get It Started!_ chapter of the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
589 2 zero_gravi
 
590
 
591
 
592 9 zero_gravi
## Contribute
593 2 zero_gravi
 
594 9 zero_gravi
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
595
to open a [new issue](https://github.com/stnolting/neorv32/issues).
596 2 zero_gravi
 
597 9 zero_gravi
If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
598
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
599 2 zero_gravi
 
600
 
601 9 zero_gravi
 
602 11 zero_gravi
## Legal
603 2 zero_gravi
 
604 12 zero_gravi
This project is released under the BSD 3-Clause license. No copyright infringement intended.
605 11 zero_gravi
Other implied or used projects might have different licensing - see their documentation to get more information.
606
 
607
#### Citation
608
 
609 2 zero_gravi
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
610
 
611
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
612
 
613 9 zero_gravi
#### BSD 3-Clause License
614 2 zero_gravi
 
615
Copyright (c) 2020, Stephan Nolting. All rights reserved.
616
 
617
Redistribution and use in source and binary forms, with or without modification, are
618
permitted provided that the following conditions are met:
619
 
620
1. Redistributions of source code must retain the above copyright notice, this list of
621
conditions and the following disclaimer.
622
2. Redistributions in binary form must reproduce the above copyright notice, this list of
623
conditions and the following disclaimer in the documentation and/or other materials
624
provided with the distribution.
625
3. Neither the name of the copyright holder nor the names of its contributors may be used to
626
endorse or promote products derived from this software without specific prior written
627
permission.
628
 
629
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
630
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
631
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
632
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
633
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
634
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
635
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
636
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
637
OF THE POSSIBILITY OF SUCH DAMAGE.
638
 
639
 
640 9 zero_gravi
#### Limitation of Liability for External Links
641
 
642
Our website contains links to the websites of third parties („external links“). As the
643
content of these websites is not under our control, we cannot assume any liability for
644
such external content. In all cases, the provider of information of the linked websites
645
is liable for the content and accuracy of the information provided. At the point in time
646
when the links were placed, no infringements of the law were recognisable to us. As soon
647
as an infringement of the law becomes known to us, we will immediately remove the
648
link in question.
649
 
650
 
651 11 zero_gravi
#### Proprietary  Notice
652 9 zero_gravi
 
653 2 zero_gravi
"Windows" is a trademark of Microsoft Corporation.
654
 
655
"Artix" and "Vivado" are trademarks of Xilinx Inc.
656
 
657 11 zero_gravi
"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
658 2 zero_gravi
 
659 11 zero_gravi
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
660
 
661 2 zero_gravi
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
662
 
663 13 zero_gravi
"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
664 2 zero_gravi
 
665
 
666 11 zero_gravi
## Acknowledgement
667 9 zero_gravi
 
668 11 zero_gravi
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
669
 
670 2 zero_gravi
[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)
671
 
672
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
673
 
674
 
675
![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
676
 
677
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
678
 
679
 
680 14 zero_gravi
 
681 6 zero_gravi
Made with :coffee: in Hannover, Germany.

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