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<<<
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:sectnums:
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=== Control and Status Registers (CSRs)
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The following table shows a summary of all available CSRs. The address field defines the CSR address for
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the CSR access instructions. The *[ASM]* name can be used for (inline) assembly code and is directly
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understood by the assembler/compiler. The *[C]* names are defined by the NEORV32 core library and can be
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used as immediate in plain C code. The *R/W* column shows whether the CSR can be read and/or written.
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The NEORV32-specific CSRs are mapped to the official "custom CSRs" CSR address space.
10
 
11
[IMPORTANT]
12
The CSRs, the CSR-related instructions as well as the complete exception/interrupt processing
13
system are only available when the `CPU_EXTENSION_RISCV_Zicsr` generic is _true_.
14
 
15
[IMPORTANT]
16
When trying to write to a read-only CSR (like the `time` CSR) or when trying to access a nonexistent
17
CSR or when trying to access a machine-mode CSR from less-privileged user-mode an
18
illegal instruction exception is raised.
19
 
20
[NOTE]
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CSR reset value: Please note that most of the CSRs do *NOT* provide a dedicated reset. Hence,
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these CSRs are not initialized by a hardware reset and keep an *UNDEFINED* value until they are
23
explicitly initialized by the software (normally, this is already done by the NEORV32-specific
24
`crt0.S` start-up code). For more information see section <<_cpu_hardware_reset>>.
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26
**CSR Listing**
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28
The description of each single CSR provides the following summary:
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30
.CSR description
31
[cols="4,27,>7"]
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[frame="topbot",grid="none"]
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|======
34
| _Address_ | _Description_ | _ASM alias_
35
3+| Reset value: _CSR content after hardware reset_ (also see <<_cpu_hardware_reset>>)
36
3+| _Detailed description_
37
|======
38
 
39
.Not Implemented CSRs / CSR Bits
40
[IMPORTANT]
41
All CSR bits that are unused / not implemented / not shown are _hardwired to zero_. All CSRs that are not
42
implemented at all (and are not "disabled" using certain configuration generics) will trigger an exception on
43
access. The CSR that are implemented within the NEORV32 might cause an exception if they are disabled.
44
See the according CSR description for more information.
45
 
46
.Debug Mode CSRs
47
[IMPORTANT]
48
The _debug mode_ CSRs are not listed here since they are only accessible in debug mode and not during normal CPU operation.
49
See section <<_cpu_debug_mode_csrs>>.
50
 
51
 
52
<<<
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// ####################################################################################################################
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**CSR Listing Notes**
55
 
56
CSRs with the following notes ...
57
 
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* `X`: _custom_ - have or are a custom CPU-specific extension (that is allowed by the RISC-V specs)
59
* `R`: _read-only_ - are read-only (in contrast to the originally specified r/w capability)
60
* `C`: _constrained_ - have a constrained compatibility, not all specified bits are implemented
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62
.NEORV32 Control and Status Registers (CSRs)
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[cols="<6,<11,<16,^3,<25,^3"]
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[options="header"]
65
|=======================
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| Address | Name [ASM] | Name [C] | R/W | Function | Note
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6+^| **<<_floating_point_csrs>>**
68
| 0x001   | <<_fflags>>     | _CSR_FFLAGS_     | r/w | Floating-point accrued exceptions |
69
| 0x002   | <<_frm>>        | _CSR_FRM_        | r/w | Floating-point dynamic rounding mode |
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| 0x003   | <<_fcsr>>       | _CSR_FCSR_       | r/w | Floating-point control and status (`frm` + `fflags`) |
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6+^| **<<_machine_configuration_csrs>>**
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| 0x30a   | <<_menvcfg>>    | _CSR_MENVCFG_    | r/- | Machine environment configuration register - low word | `R`
73
| 0x31a   | <<_menvcfgh>>   | _CSR_MENVCFGH_   | r/- | Machine environment configuration register - low word | `R`
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6+^| **<<_machine_trap_setup_csrs>>**
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| 0x300   | <<_mstatus>>    | _CSR_MSTATUS_    | r/w | Machine status register - low word | `C`
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| 0x301   | <<_misa>>       | _CSR_MISA_       | r/- | Machine CPU ISA and extensions | `R`
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| 0x304   | <<_mie>>        | _CSR_MIE_        | r/w | Machine interrupt enable register | `X`
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| 0x305   | <<_mtvec>>      | _CSR_MTVEC_      | r/w | Machine trap-handler base address (for ALL traps) |
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| 0x306   | <<_mcounteren>> | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `C`
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| 0x310   | <<_mstatush>>   | _CSR_MSTATUSH_   | r/- | Machine status register - high word | `C`
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6+^| **<<_machine_trap_handling_csrs>>**
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| 0x340   | <<_mscratch>>   | _CSR_MSCRATCH_   | r/w | Machine scratch register |
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| 0x341   | <<_mepc>>       | _CSR_MEPC_       | r/w | Machine exception program counter |
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| 0x342   | <<_mcause>>     | _CSR_MCAUSE_     | r/w | Machine trap cause | `X`
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| 0x343   | <<_mtval>>      | _CSR_MTVAL_      | r/- | Machine bad address or instruction | `R`
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| 0x344   | <<_mip>>        | _CSR_MIP_        | r/w | Machine interrupt pending register | `X`
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6+^| **<<_machine_physical_memory_protection_csrs>>**
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| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>>     | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_   | r/w | Physical memory protection config. for region 0..63 | `C`
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| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
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6+^| **<<_machine_counter_and_timer_csrs>>**
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| 0xb00   | <<_mcycleh, `mcycle`>>      | _CSR_MCYCLE_     | r/w | Machine cycle counter low word |
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| 0xb02   | <<_minstreth, `minstret`>> | _CSR_MINSTRET_    | r/w | Machine instruction-retired counter low word |
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| 0xb80   | <<_mcycleh>>                | _CSR_MCYCLE_     | r/w | Machine cycle counter high word |
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| 0xb82   | <<_minstreth>>              | _CSR_MINSTRET_   | r/w | Machine instruction-retired counter high word |
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| 0xc00   | <<_cycleh, `cycle`>>        | _CSR_CYCLE_      | r/- | Cycle counter low word |
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| 0xc01   | <<_timeh, `time`>>          | _CSR_TIME_       | r/- | System time (from MTIME) low word |
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| 0xc02   | <<_instreth, `instret`>>    | _CSR_INSTRET_    | r/- | Instruction-retired counter low word |
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| 0xc80   | <<_cycleh>>                 | _CSR_CYCLEH_     | r/- | Cycle counter high word |
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| 0xc81   | <<_timeh>>                  | _CSR_TIMEH_      | r/- | System time (from MTIME) high word |
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| 0xc82   | <<_instreth>>               | _CSR_INSTRETH_   | r/- | Instruction-retired counter high word |
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6+^| **<<_hardware_performance_monitors_hpm_csrs>>**
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| 0x323 .. 0x33f | <<_mhpmevent, `mhpmevent3`>> .. <<_mhpmevent, `mhpmevent31`>>             | _CSR_MHPMEVENT3_ .. _CSR_MHPMEVENT31_       | r/w | Machine performance-monitoring event selector 3..31 | `X`
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| 0xb03 .. 0xb1f | <<_mhpmcounterh, `mhpmcounter3`>> .. <<_mhpmcounterh, `mhpmcounter31`>>   | _CSR_MHPMCOUNTER3_ .. _CSR_MHPMCOUNTER31_   | r/w | Machine performance-monitoring counter 3..31 low word |
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| 0xb83 .. 0xb9f | <<_mhpmcounterh, `mhpmcounter3h`>> .. <<_mhpmcounterh, `mhpmcounter31h`>> | _CSR_MHPMCOUNTER3H_ .. _CSR_MHPMCOUNTER31H_ | r/w | Machine performance-monitoring counter 3..31 high word |
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6+^| **<<_machine_counter_setup_csrs>>**
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| 0x320   | <<_mcountinhibit>> | _CSR_MCOUNTINHIBIT_ | r/w | Machine counter-enable register |
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6+^| **<<_machine_information_csrs>>**
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| 0xf11   | <<_mvendorid>>  | _CSR_MVENDORID_  | r/- | Vendor ID |
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| 0xf12   | <<_marchid>>    | _CSR_MARCHID_    | r/- | Architecture ID |
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| 0xf13   | <<_mimpid>>     | _CSR_MIMPID_     | r/- | Machine implementation ID / version |
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| 0xf14   | <<_mhartid>>    | _CSR_MHARTID_    | r/- | Machine thread ID |
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| 0xf15   | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
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|=======================
114
 
115
 
116
 
117
<<<
118
// ####################################################################################################################
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:sectnums:
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==== Floating-Point CSRs
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122
These CSRs are available if the `Zfinx` extensions is enabled (`CPU_EXTENSION_RISCV_Zfinx` is _true_).
123
Otherwise any access to the floating-point CSRs will raise an illegal instruction exception.
124
 
125
 
126
:sectnums!:
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===== **`fflags`**
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129
[cols="4,27,>7"]
130
[frame="topbot",grid="none"]
131
|======
132
| 0x001 | **Floating-point accrued exceptions** | `fflags`
133
3+| Reset value: _UNDEFINED_
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3+| The `fflags` CSR is compatible to the RISC-V specifications. It shows the accrued ("accumulated")
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exception flags in the lowest 5 bits. This CSR is only available if a floating-point CPU extension is enabled.
136
See the RISC-V ISA spec for more information.
137
|======
138
 
139
 
140
:sectnums!:
141
===== **`frm`**
142
 
143
[cols="4,27,>7"]
144
[frame="topbot",grid="none"]
145
|======
146
| 0x002 | **Floating-point dynamic rounding mode** | `frm`
147
3+| Reset value: _UNDEFINED_
148
3+| The `frm` CSR is compatible to the RISC-V specifications and is used to configure the rounding modes using
149
the lowest 3 bits. This CSR is only available if a floating-point CPU extension is enabled. See the RISC-V
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ISA spec for more information.
151
|======
152
 
153
 
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:sectnums!:
155
===== **`fcsr`**
156
 
157
[cols="4,27,>7"]
158
[frame="topbot",grid="none"]
159
|======
160
| 0x003 | **Floating-point control and status register** | `fcsr`
161
3+| Reset value: _UNDEFINED_
162
3+| The `fcsr` CSR is compatible to the RISC-V specifications. It provides combined read/write access to the
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`fflags` and `frm` CSRs. This CSR is only available if a floating-point CPU extension is enabled. See the
164
RISC-V ISA spec for more information.
165
|======
166
 
167
 
168
<<<
169
// ####################################################################################################################
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:sectnums:
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==== Machine Configuration CSRs
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173
:sectnums!:
174
===== **`menvcfg`**
175
 
176
[cols="4,27,>7"]
177
[frame="topbot",grid="none"]
178
|======
179
| 0x30a | **Machine environment configuration register** | `menvcfg`
180
3+| Reset value: _0x00000000_
181
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
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only exists if the `U` ISA extensions is enabled.
183
|======
184
 
185
 
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:sectnums!:
187
===== **`menvcfgh`**
188
 
189
[cols="4,27,>7"]
190
[frame="topbot",grid="none"]
191
|======
192
| 0x31a | **Machine environment configuration register - high word** | `menvcfgh`
193
3+| Reset value: _0x00000000_
194
3+| The features of this CSR are not implemented yet. The register is read-only. NOTE: This register
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only exists if the `U` ISA extensions is enabled.
196
|======
197
 
198
 
199
<<<
200
// ####################################################################################################################
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:sectnums:
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==== Machine Trap Setup CSRs
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204
:sectnums!:
205
===== **`mstatus`**
206
 
207
[cols="4,27,>7"]
208
[frame="topbot",grid="none"]
209
|======
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| 0x300 | **Machine status register** | `mstatus`
211
3+| Reset value: _0x00000000_
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3+| The `mstatus` CSR is compatible to the RISC-V specifications. It shows the CPU's current execution state.
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The following bits are implemented (all remaining bits are always zero and are read-only).
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|======
215
 
216
.Machine status register
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[cols="^1,<3,^1,<5"]
218
[options="header",grid="rows"]
219
|=======================
220
| Bit   | Name [C] | R/W | Function
221
| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
222
| 7     | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
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| 3     | _CSR_MSTATUS_MIE_  | r/w | Machine global interrupt enable flag
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|=======================
225
 
226
When entering an exception/interrupt, the `MIE` flag is copied to `MPIE` and cleared afterwards. When leaving
227
the exception/interrupt (via the `mret` instruction), `MPIE` is copied back to `MIE`.
228
 
229
 
230
:sectnums!:
231
===== **`misa`**
232
 
233
[cols="4,27,>7"]
234
[frame="topbot",grid="none"]
235
|======
236
| 0x301 | **ISA and extensions** | `misa`
237
3+| Reset value: _configuration dependant_
238
3+| The `misa` CSR gives information about the actual CPU features. The lowest 26 bits show the implemented
239
CPU extensions. The following bits are implemented (all remaining bits are always zero and are read-only).
240
|======
241
 
242
[IMPORTANT]
243
The `misa` CSR is not fully RISC-V-compatible as it is read-only. Hence, implemented CPU
244
extensions cannot be switch on/off during runtime. For compatibility reasons any write access to this
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CSR is simply ignored and will _NOT_ cause an illegal instruction exception.
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247
.Machine ISA and extension register
248
[cols="^1,<3,^1,<5"]
249
[options="header",grid="rows"]
250
|=======================
251
| Bit   | Name [C] | R/W | Function
252
| 31:30 | _CSR_MISA_MXL_HI_EXT_ : _CSR_MISA_MXL_LO_EXT_ | r/- | 32-bit architecture indicator (always _01_)
253
| 23    | _CSR_MISA_X_EXT_ | r/- | `X` extension bit is always set to indicate custom non-standard extensions
254
| 20    | _CSR_MISA_U_EXT_ | r/- | `U` CPU extension (user mode) available, set when _CPU_EXTENSION_RISCV_U_ enabled
255
| 12    | _CSR_MISA_M_EXT_ | r/- | `M` CPU extension (mul/div) available, set when _CPU_EXTENSION_RISCV_M_ enabled
256
| 8     | _CSR_MISA_I_EXT_ | r/- | `I` CPU base ISA, cleared when _CPU_EXTENSION_RISCV_E_ enabled
257
| 4     | _CSR_MISA_E_EXT_ | r/- | `E` CPU extension (embedded) available, set when _CPU_EXTENSION_RISCV_E_ enabled
258
| 2     | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
259
| 0     | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
260
|=======================
261
 
262
[TIP]
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Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found
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in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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266
 
267
:sectnums!:
268
===== **`mie`**
269
 
270
[cols="4,27,>7"]
271
[frame="topbot",grid="none"]
272
|======
273
| 0x304 | **Machine interrupt-enable register** | `mie`
274
3+| Reset value: _UNDEFINED_
275
3+| The `mie` CSR is compatible to the RISC-V specifications and features custom extensions for the fast
276
interrupt channels. It is used to enabled specific interrupts sources. Please note that interrupts also have to be
277
globally enabled via the `CSR_MSTATUS_MIE` flag of the `mstatus` CSR. The following bits are implemented
278
(all remaining bits are always zero and are read-only):
279
|======
280
 
281
.Machine ISA and extension register
282
[cols="^1,<3,^1,<5"]
283
[options="header",grid="rows"]
284
|=======================
285
| Bit   | Name [C] | R/W | Function
286
| 31:16 | _CSR_MIE_FIRQ15E_ : _CSR_MIE_FIRQ0E_ | r/w | Fast interrupt channel 15..0 enable
287
| 11    | _CSR_MIE_MEIE_ | r/w | Machine _external_ interrupt enable
288
| 7     | _CSR_MIE_MTIE_ | r/w | Machine _timer_ interrupt enable (from _MTIME_)
289
| 3     | _CSR_MIE_MSIE_ | r/w | Machine _software_ interrupt enable
290
|=======================
291
 
292
 
293
:sectnums!:
294
===== **`mtvec`**
295
 
296
[cols="4,27,>7"]
297
[frame="topbot",grid="none"]
298
|======
299
| 0x305 | **Machine trap-handler base address** | `mtvec`
300
3+| Reset value: _UNDEFINED_
301
3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
302
traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
303 64 zero_gravi
source. The lowest two bits of this register are always zero and cannot be modified (= address mode only).
304 60 zero_gravi
|======
305
 
306
.Machine trap-handler base address
307
[cols="^1,^1,<8"]
308
[options="header",grid="rows"]
309
|=======================
310
| Bit  | R/W | Function
311
| 31:2 | r/w | 4-byte aligned base address of trap base handler
312
| 1:0  | r/- | Always zero
313
|=======================
314
 
315
 
316
:sectnums!:
317
===== **`mcounteren`**
318
 
319
[cols="4,27,>7"]
320
[frame="topbot",grid="none"]
321
|======
322
| 0x306 | **Machine counter enable** | `mcounteren`
323
3+| Reset value: _UNDEFINED_
324
3+| The `mcounteren` CSR is compatible to the RISC-V specifications. The bits of this CSR define which
325
counter/timer CSR can be accessed (read) from code running in a less-privileged modes. For example,
326 61 zero_gravi
if user-level code tries to read from a counter/timer CSR without enabled access, an illegal instruction
327 64 zero_gravi
exception is raised. NOTE: If the `U` ISA extension is not enabled this CSR does not exist.
328 60 zero_gravi
|======
329
 
330
.Machine counter enable register
331
[cols="^1,<3,^1,<5"]
332
[options="header",grid="rows"]
333
|=======================
334
| Bit   | Name [C] | R/W | Function
335 64 zero_gravi
| 31:3  | `0`                 | r/- | Always zero: user-level code is **not** allowed to read HPM counters
336 60 zero_gravi
| 2     | _CSR_MCOUNTEREN_IR_ | r/w | User-level code is allowed to read `cycle[h]` CSRs when set
337
| 1     | _CSR_MCOUNTEREN_TM_ | r/w | User-level code is allowed to read `time[h]` CSRs when set
338
| 0     | _CSR_MCOUNTEREN_CY_ | r/w | User-level code is allowed to read `instret[h]` CSRs when set
339
|=======================
340
 
341
 
342 62 zero_gravi
:sectnums!:
343
===== **`mstatush`**
344
 
345
[cols="4,27,>7"]
346
[frame="topbot",grid="none"]
347
|======
348
| 0x310 | **Machine status register - high word** | `mstatush`
349
3+| Reset value: _0x00000000_
350
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
351
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
352
|======
353
 
354
[NOTE]
355
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
356
return zero. However, any access will not raise an illegal instruction exception. The CSR address is implemented
357
in order to comply with the RISC-V privilege architecture specs.
358
 
359
 
360
 
361 60 zero_gravi
<<<
362
// ####################################################################################################################
363
:sectnums:
364 66 zero_gravi
==== Machine Trap Handling CSRs
365 60 zero_gravi
 
366
:sectnums!:
367
===== **`mscratch`**
368
 
369
[cols="4,27,>7"]
370
[frame="topbot",grid="none"]
371
|======
372
| 0x340 | **Scratch register for machine trap handlers** | `mscratch`
373
3+| Reset value: _UNDEFINED_
374
3+| The `mscratch` CSR is compatible to the RISC-V specifications. It is a general purpose scratch register that
375
can be used by the exception/interrupt handler. The content pf this register after reset is undefined.
376
|======
377
 
378
:sectnums!:
379
===== **`mepc`**
380
 
381
[cols="4,27,>7"]
382
[frame="topbot",grid="none"]
383
|======
384
| 0x341 | **Machine exception program counter** | `mepc`
385
3+| Reset value: _UNDEFINED_
386
3+| The `mepc` CSR is compatible to the RISC-V specifications. For exceptions (like an illegal instruction) this
387
register provides the address of the exception-causing instruction. For Interrupt (like a machine timer
388
interrupt) this register provides the address of the next not-yet-executed instruction.
389
|======
390
 
391
:sectnums!:
392
===== **`mcause`**
393
 
394
[cols="4,27,>7"]
395
[frame="topbot",grid="none"]
396
|======
397
| 0x342 | **Machine trap cause** | `mcause`
398
3+| Reset value: _UNDEFINED_
399
3+| The `mcause` CSR is compatible to the RISC-V specifications. It show the cause ID for a taken exception.
400
|======
401
 
402
.Machine trap cause register
403
[cols="^1,^1,<8"]
404
[options="header",grid="rows"]
405
|=======================
406
| Bit  | R/W | Function
407
| 31   | r/w | `1` if the trap is caused by an interrupt (`0` if the trap is caused by an exception)
408
| 30:5 | r/- | _Reserved_, read as zero
409
| 4:0  | r/w | Trap ID, see <<_neorv32_trap_listing>>
410
|=======================
411
 
412
:sectnums!:
413
===== **`mtval`**
414
 
415
[cols="4,27,>7"]
416
[frame="topbot",grid="none"]
417
|======
418
| 0x343 | **Machine bad address or instruction** | `mtval`
419
3+| Reset value: _UNDEFINED_
420
3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
421
the faulting address (for misaligned/faulting load/stores/fetch) or the faulting instruction itself (for illegal
422
instructions). For interrupts the CSR is set to zero.
423
|======
424
 
425
.Machine bad address or instruction register
426
[cols="^5,^5"]
427
[options="header",grid="rows"]
428
|=======================
429
| Trap cause | `mtval` content
430
| misaligned instruction fetch address or instruction fetch access fault | address of faulting instruction fetch
431
| breakpoint | program counter (= address) of faulting instruction itself
432
| misaligned load address, load access fault, misaligned store address or store access fault | program counter (= address) of faulting instruction itself
433
| illegal instruction | actual instruction word of faulting instruction
434
| anything else including interrupts | _0x00000000_ (always zero)
435
|=======================
436
 
437
[IMPORTAN]
438 64 zero_gravi
The NEORV32 `mtval` CSR is read-only. However, a write access will _NOT_ raise an illegal instruction exception.
439 60 zero_gravi
 
440
:sectnums!:
441
===== **`mip`**
442
 
443
[cols="4,27,>7"]
444
[frame="topbot",grid="none"]
445
|======
446
| 0x344 | **Machine interrupt Pending** | `mip`
447
3+| Reset value: _0x00000000_
448 65 zero_gravi
3+| The `mip` CSR is compatible to the RISC-V specifications and also provides custom extensions. It shows currently _pending_ interrupts.
449 69 zero_gravi
The bits for the standard RISC-V interrupts are read-only. Hence, these interrupts cannot be cleared using the `mip` register and must
450
be cleared/acknowledged within the according interrupt-generating device.
451
The upper 16 bits represent the status of the CPU's fast interrupt request lines (FIRQ). Once triggered, these _have to be cleared_ again by setting
452
the according `mip` bit in the interrupt handler routine to clear the current interrupt request.
453 60 zero_gravi
|======
454
 
455
.Machine interrupt pending register
456
[cols="^1,<3,^1,<5"]
457
[options="header",grid="rows"]
458
|=======================
459
| Bit | Name [C] | R/W | Function
460 69 zero_gravi
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/w | fast interrupt channel 15..0 pending; cleared request by writing 1
461
| 11    | _CSR_MIP_MEIP_                       | r/- | machine _external_ interrupt pending; _cleared by user-defined mechanism_
462
| 7     | _CSR_MIP_MTIP_                       | r/- | machine _timer_ interrupt pending; cleared by incrementing MTIME's time compare register
463
| 3     | _CSR_MIP_MSIP_                       | r/- | machine _software_ interrupt pending; _cleared by user-defined mechanism_
464 60 zero_gravi
|=======================
465
 
466
 
467
<<<
468
// ####################################################################################################################
469
:sectnums:
470 66 zero_gravi
==== Machine Physical Memory Protection CSRs
471 60 zero_gravi
 
472
The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
473
_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
474
protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
475
 
476 70 zero_gravi
[NOTE]
477 60 zero_gravi
If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
478
exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
479
 
480
[IMPORTANT]
481 70 zero_gravi
The RISC-V-compatible NEORV32 physical memory protection only implements the **NAPOT**
482
(naturally aligned power-of-two region) mode yet with a minimal region granularity of 8 bytes.
483 60 zero_gravi
 
484
 
485
:sectnums!:
486
===== **`pmpcfg`**
487
 
488
[cols="4,27,>7"]
489
[frame="topbot",grid="none"]
490
|======
491
| 0x3a0 - 0x3af| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg15`
492
3+| Reset value: _0x00000000_
493
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
494
regions, where each `pmpcfg*` CSR provides configuration bits for four regions. The following bits (for the
495
first PMP configuration entry) are implemented (all remaining bits are always zero and are read-only):
496
|======
497
 
498
.Physical memory protection configuration register entry
499
[cols="^1,^3,^1,<11"]
500
[options="header",grid="rows"]
501
|=======================
502
| Bit | RISC-V name | R/W | Function
503 70 zero_gravi
| 7   | _L_ | r/w | lock bit, can only be cleared by CPU reset
504 60 zero_gravi
| 6:5 | -   | r/- | reserved, read as zero
505
| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
506
| 2   | _X_ | r/w | execute permission
507
| 1   | _W_ | r/w | write permission
508
| 0   | _R_ | r/w | read permission
509
|=======================
510
 
511
 
512
:sectnums!:
513
===== **`pmpaddr`**
514
 
515
[cols="4,27,>7"]
516
[frame="topbot",grid="none"]
517
|======
518 70 zero_gravi
| 0x3b0 - 0x3ef| **Physical memory protection address registers** | `pmpaddr0` - `pmpaddr63`
519 60 zero_gravi
3+| Reset value: _UNDEFINED_
520 70 zero_gravi
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the PMP region's base
521 60 zero_gravi
address and the region size.
522
|======
523
 
524
[NOTE]
525
When configuring PMP make sure to set `pmpaddr*` before activating the according region via
526
`pmpcfg*`. When changing the PMP configuration, deactivate the according region via `pmpcfg*`
527
before modifying `pmpaddr*`.
528
 
529
 
530
<<<
531
// ####################################################################################################################
532
:sectnums:
533 66 zero_gravi
==== (Machine) Counter and Timer CSRs
534 60 zero_gravi
 
535 66 zero_gravi
The (machine) counters and timers are implemented when the `Zicntr` ISA extensions is enabled (default)
536
via the <<_cpu_extension_riscv_zicntr>> generic.
537
 
538 64 zero_gravi
[NOTE]
539 61 zero_gravi
The <<_cpu_cnt_width>> generic defines the total size of the CPU's <<_cycleh>> and <<_instreth>>
540
/ <<_mcycleh>> and <<_minstreth>>
541 64 zero_gravi
counter CSRs (low and high words combined); the time CSRs are not affected by this generic. Note that any
542 61 zero_gravi
configuration with <<_cpu_cnt_width>> less than 64 is not RISC-V compliant.
543 60 zero_gravi
 
544 64 zero_gravi
.Effective CPU counter width (`[m]cycle` & `[m]instret`)
545 60 zero_gravi
[IMPORTANT]
546
If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
547
MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
548 64 zero_gravi
will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in the `CPU`
549
<<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
550 61 zero_gravi
 +
551 64 zero_gravi
If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` CSRs are hardwired to zero
552
and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
553
and always read as zero. This configuration will also set the _SYSINFO_CPU_ZXSCNT_ flag ("small counters") in
554
the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
555 61 zero_gravi
 +
556 64 zero_gravi
If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
557 66 zero_gravi
and any write access to them is ignored.
558 60 zero_gravi
 
559
 
560
:sectnums!:
561
===== **`cycle[h]`**
562
 
563
[cols="4,27,>7"]
564
[frame="topbot",grid="none"]
565
|======
566
| 0xc00 | **Cycle counter - low word** | `cycle`
567
| 0xc80 | **Cycle counter - high word** | `cycleh`
568
3+| Reset value: _UNDEFINED_
569
3+| The `cycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
570
counter. The `cycle[h]` CSR is a read-only shadowed copy of the `mcycle[h]` CSR.
571
|======
572
 
573
 
574
:sectnums!:
575
===== **`time[h]`**
576
 
577
[cols="4,27,>7"]
578
[frame="topbot",grid="none"]
579
|======
580
| 0xc01 | **System time - low word** | `time`
581
| 0xc81 | **System time - high word** | `timeh`
582
3+| Reset value: _UNDEFINED_
583
3+| The `time[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit system
584
time. The system time is either generated by the processor-internal _MTIME_ system timer unit (if _IO_MTIME_EN_ = _true_) or can be provided by an
585
external timer unit via the processor's `mtime_i` signal (if _IO_MTIME_EN_ = _false_).
586
CSR is read-only. Change the system time via the _MTIME_ unit.
587
|======
588
 
589
 
590
:sectnums!:
591
===== **`instret[h]`**
592
 
593
[cols="4,27,>7"]
594
[frame="topbot",grid="none"]
595
|======
596
| 0xc02 | **Instructions-retired counter - low word** | `instret`
597
| 0xc82 | **Instructions-retired counter - high word** | `instreth`
598
3+| Reset value: _UNDEFINED_
599
3+| The `instret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
600
instructions counter. The `instret[h]` CSR is a read-only shadowed copy of the `minstret[h]` CSR.
601
|======
602
 
603
 
604
:sectnums!:
605
===== **`mcycle[h]`**
606
 
607
[cols="4,27,>7"]
608
[frame="topbot",grid="none"]
609
|======
610
| 0xb00 | **Machine cycle counter - low word** | `mcycle`
611
| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
612
3+| Reset value: _UNDEFINED_
613
3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
614 70 zero_gravi
counter. The `mcycle[h]` CSR can also be written when in machine mode and is mirrored to the `cycle[h]` CSR.
615 60 zero_gravi
|======
616
 
617
 
618
:sectnums!:
619
===== **`minstret[h]`**
620
 
621
[cols="4,27,>7"]
622
[frame="topbot",grid="none"]
623
|======
624
| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
625
| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
626
3+| Reset value: _UNDEFINED_
627
3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
628 70 zero_gravi
instructions counter. The `minstret[h]` CSR also be written when in machine mode and is mirrored to the `instret[h]` CSR.
629 60 zero_gravi
|======
630
 
631
 
632
 
633
<<<
634
// ####################################################################################################################
635
:sectnums:
636 66 zero_gravi
==== Hardware Performance Monitors (HPM) CSRs
637 60 zero_gravi
 
638 66 zero_gravi
The hardware performance monitor CSRs are implemented when the `Zihpm` ISA extension is enabled via the
639
<<_cpu_extension_riscv_zihpm>> generic.
640 60 zero_gravi
 
641 66 zero_gravi
The actually implemented hardware performance logic is configured via the <<_hpm_num_cnts>> top entity generic,
642
which defines the number of implemented performance monitors. Note that always all 28 HPM counter and configuration registers
643
(`mhpmcounter*[h]` and `mhpmevent*`) are implemented, but only the actually configured ones are real registers and
644
not hardwired to zero.
645
 
646
[TIP]
647
If trying to access an HPM-related CSR beyond <<_hpm_num_cnts>> **no illegal instruction exception is
648
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
649
 
650 61 zero_gravi
[IMPORTANT]
651 66 zero_gravi
The HPM system only allows machine-mode access. Hence, `hpmcounter*[h]` CSR are not implemented
652 61 zero_gravi
and any access (even) from machine mode will raise an exception. Furthermore, the according bits of <<_mcounteren>>
653
used to configure user-mode access to `hpmcounter*[h]` are hard-wired to zero.
654 60 zero_gravi
 
655 66 zero_gravi
The total counter width of the HPMs can be configured before synthesis via the <<_hpm_cnt_width>> generic (0..64-bit).
656 61 zero_gravi
 
657 60 zero_gravi
[NOTE]
658
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
659 61 zero_gravi
<<_hpm_num_cnts>> generic (0..64-bit). If <<_hpm_num_cnts>> is less than 64, all unused MSB-aligned
660 60 zero_gravi
bits are hardwired to zero.
661
 
662
 
663
:sectnums!:
664
===== **`mhpmevent`**
665
 
666
[cols="4,27,>7"]
667
[frame="topbot",grid="none"]
668
|======
669
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
670
3+| Reset value: _UNDEFINED_
671
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
672 62 zero_gravi
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
673 60 zero_gravi
listed in the table below. If more than one event is selected, the according counter will increment if any of
674
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
675
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
676
at all.
677
|======
678
 
679
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
680
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
681 62 zero_gravi
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
682 60 zero_gravi
 
683
.HPM event selector
684
[cols="^1,<3,^1,<5"]
685
[options="header",grid="rows"]
686
|=======================
687 61 zero_gravi
| Bit | Name [C]               | R/W | Event
688
| 0   | _HPMCNT_EVENT_CY_      | r/w | active clock cycle (not in sleep)
689
| 1   | -                      | r/- | _not implemented, always read as zero_
690
| 2   | _HPMCNT_EVENT_IR_      | r/w | retired instruction
691
| 3   | _HPMCNT_EVENT_CIR_     | r/w | retired compressed instruction
692 60 zero_gravi
| 4   | _HPMCNT_EVENT_WAIT_IF_ | r/w | instruction fetch memory wait cycle (if more than 1 cycle memory latency)
693
| 5   | _HPMCNT_EVENT_WAIT_II_ | r/w | instruction issue pipeline wait cycle (if more than 1 cycle latency), caused by pipelines flushes (like taken branches)
694
| 6   | _HPMCNT_EVENT_WAIT_MC_ | r/w | multi-cycle ALU operation wait cycle
695 61 zero_gravi
| 7   | _HPMCNT_EVENT_LOAD_    | r/w | load operation
696
| 8   | _HPMCNT_EVENT_STORE_   | r/w | store operation
697 60 zero_gravi
| 9   | _HPMCNT_EVENT_WAIT_LS_ | r/w | load/store memory wait cycle (if more than 1 cycle memory latency)
698 61 zero_gravi
| 10  | _HPMCNT_EVENT_JUMP_    | r/w | unconditional jump
699
| 11  | _HPMCNT_EVENT_BRANCH_  | r/w | conditional branch (taken or not taken)
700 60 zero_gravi
| 12  | _HPMCNT_EVENT_TBRANCH_ | r/w | taken conditional branch
701 61 zero_gravi
| 13  | _HPMCNT_EVENT_TRAP_    | r/w | entered trap
702 60 zero_gravi
| 14  | _HPMCNT_EVENT_ILLEGAL_ | r/w | illegal instruction exception
703
|=======================
704
 
705
 
706
:sectnums!:
707
===== **`mhpmcounter[h]`**
708
 
709
[cols="4,27,>7"]
710
[frame="topbot",grid="none"]
711
|======
712
| 0xb03 - 0xb1f | **Machine hardware performance monitor - counter low** | `mhpmcounter3` - `mhpmcounter31`
713
| 0xb83 - 0xb9f | **Machine hardware performance monitor - counter high** | `mhpmcounter3h` - `mhpmcounter31h`
714
3+| Reset value: _UNDEFINED_
715
3+| The `mhpmcounter*[h]` CSRs are compatible to the RISC-V specifications. These CSRs provide the lower/upper 32-
716 61 zero_gravi
bit of arbitrary event counters. The event(s) that trigger an increment of theses counters are selected via the according
717
`mhpmevent*` CSRs bits.
718 60 zero_gravi
|======
719
 
720
 
721
<<<
722
// ####################################################################################################################
723
:sectnums:
724 66 zero_gravi
==== Machine Counter Setup CSRs
725 60 zero_gravi
 
726
:sectnums!:
727
===== **`mcountinhibit`**
728
 
729
[cols="4,27,>7"]
730
[frame="topbot",grid="none"]
731
|======
732
| 0x320 | **Machine counter-inhibit register** | `mcountinhibit`
733
3+| Reset value: _UNDEFINED_
734
3+| The `mcountinhibit` CSR is compatible to the RISC-V specifications. The bits in this register define which
735
counter/timer CSR are allowed to perform an automatic increment. Automatic update is enabled if the
736
according bit in `mcountinhibit` is cleared. The following bits are implemented (all remaining bits are
737
always zero and are read-only).
738
|======
739
 
740
.Machine counter-inhibit register
741
[cols="^1,<3,^1,<5"]
742
[options="header",grid="rows"]
743
|=======================
744
| Bit  | Name [C] | R/W | Event
745
| 0    | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]instret[h]` CSRs will auto-increment with each committed instruction when set
746
| 2    | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]cycle[h]` CSRs will auto-increment with each clock cycle (if CPU is not in sleep state) when set
747 62 zero_gravi
| 3:31 | _CSR_MCOUNTINHIBIT_HPM3_ _: _CSR_MCOUNTINHIBIT_HPM31_ | r/w | the `mhpmcount*[h]` CSRs will auto-increment according to the configured `mhpmevent*` selector
748 60 zero_gravi
|=======================
749
 
750
 
751
<<<
752
// ####################################################################################################################
753
:sectnums:
754 66 zero_gravi
==== Machine Information CSRs
755 60 zero_gravi
 
756 62 zero_gravi
[NOTE]
757
All machine information registers can only be accessed in machine mode and are read-only.
758 60 zero_gravi
 
759
:sectnums!:
760
===== **`mvendorid`**
761
 
762
[cols="4,27,>7"]
763
[frame="topbot",grid="none"]
764
|======
765
| 0xf11 | **Machine vendor ID** | `mvendorid`
766
3+| Reset value: _0x00000000_
767
3+| The `mvendorid` CSR is compatible to the RISC-V specifications. It is read-only and always reads zero.
768
|======
769
 
770
 
771
:sectnums!:
772
===== **`marchid`**
773
 
774
[cols="4,27,>7"]
775
[frame="topbot",grid="none"]
776
|======
777
| 0xf12 | **Machine architecture ID** | `marchid`
778
3+| Reset value: _0x00000013_
779
3+| The `marchid` CSR is compatible to the RISC-V specifications. It is read-only and shows the NEORV32
780
official _RISC-V open-source architecture ID_ (decimal: 19, 32-bit hexadecimal: 0x00000013).
781
|======
782
 
783
 
784
:sectnums!:
785
===== **`mimpid`**
786
 
787
[cols="4,27,>7"]
788
[frame="topbot",grid="none"]
789
|======
790
| 0xf13 | **Machine implementation ID** | `mimpid`
791
3+| Reset value: _HW version number_
792
3+| The `mimpid` CSR is compatible to the RISC-V specifications. It is read-only and shows the version of the
793
NEORV32 as BCD-coded number (example: `mimpid` = _0x01020312_ → 01.02.03.12 → version 1.2.3.12).
794
|======
795
 
796
 
797
:sectnums!:
798
===== **`mhartid`**
799
 
800
[cols="4,27,>7"]
801
[frame="topbot",grid="none"]
802
|======
803
| 0xf14 | **Machine hardware thread ID** | `mhartid`
804
3+| Reset value: _HW_THREAD_ID_ generic
805
3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
806
which is assigned via the CPU's _HW_THREAD_ID_ generic.
807
|======
808
 
809
 
810 62 zero_gravi
:sectnums!:
811
===== **`mconfigptr`**
812 60 zero_gravi
 
813 62 zero_gravi
[cols="4,27,>7"]
814
[frame="topbot",grid="none"]
815
|======
816
| 0xf15 | **Machine configuration pointer register** | `mconfigptr`
817
3+| Reset value: `0x00000000`
818
3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
819
Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
820
**NOTE: Not assigned yet.**
821
|======

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