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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
7 
interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
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11 
**Key Features**
12 
 
13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
29 
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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31 
 
32 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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[IMPORTAN]
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
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since all control signals have defined level.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 0..60 | out | pulse-width modulated channels
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **External Interrupts (<<_processor_interrupts, XIRQ>>)**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **RISC-V Machine-Level <<_processor_interrupts, CPU Interrupts>>**
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), high-active
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), high-active
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), high-active
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|=======================
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120 
 
121 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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126 
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
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130 
[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance. +
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**More information can be found in the user guides' section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
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137 
[TIP]
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Privileged software can determine the actual CPU and processor configuration via the `misa` and the
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<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
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[NOTE]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
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**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
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and do not impact the timing.
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[NOTE]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
161 
 
162 
<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | _none_
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
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from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
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|======
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | false
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
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Note that hart IDs must be unique within a system.
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|======
204 
 
205 
 
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
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See chapter <<_on_chip_debugger_ocd>> for more information.
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|======
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218 
// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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[TIP]
223 
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
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(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
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can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
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239 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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243 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
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3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
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size by approx. 30%. See section <<_c_compressed_instructions>>.
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|======
250 
 
251 
 
252 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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255 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
258 
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
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requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
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requires a different application binary interface (ABI).
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|======
263 
 
264 
 
265 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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268 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
271 
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
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If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
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If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
275 
to DSP slices via the <<_fast_mul_en>> generic.
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See section <<_m_integer_multiplication_and_division>> for more information.
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|======
278 
 
279 
 
280 
:sectnums!:
281 
===== _CPU_EXTENSION_RISCV_U_
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283 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
286 
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
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3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>> for more information.
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|======
290 
 
291 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zbb_
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295 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
298 
| **CPU_EXTENSION_RISCV_Zbb** | _boolean_ | false
299 
3+| Implement the `Zbb` _basic_ bit-manipulation sub-extension when _true_.
300 
See section <<_zbb_basic_bit_manipulation_operations>> for more information.
301 
|======
302 
 
303 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
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See section <<_zfinx_single_precision_floating_point_operations>> for more information.
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|======
314 
 
315 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicsr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
322 
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
323 
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
324 
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
325 
no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
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|======
328 
 
329 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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333 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
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See section <<_zifencei_instruction_stream_synchronization>> for more information.
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|======
341 
 
342 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zmmul_
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346 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
349 
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
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3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
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cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
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|======
353 
 
354 
 
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// ####################################################################################################################
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:sectnums:
357 
==== Extension Options
358 
 
359 
See section <<_instruction_sets_and_extensions>> for more information.
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361 
 
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:sectnums!:
363 
===== _FAST_MUL_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
368 
| **FAST_MUL_EN** | _boolean_ | false
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3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
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iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
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utilization. This generic is only relevant when a hardware multiplier CPU extension is
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enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
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<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
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|======
375 
 
376 
 
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:sectnums!:
378 
===== _FAST_SHIFT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **FAST_SHIFT_EN** | _boolean_ | false
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3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
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more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
386 
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
387 
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
388 
shift-related operations of the <<_zbb_basic_bit_manipulation_operations>> extension.**
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|======
390 
 
391 
 
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:sectnums!:
393 
===== _CPU_CNT_WIDTH_
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395 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_CNT_WIDTH** | _natural_ | 64
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3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
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The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
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Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
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|======
403 
 
404 
 
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:sectnums!:
406 
===== _CPU_IPB_ENTRIES_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
411 
| **CPU_IPB_ENTRIES** | _natural_ | 2
412 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
413 
The value has to be a power of two and has to be greater than zero.
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Long linear sequences of code can benefit from an increased IPB size.
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|======
416 
 
417 
 
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// ####################################################################################################################
419 
:sectnums:
420 
==== Physical Memory Protection (PMP)
421 
 
422 
See section <<_pmp_physical_memory_protection>> for more information.
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:sectnums!:
426 
===== _PMP_NUM_REGIONS_
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428 
[cols="4,4,2"]
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[frame="all",grid="none"]
430 
|======
431 
| **PMP_NUM_REGIONS** | _natural_ | 0
432 
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
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protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
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in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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|======
436 
 
437 
 
438 
:sectnums!:
439 
===== _PMP_MIN_GRANULARITY_
440 
 
441 
[cols="4,4,2"]
442 
[frame="all",grid="none"]
443 
|======
444 
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
445 
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
446 
|======
447 
 
448 
 
449 
// ####################################################################################################################
450 
:sectnums:
451 
==== Hardware Performance Monitors (HPM)
452 
 
453 
See section <<_hpm_hardware_performance_monitors>> for more information.
454 
 
455 
 
456 
:sectnums!:
457 
===== _HPM_NUM_CNTS_
458 
 
459 
[cols="4,4,2"]
460 
[frame="all",grid="none"]
461 
|======
462 
| **HPM_NUM_CNTS** | _natural_ | 0
463 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
464 
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _SYSINFO_CPU_HPM_ flag
465 64 zero_gravi 
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
466 60 zero_gravi 
|======
467 
 
468 
 
469 
:sectnums!:
470 
===== _HPM_CNT_WIDTH_
471 
 
472 
[cols="4,4,2"]
473 
[frame="all",grid="none"]
474 
|======
475 
| **HPM_CNT_WIDTH** | _natural_ | 40
476 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
477 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
478 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
479 
|======
480 
 
481 
 
482 
// ####################################################################################################################
483 
:sectnums:
484 
==== Internal Instruction Memory
485 
 
486 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
487 
 
488 
 
489 
:sectnums!:
490 
===== _MEM_INT_IMEM_EN_
491 
 
492 
[cols="4,4,2"]
493 
[frame="all",grid="none"]
494 
|======
495 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
496 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
497 
|======
498 
 
499 
 
500 
:sectnums!:
501 
===== _MEM_INT_IMEM_SIZE_
502 
 
503 
[cols="4,4,2"]
504 
[frame="all",grid="none"]
505 
|======
506 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
507 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
508 60 zero_gravi 
|======
509 
 
510 
 
511 
// ####################################################################################################################
512 
:sectnums:
513 
==== Internal Data Memory
514 
 
515 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
516 
 
517 
 
518 
:sectnums!:
519 
===== _MEM_INT_DMEM_EN_
520 
 
521 
[cols="4,4,2"]
522 
[frame="all",grid="none"]
523 
|======
524 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
525 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
526 
|======
527 
 
528 
 
529 
:sectnums!:
530 
===== _MEM_INT_DMEM_SIZE_
531 
 
532 
[cols="4,4,2"]
533 
[frame="all",grid="none"]
534 
|======
535 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
536 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
537 60 zero_gravi 
|======
538 
 
539 
 
540 
// ####################################################################################################################
541 
:sectnums:
542 
==== Internal Cache Memory
543 
 
544 
See section <<_processor_internal_instruction_cache_icache>> for more information.
545 
 
546 
 
547 
:sectnums!:
548 
===== _ICACHE_EN_
549 
 
550 
[cols="4,4,2"]
551 
[frame="all",grid="none"]
552 
|======
553 
| **ICACHE_EN** | _boolean_ | false
554 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
555 
and instruction memories there is not point of implementing the i-cache.
556 60 zero_gravi 
|======
557 
 
558 
 
559 
:sectnums!:
560 
===== _ICACHE_NUM_BLOCK_
561 
 
562 
[cols="4,4,2"]
563 
[frame="all",grid="none"]
564 
|======
565 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
566 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
567 63 zero_gravi 
effect when <<_icache_dmem_en>> is false.
568 60 zero_gravi 
|======
569 
 
570 
 
571 
:sectnums!:
572 
===== _ICACHE_BLOCK_SIZE_
573 
 
574 
[cols="4,4,2"]
575 
[frame="all",grid="none"]
576 
|======
577 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
578 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
579 63 zero_gravi 
<<_icache_dmem_en>> is _false_.
580 60 zero_gravi 
|======
581 
 
582 
 
583 
:sectnums!:
584 
===== _ICACHE_ASSOCIATIVITY_
585 
 
586 
[cols="4,4,2"]
587 
[frame="all",grid="none"]
588 
|======
589 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
590 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
591 63 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_dmem_en>> is _false_.
592 60 zero_gravi 
|======
593 
 
594 
 
595 
// ####################################################################################################################
596 
:sectnums:
597 
==== External Memory Interface
598 
 
599 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
600 
 
601 
 
602 
:sectnums!:
603 
===== _MEM_EXT_EN_
604 
 
605 
[cols="4,4,2"]
606 
[frame="all",grid="none"]
607 
|======
608 
| **MEM_EXT_EN** | _boolean_ | false
609 
3+| Implement external bus interface (WISHBONE) when _true_.
610 
|======
611 
 
612 
 
613 
:sectnums!:
614 
===== _MEM_EXT_TIMEOUT_
615 
 
616 
[cols="4,4,2"]
617 
[frame="all",grid="none"]
618 
|======
619 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
620 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
621 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
622 60 zero_gravi 
|======
623 
 
624 
 
625 62 zero_gravi 
:sectnums!:
626 
===== _MEM_EXT_PIPE_MODE_
627 
 
628 
[cols="4,4,2"]
629 
[frame="all",grid="none"]
630 
|======
631 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
632 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
633 
Use _pipelined_ Wishbone protocol when _true_.
634 62 zero_gravi 
|======
635 
 
636 
 
637 
:sectnums!:
638 
===== _MEM_EXT_BIG_ENDIAN_
639 
 
640 
[cols="4,4,2"]
641 
[frame="all",grid="none"]
642 
|======
643 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
644 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
645 62 zero_gravi 
|======
646 
 
647 
 
648 
:sectnums!:
649 
===== _MEM_EXT_ASYNC_RX_
650 
 
651 
[cols="4,4,2"]
652 
[frame="all",grid="none"]
653 
|======
654 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
655 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
656 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
657 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
658 62 zero_gravi 
|======
659 
 
660 
 
661 60 zero_gravi 
// ####################################################################################################################
662 
:sectnums:
663 61 zero_gravi 
==== Stream Link Interface
664 
 
665 
See section <<_stream_link_interface_slink>> for more information.
666 
 
667 
 
668 
:sectnums!:
669 
===== _SLINK_NUM_TX_
670 
 
671 
[cols="4,4,2"]
672 
[frame="all",grid="none"]
673 
|======
674 
| **SLINK_NUM_TX** | _natural_ | 0
675 
3+| Number of TX (send) links to implement. Valid values are 0..8.
676 
|======
677 
 
678 
 
679 
:sectnums!:
680 
===== _SLINK_NUM_RX_
681 
 
682 
[cols="4,4,2"]
683 
[frame="all",grid="none"]
684 
|======
685 
| **SLINK_NUM_RX** | _natural_ | 0
686 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
687 
|======
688 
 
689 
 
690 
:sectnums!:
691 
===== _SLINK_TX_FIFO_
692 
 
693 
[cols="4,4,2"]
694 
[frame="all",grid="none"]
695 
|======
696 
| **SLINK_TX_FIFO** | _natural_ | 1
697 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
698 
|======
699 
 
700 
 
701 
:sectnums!:
702 
===== _SLINK_RX_FIFO_
703 
 
704 
[cols="4,4,2"]
705 
[frame="all",grid="none"]
706 
|======
707 
| **SLINK_RX_FIFO** | _natural_ | 1
708 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
709 
|======
710 
 
711 
 
712 
// ####################################################################################################################
713 
:sectnums:
714 
==== External Interrupt Controller
715 
 
716 
See section <<_external_interrupt_controller_xirq>> for more information.
717 
 
718 
 
719 
:sectnums!:
720 
===== _XIRQ_NUM_CH_
721 
 
722 
[cols="4,4,2"]
723 
[frame="all",grid="none"]
724 
|======
725 
| **XIRQ_NUM_CH** | _natural_ | 0
726 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
727 
|======
728 
 
729 
 
730 
:sectnums!:
731 
===== _XIRQ_TRIGGER_TYPE_
732 
 
733 
[cols="4,4,2"]
734 
[frame="all",grid="none"]
735 
|======
736 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
737 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
738 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
739 61 zero_gravi 
|======
740 
 
741 
 
742 
:sectnums!:
743 
===== _XIRQ_TRIGGER_POLARITY_
744 
 
745 
[cols="4,4,2"]
746 
[frame="all",grid="none"]
747 
|======
748 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
749 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
750 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
751 61 zero_gravi 
|======
752 
 
753 
 
754 
// ####################################################################################################################
755 
:sectnums:
756 60 zero_gravi 
==== Processor Peripheral/IO Modules
757 
 
758 
See section <<_processor_internal_modules>> for more information.
759 
 
760 
 
761 
:sectnums!:
762 
===== _IO_GPIO_EN_
763 
 
764 
[cols="4,4,2"]
765 
[frame="all",grid="none"]
766 
|======
767 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
768 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
769 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
770 
|======
771 
 
772 
 
773 
:sectnums!:
774 
===== _IO_MTIME_EN_
775 
 
776 
[cols="4,4,2"]
777 
[frame="all",grid="none"]
778 
|======
779 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
780 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
781 
See section <<_machine_system_timer_mtime>> for more information.
782 
|======
783 
 
784 
 
785 
:sectnums!:
786 
===== _IO_UART0_EN_
787 
 
788 
[cols="4,4,2"]
789 
[frame="all",grid="none"]
790 
|======
791 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
792 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
793 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
794 
more information.
795 
|======
796 
 
797 
 
798 
:sectnums!:
799 65 zero_gravi 
===== _IO_UART0_RX_FIFO_
800 
 
801 
[cols="4,4,2"]
802 
[frame="all",grid="none"]
803 
|======
804 
| **IO_UART0_RX_FIFO** | _natural_ | 1
805 
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
806 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
807 
more information.
808 
|======
809 
 
810 
 
811 
:sectnums!:
812 
===== _IO_UART0_TX_FIFO_
813 
 
814 
[cols="4,4,2"]
815 
[frame="all",grid="none"]
816 
|======
817 
| **IO_UART0_TX_FIFO** | _natural_ | 1
818 
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
819 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
820 
more information.
821 
|======
822 
 
823 
 
824 
:sectnums!:
825 60 zero_gravi 
===== _IO_UART1_EN_
826 
 
827 
[cols="4,4,2"]
828 
[frame="all",grid="none"]
829 
|======
830 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
831 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
832 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
833 
|======
834 
 
835 
 
836 
:sectnums!:
837 65 zero_gravi 
===== _IO_UART1_RX_FIFO_
838 
 
839 
[cols="4,4,2"]
840 
[frame="all",grid="none"]
841 
|======
842 
| **IO_UART1_RX_FIFO** | _natural_ | 1
843 
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
844 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
845 
more information.
846 
|======
847 
 
848 
 
849 
:sectnums!:
850 
===== _IO_UART1_TX_FIFO_
851 
 
852 
[cols="4,4,2"]
853 
[frame="all",grid="none"]
854 
|======
855 
| **IO_UART1_TX_FIFO** | _natural_ | 1
856 
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
857 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
858 
more information.
859 
|======
860 
 
861 
 
862 
:sectnums!:
863 60 zero_gravi 
===== _IO_SPI_EN_
864 
 
865 
[cols="4,4,2"]
866 
[frame="all",grid="none"]
867 
|======
868 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
869 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
870 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
871 
|======
872 
 
873 
 
874 
:sectnums!:
875 
===== _IO_TWI_EN_
876 
 
877 
[cols="4,4,2"]
878 
[frame="all",grid="none"]
879 
|======
880 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
881 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
882 
See section <<_two_wire_serial_interface_controller_twi>> for
883 
more information.
884 
|======
885 
 
886 
 
887 
:sectnums!:
888 
===== _IO_PWM_NUM_CH_
889 
 
890 
[cols="4,4,2"]
891 
[frame="all",grid="none"]
892 
|======
893 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
894 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
895 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
896 
|======
897 
 
898 
 
899 
:sectnums!:
900 
===== _IO_WDT_EN_
901 
 
902 
[cols="4,4,2"]
903 
[frame="all",grid="none"]
904 
|======
905 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
906 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
907 
information.
908 
|======
909 
 
910 
 
911 
:sectnums!:
912 
===== _IO_TRNG_EN_
913 
 
914 
[cols="4,4,2"]
915 
[frame="all",grid="none"]
916 
|======
917 
| **IO_TRNG_EN** | _boolean_ | false
918 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
919 
|======
920 
 
921 
 
922 
:sectnums!:
923 
===== _IO_CFS_EN_
924 
 
925 
[cols="4,4,2"]
926 
[frame="all",grid="none"]
927 
|======
928 
| **IO_CFS_EN** | _boolean_ | false
929 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
930 
|======
931 
 
932 
 
933 
:sectnums!:
934 
===== _IO_CFS_CONFIG_
935 
 
936 
[cols="4,4,2"]
937 
[frame="all",grid="none"]
938 
|======
939 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
940 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
941 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
942 
|======
943 
 
944 
 
945 
:sectnums!:
946 
===== _IO_CFS_IN_SIZE_
947 
 
948 
[cols="4,4,2"]
949 
[frame="all",grid="none"]
950 
|======
951 
| **IO_CFS_IN_SIZE** | _positive_ | 32
952 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
953 
|======
954 
 
955 
 
956 
:sectnums!:
957 
===== _IO_CFS_OUT_SIZE_
958 
 
959 
[cols="4,4,2"]
960 
[frame="all",grid="none"]
961 
|======
962 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
963 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
964 
|======
965 
 
966 
 
967 
:sectnums!:
968 
===== _IO_NEOLED_EN_
969 
 
970 
[cols="4,4,2"]
971 
[frame="all",grid="none"]
972 
|======
973 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
974 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
975 
See section <<_smart_led_interface_neoled>> for more information.
976 
|======
977 
 
978 
 
979 62 zero_gravi 
:sectnums!:
980 
===== _IO_NEOLED_TX_FIFO_
981 
 
982 
[cols="4,4,2"]
983 
[frame="all",grid="none"]
984 
|======
985 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
986 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
987 
See section <<_smart_led_interface_neoled>> for more information.
988 
|======
989 
 
990 
 
991 
 
992 60 zero_gravi 
<<<
993 
// ####################################################################################################################
994 
:sectnums:
995 
=== Processor Interrupts
996 
 
997 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
998 60 zero_gravi 
 
999 
 
1000 61 zero_gravi 
:sectnums:
1001 
==== RISC-V Standard Interrupts
1002 
 
1003 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
1004 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
1005 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
1006 
<<_traps_exceptions_and_interrupts>> for more information.
1007 60 zero_gravi 
 
1008 61 zero_gravi 
[cols="<3,^2,<11"]
1009 
[options="header",grid="rows"]
1010 
|=======================
1011 
| Top signal | Width | Description
1012 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
1013 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
1014 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
1015 
|=======================
1016 60 zero_gravi 
 
1017 64 zero_gravi 
.Trigger type
1018 62 zero_gravi 
[IMPORTANT]
1019 65 zero_gravi 
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
1020 
by the software (for example by writing to a specifc memory-mapped register). Hence, pending interrupts remain pending
1021 
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
1022 61 zero_gravi 
 
1023 
 
1024 
:sectnums:
1025 
==== Platform External Interrupts
1026 
 
1027 
[cols="<3,^2,<11"]
1028 
[options="header",grid="rows"]
1029 
|=======================
1030 
| Top signal | Width | Description
1031 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
1032 
|=======================
1033 
 
1034 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
1035 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1036 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1037 
 
1038 64 zero_gravi 
.Trigger type
1039 
[IMPORTANT]
1040 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1041 64 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
1042 65 zero_gravi 
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
1043 
_fast interrupt request_ (see below).
1044 61 zero_gravi 
 
1045 
 
1046 
:sectnums:
1047 
==== NEORV32-Specific Fast Interrupt Requests
1048 
 
1049 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1050 65 zero_gravi 
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
1051 61 zero_gravi 
interfaces to signal "available incoming data" or "ready to send new data").
1052 60 zero_gravi 
 
1053 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1054 
the according FIRQ priority; 0 = highest, 15 = lowest):
1055 60 zero_gravi 
 
1056 
.NEORV32 fast interrupt channel mapping
1057 
[cols="^1,<2,<7"]
1058 
[options="header",grid="rows"]
1059 
|=======================
1060 
| Channel | Source | Description
1061 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1062 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1063 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1064 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1065 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1066 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1067 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1068 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1069 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1070 65 zero_gravi 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
1071 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
1072 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
1073 62 zero_gravi 
| 12:15   | - | _reserved_, will never fire
1074 60 zero_gravi 
|=======================
1075 
 
1076 64 zero_gravi 
.Trigger type
1077 
[IMPORTANT]
1078 65 zero_gravi 
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
1079 
by the software (for example by writing to a specifc memory-mapped register). Hence, pending interrupts remain pending
1080 
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
1081 60 zero_gravi 
 
1082 
 
1083 64 zero_gravi 
 
1084 60 zero_gravi 
<<<
1085 
// ####################################################################################################################
1086 
:sectnums:
1087 
=== Address Space
1088 
 
1089 65 zero_gravi 
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
1090 
By default, this address space is divided into five main regions:
1091 60 zero_gravi 
 
1092 65 zero_gravi 
1. **Instruction address space** - memory address space for instructions (=code) and constants.
1093 
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
1094 
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
1095 
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
1096 
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
1097 61 zero_gravi 
internal _bootloader memory_ (BOOTLDROM).
1098 65 zero_gravi 
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
1099 
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
1100 60 zero_gravi 
 
1101 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1102 
image::address_space.png[900]
1103 60 zero_gravi 
 
1104 
 
1105 
:sectnums:
1106 
==== CPU Data and Instruction Access
1107 
 
1108 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1109 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1110 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1111 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1112 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1113 
setup a modified von-Neumann architecture.
1114 
 
1115 
.Processor-internal bus architecture
1116 
image::neorv32_bus.png[1300]
1117 
 
1118 
[NOTE]
1119 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1120 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1121 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1122 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1123 
accesses.
1124 
 
1125 
[IMPORTANT]
1126 
Please note that all processor-internal components including the peripheral/IO devices can also be
1127 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1128 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1129 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1130 
PMP system (see <<_machine_physical_memory_protection>>).
1131 
 
1132 61 zero_gravi 
 
1133 60 zero_gravi 
:sectnums:
1134 61 zero_gravi 
==== Address Space Layout
1135 
 
1136 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1137 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1138 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1139 
`rtl/core/neorv32_package.vhd`:
1140 
 
1141 
[source,vhdl]
1142 
----
1143 
-- Architecture Configuration ----------------------------------------------------
1144 
-- ----------------------------------------------------------------------------------
1145 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1146 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1147 
----
1148 
 
1149 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1150 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1151 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1152 
are _aligned_ to a 4-byte boundary.
1153 
 
1154 
[NOTE]
1155 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1156 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1157 65 zero_gravi 
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
1158 61 zero_gravi 
hardware sources.
1159 
 
1160 
 
1161 
:sectnums:
1162 60 zero_gravi 
==== Physical Memory Attributes
1163 
 
1164 61 zero_gravi 
The processor setup defines fixed attributes for the four processor-internal address space regions.
1165 
Accessing a memory region in a way that violates any of these attributes will raise an according
1166 
access exception..
1167 60 zero_gravi 
 
1168 65 zero_gravi 
* `r` - read access (from CPU data access interface, "loads")
1169 
* `w` - write access (from CPU data access interface, "stores")
1170 
* `x` - execute access (from CPU instruction fetch interface)
1171 
* `a` - atomic access (from CPU data access interface)
1172 
* `8` - byte (8-bit)-accessible (when writing)
1173 
* `16` - half-word (16-bit)-accessible (when writing)
1174 
* `32` - word (32-bit)-accessible (when writing)
1175 60 zero_gravi 
 
1176 61 zero_gravi 
[NOTE]
1177 65 zero_gravi 
Read accesses (loads and instruction fetches) can always access data in
1178 
word, half-word (for instruction fetch only if `C` extension is enabled)
1179 
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
1180 60 zero_gravi 
 
1181 65 zero_gravi 
[TIP]
1182 
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
1183 
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
1184 
provided using the RISC-V <<_machine_physical_memory_protection>>.
1185 
 
1186 60 zero_gravi 
[cols="^1,^2,^2,^3,^2"]
1187 
[options="header",grid="rows"]
1188 
|=======================
1189 65 zero_gravi 
| # | Region                | Base address | Size        | Attributes
1190 
| 5 | IO/peripheral devices | 0xfffffe00   | 512 bytes   | `r/w/a/32`
1191 
| 4 | On-chip debugger      | 0xfffff800   | 512 bytes   | `r/w/x/32`
1192 
| 3 | Bootloader ROM        | 0xffff0000   | up to 32kB  | `r/x/a`
1193 
| 2 | DMEM                  | 0x80000000   | up to "2GB" | `r/w/x/a/8/16/32`
1194 
| 1 | IMEM                  | 0x00000000   | up to 2GB   | `r/w/x/a/8/16/32`
1195 60 zero_gravi 
|=======================
1196 
 
1197 
 
1198 
:sectnums:
1199 61 zero_gravi 
==== Memory Configuration
1200 60 zero_gravi 
 
1201 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1202 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1203 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1204 
the internal ones. The figure below show some exemplary memory configurations.
1205 60 zero_gravi 
 
1206 61 zero_gravi 
.Exemplary memory configurations
1207 
image::neorv32_memory_configurations.png[800]
1208 60 zero_gravi 
 
1209 61 zero_gravi 
:sectnums!:
1210 
===== Internal Memories
1211 
 
1212 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1213 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1214 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1215 
 
1216 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1217 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1218 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1219 
implemented.
1220 
 
1221 61 zero_gravi 
[TIP]
1222 
The default processor setup uses only _internal_ memories.
1223 60 zero_gravi 
 
1224 61 zero_gravi 
[NOTE]
1225 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1226 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1227 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1228 
any access to the "dead address space" in between will raise an exception that can be caught
1229 
by the runtime environment.
1230 60 zero_gravi 
 
1231 61 zero_gravi 
:sectnums!:
1232 
===== External Memories
1233 
 
1234 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1235 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1236 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1237 
 
1238 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1239 
via the processor's bus interface to external components:
1240 
 
1241 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1242 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1243 
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1244 
 
1245 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1246 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1247 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1248 
memory system.
1249 60 zero_gravi 
 
1250 61 zero_gravi 
[NOTE]
1251 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1252 
the internal peripheral address space will trigger a bus access fault exception.
1253 60 zero_gravi 
 
1254 
 
1255 61 zero_gravi 
:sectnums:
1256 
==== Boot Configuration
1257 
 
1258 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1259 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1260 
 
1261 
.NEORV32 boot configurations
1262 
image::neorv32_boot_configurations.png[800]
1263 
 
1264 
[NOTE]
1265 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1266 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1267 
 
1268 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1269 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1270 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1271 
 
1272 
[NOTE]
1273 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1274 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1275 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1276 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1277 
store it to external _data_ memory and transfers CPU control to that.
1278 
 
1279 
:sectnums!:
1280 
===== Indirect Boot
1281 
 
1282 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
1283 
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1284 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1285 
 
1286 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
1287 
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
1288 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1289 
RAM so the bootloader can write the actual executable to it.
1290 
 
1291 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1292 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1293 
write the executable to the processor-external memory.
1294 
 
1295 
:sectnums!:
1296 
===== Direct Boot
1297 
 
1298 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
1299 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1300 
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
1301 
in order to provide an executable _in_ memory.
1302 
 
1303 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1304 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
1305 
 
1306 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1307 
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
1308 
 
1309 
 
1310 
 
1311 60 zero_gravi 
<<<
1312 
// ####################################################################################################################
1313 
:sectnums:
1314 
=== Processor-Internal Modules
1315 
 
1316 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1317 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1318 
system implements an internal reset generator and a global clock generator/divider.
1319 
 
1320 
**Internal Reset Generator**
1321 
 
1322 65 zero_gravi 
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
1323 60 zero_gravi 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1324 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1325 
modules to ensure a clean system reset state.
1326 
 
1327 
The hardware reset signal of the processor can either be
1328 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1329 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1330 
clock cycles.
1331 
 
1332 
**Internal Clock Divider**
1333 
 
1334 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1335 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1336 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1337 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1338 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1339 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1340 
power.
1341 
 
1342 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1343 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1344 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1345 
from the top entity's `clk_i` signal.
1346 
 
1347 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1348 
[grid="rows"]
1349 
|=======================
1350 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1351 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1352 
|=======================
1353 
 
1354 
**Peripheral / IO Devices**
1355 
 
1356 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1357 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1358 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1359 
library abstract the specific memory layout for the user.
1360 
 
1361 
[IMPORTANT]
1362 64 zero_gravi 
The base address of each component/module has to be aligned to the
1363 
total size of the module's occupied address space! The occupied address space
1364 
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
1365 
 
1366 
[IMPORTANT]
1367 60 zero_gravi 
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
1368 
load/store access fault exception is triggered.
1369 
 
1370 
[IMPORTANT]
1371 
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1372 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1373 
Processor-internal memories as well as modules connected to the external memory interface can still
1374 
be written with a byte-wide granularity.
1375 
 
1376 
[TIP]
1377 
You should use the provided core software library to interact with the peripheral devices. This
1378 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1379 
register and register bit accesses.
1380 
 
1381 
[TIP]
1382 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1383 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1384 
application start-up code `crt0.S`.
1385 
 
1386 64 zero_gravi 
**Interrupts of Processor-Internal Modules**
1387 
 
1388 
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
1389 
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
1390 
interrupt lines are triggered by a "one-shot" signal (hich for exactly one cycle) and _do not_ require any
1391 
explicit acknowledgment.
1392 
 
1393 60 zero_gravi 
**Nomenclature for the Peripheral / IO Devices Listing**
1394 
 
1395 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1396 64 zero_gravi 
according device including the implemented control and status bits. C-language code can directly interact with these
1397 
registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
1398 
interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the
1399 
main processor core library include file `sw/lib/include/neorv32.h`.
1400 60 zero_gravi 
 
1401 64 zero_gravi 
The naming scheme of these low-level hardware access structs is `NEORV32_.`.
1402 
 
1403 
.Low-level hardware access example in C using the pre-defined `struct`
1404 
[source,c]
1405 
----
1406 
// Read from SYSINFO "CLK" register
1407 
uint32_t temp = NEORV32_SYSINFO.CLK;
1408 
----
1409 
 
1410 
The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]".
1411 60 zero_gravi 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1412 
available:
1413 
 
1414 
* `r/w` registers / bits can be read and written
1415 
* `r/-` registers / bits are read-only; any write access to them has no effect
1416 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1417 
 
1418 
[TIP]
1419 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1420 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1421 
write zero to them to keep compatible with future extension.
1422 
 
1423 
[TIP]
1424 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1425 
written. When reading data from a write-only register the result is undefined.
1426 
 
1427 
 
1428 
include::soc_imem.adoc[]
1429 
 
1430 
include::soc_dmem.adoc[]
1431 
 
1432 
include::soc_bootrom.adoc[]
1433 
 
1434 
include::soc_icache.adoc[]
1435 
 
1436 
include::soc_wishbone.adoc[]
1437 
 
1438 61 zero_gravi 
include::soc_slink.adoc[]
1439 
 
1440 60 zero_gravi 
include::soc_gpio.adoc[]
1441 
 
1442 
include::soc_wdt.adoc[]
1443 
 
1444 
include::soc_mtime.adoc[]
1445 
 
1446 
include::soc_uart.adoc[]
1447 
 
1448 
include::soc_spi.adoc[]
1449 
 
1450 
include::soc_twi.adoc[]
1451 
 
1452 
include::soc_pwm.adoc[]
1453 
 
1454 
include::soc_trng.adoc[]
1455 
 
1456 
include::soc_cfs.adoc[]
1457 
 
1458 
include::soc_neoled.adoc[]
1459 
 
1460 61 zero_gravi 
include::soc_xirq.adoc[]
1461 
 
1462 60 zero_gravi 
include::soc_sysinfo.adoc[]
1463 
 
1464 
 

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