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==== System Configuration Information Memory (SYSINFO)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_sysinfo.vhd |
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| Software driver file(s): | neorv32.h |
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| Top entity port:         | none |
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| Configuration generics:  | * | most of the top's configuration generics
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| CPU interrupts:          | none |
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|=======================
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**Theory of Operation**
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The SYSINFO allows the application software to determine the setting of most of the processor's top entity
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generics that are related to processor/SoC configuration. All registers of this unit are read-only.
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This device is always implemented – regardless of the actual hardware configuration. The bootloader as well
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as the NEORV32 software runtime environment require information from this device (like memory layout
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and default clock speed) for correct operation.
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.SYSINFO register map
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|=======================
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| Address | Name [C] | Function
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| `0xffffffe0` | _SYSINFO_CLK_         | clock speed in Hz (via top's <<_clock_frequency>> generic)
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| `0xffffffe4` | _SYSINFO_CPU_         | specific CPU configuration (see <<_sysinfo_cpu_configuration>>)
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| `0xffffffe8` | _SYSINFO_FEATURES_    | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
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| `0xffffffec` | _SYSINFO_CACHE_       | cache configuration information (see <<_sysinfo_cache_configuration>>)
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| `0xfffffff0` | _SYSINFO_ISPACE_BASE_ | instruction address space base (via package's `ispace_base_c` constant)
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| `0xfffffff4` | _SYSINFO_IMEM_SIZE_   | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic)
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| `0xfffffff8` | _SYSINFO_DSPACE_BASE_ | data address space base (via package's `sdspace_base_c` constant)
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| `0xfffffffc` | _SYSINFO_DMEM_SIZE_   | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic)
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|=======================
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===== SYSINFO - CPU Configuration
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._SYSINFO_CPU_ bits
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|=======================
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| Bit | Name [C] | Function
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| `0`  | _SYSINFO_CPU_ZICSR_     | `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
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| `1`  | _SYSINFO_CPU_ZIFENCEI_  | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
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| `2`  | _SYSINFO_CPU_ZMMUL_     | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
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| `3`  | _SYSINFO_CPU_ZBB_       | `Zbb` extension (`B` sub-extension) available when set (via top's <<_cpu_extension_riscv_zbb>> generic)
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| `5`  | _SYSINFO_CPU_ZFINX_     | `Zfinx` extension (`F` sub-/alternative-extension) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
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| `6`  | _SYSINFO_CPU_ZXSCNT_    | Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
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| `7`  | _SYSINFO_CPU_ZXNOCNT_   | Custom extension - _NO_ CPU counters: `[m]cycle` & `[m]instret` CSRs are NOT available at all when set (via top's <<_cpu_cnt_width>> generic)
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| `8`  | _SYSINFO_CPU_PMP_       | `PMP` (physical memory protection) extension available when set (via top's <<_>> generic)
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| `9`  | _SYSINFO_CPU_HPM_       | `HPM` (hardware performance monitors) extension available when set (via top's <<_>> generic)
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| `10` | _SYSINFO_CPU_DEBUGMODE_ | RISC-V CPU `debug_mode` available when set (via top's <<_>> generic)
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| `30  | _SYSINFO_CPU_FASTMUL_   | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
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| `31` | _SYSINFO_CPU_FASTSHIFT_ | fast shifts available when set (via top's <<_fast_shift_en>> generic)
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|=======================
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===== SYSINFO - SoC Configuration
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._SYSINFO_FEATURES_ bits
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|=======================
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| Bit | Name [C] | Function
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| `0`  | _SYSINFO_FEATURES_BOOTLOADER_       | set if the processor-internal bootloader is implemented (via top's <<_int_bootloader_en>> generic)
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| `1`  | _SYSINFO_FEATURES_MEM_EXT_          | set if the external Wishbone bus interface is implemented (via top's <<_mem_ext_en>> generic)
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| `2`  | _SYSINFO_FEATURES_MEM_INT_IMEM_     | set if the processor-internal DMEM implemented (via top's <<_mem_int_dmem_en>> generic)
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| `3`  | _SYSINFO_FEATURES_MEM_INT_DMEM_     | set if the processor-internal IMEM is implemented (via top's <<_mem_int_imem_en>> generic)
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| `4`  | _SYSINFO_FEATURES_MEM_EXT_ENDIAN_   | set if external bus interface uses BIG-endian byte-order (via top's <<_mem_ext_big_endian>> generic)
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| `5`  | _SYSINFO_FEATURES_ICACHE_           | set if processor-internal instruction cache is implemented (via top's <<_icache_en>> generic)
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| `14` | _SYSINFO_FEATURES_HW_RESET_         | set if on-chip debugger implemented (via top's <<_on_chip_debugger_en>> generic)
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| `15` | _SYSINFO_FEATURES_HW_RST_           | set if a dedicated hardware reset of all core registers is implemented (via package's `dedicated_reset_c` constant)
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| `16` | _SYSINFO_FEATURES_IO_GPIO_          | set if the GPIO is implemented (via top's <<_io_gpio_en>> generic)
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| `17` | _SYSINFO_FEATURES_IO_MTIME_         | set if the MTIME is implemented (via top's <<_io_mtime_en>> generic)
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| `18` | _SYSINFO_FEATURES_IO_UART0_         | set if the primary UART0 is implemented (via top's <<_io_uart0_en>> generic)
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| `19` | _SYSINFO_FEATURES_IO_SPI_           | set if the SPI is implemented (via top's <<_io_spi_en>> generic)
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| `20` | _SYSINFO_FEATURES_IO_TWI_           | set if the TWI is implemented (via top's <<_io_twi_en>> generic)
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| `21` | _SYSINFO_FEATURES_IO_PWM_           | set if the PWM is implemented (via top's <<_io_pwm_en>> generic)
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| `22` | _SYSINFO_FEATURES_IO_WDT_           | set if the WDT is implemented (via top's <<_io_wdt_en>> generic)
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| `23` | _SYSINFO_FEATURES_IO_CFS_           | set if the custom functions subsystem is implemented (via top's <<_io_cfs_en>> generic)
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| `24` | _SYSINFO_FEATURES_IO_TRNG_          | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic)
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| `25` | _SYSINFO_FEATURES_IO_SLINK_         | set if the SLINK is implemented (via top's <<_slink_num_tx>> and/or <<_slink_num_rx>> generics)
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| `26` | _SYSINFO_FEATURES_IO_UART1_         | set if the secondary UART1 is implemented (via top's <<_io_uart1_en>> generic)
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| `27` | _SYSINFO_FEATURES_IO_NEOLED_        | set if the NEOLED is implemented (via top's <<_io_neoled_en>> generic)
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|=======================
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===== SYSINFO - Cache Configuration
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[NOTE]
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Bit fields in this register are set to all-zero if the according cache is not implemented.
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._SYSINFO_CACHE_ bits
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|=======================
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| Bit      | Name [C] | Function
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| `3:0`    | _SYSINFO_CACHE_IC_BLOCK_SIZE_3_ : _SYSINFO_CACHE_IC_BLOCK_SIZE_0_       | _log2_(i-cache block size in bytes), via top's <<_icache_block_size>> generic
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| `7:4`    | _SYSINFO_CACHE_IC_NUM_BLOCKS_3_ : _SYSINFO_CACHE_IC_NUM_BLOCKS_0_       | _log2_(i-cache number of cache blocks), via top's <<_icache_num_blocks>> generic
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| `11:9`   | _SYSINFO_CACHE_IC_ASSOCIATIVITY_3_ : _SYSINFO_CACHE_IC_ASSOCIATIVITY_0_ | _log2_(i-cache associativity), via top's <<_icache_associativity>> generic
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| `15:12`  | _SYSINFO_CACHE_IC_REPLACEMENT_3_ : _SYSINFO_CACHE_IC_REPLACEMENT_0_     | i-cache replacement policy (`0001` = LRU if associativity > 0)
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| `32:16`  | -                                                                       | zero, reserved for d-cache
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|=======================

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