Subversion Repositories neorv32

<<<

:sectnums:

== Legal

// ####################################################################################################################

:sectnums!:

=== License

**BSD 3-Clause License**

Copyright (c) 2022, Stephan Nolting. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that

the following conditions are met:

. Redistributions of source code must retain the above copyright notice, this list of conditions and the

following disclaimer.

. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and

the following disclaimer in the documentation and/or other materials provided with the distribution.

. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or

promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

ARISING IN ANY WAY OUT OF

==========================

**The NEORV32 RISC-V Processor** +

By Dipl.-Ing. Stephan Nolting +

Contact: stnolting@gmail.com +

HQ: https://github.com/stnolting/neorv32

==========================

<<<

// ####################################################################################################################

:sectnums!:

=== Proprietary Notice

* "GitHub" is a Subsidiary of Microsoft Corporation.

* "Vivado" and "Artix" are trademarks of Xilinx Inc.

* "AXI", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.

* "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.

* "Quartus Prime" and "Cyclone" are trademarks of Intel Corporation.

* "iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.

* "Windows" is a trademark of Microsoft Corporation.

* "Tera Term" copyright by T. Teranishi.

* "NeoPixel" is a trademark of Adafruit Industries.

* Images/figures made with _Microsoft Power Point_.

* Timing diagrams made with _WaveDrom Editor_.

* Documentation proudly made with `asciidoctor`.

* All further/unreferenced products belong to their according copyright holders.

PDF icons from https://www.flaticon.com and made by

link:https://www.freepik.com[Freepik], link:https://www.flaticon.com/authors/good-ware[Good Ware],

link:https://www.flaticon.com/authors/pixel-perfect[Pixel perfect], link:https://www.flaticon.com/authors/vectors-market[Vectors Market]

:sectnums!:

=== Disclaimer

This project is released under the BSD 3-Clause license. No copyright infringement

intended. Other implied or used projects might have different licensing – see their documentation to get more information.

:sectnums!:

=== Limitation of Liability for External Links

This document contains links to the websites of third parties ("external links"). As the content of these websites

is not under our control, we cannot assume any liability for such external content. In all cases, the provider of

information of the linked websites is liable for the content and accuracy of the information provided. At the

point in time when the links were placed, no infringements of the law were recognizable to us. As soon as an

infringement of the law becomes known to us, we will immediately remove the link in question.

:sectnums!:

=== Citing

[NOTE]

This is an open-source project that is free of charge. Use this project in any way you like

(as long as it complies to the permissive license). Please quote it appropriately. 👍

.Contributors ❤️

[NOTE]

Please add as many https://github.com/stnolting/neorv32/graphs/contributors[contributors] as possible to the `author` field. +

This project would not be where it is without them.

If you are using the NEORV32 or parts of the project in some kind of publication, please cite it as follows:

.BibTeX

[source]

----

@misc{nolting22,

  author       = {Nolting, S. and ...},

  title        = {The NEORV32 RISC-V Processor},

  year         = {2022},

  publisher    = {GitHub},

  journal      = {GitHub repository},

  howpublished = {\url{https://github.com/stnolting/neorv32}}

}

----

.DOI

[TIP]

This project also provides a _digital object identifier_ provided by https://zenodo.org[zenodo]:

https://doi.org/10.5281/zenodo.5018888[image:https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg[title='zenodo']]

:sectnums!:

=== Acknowledgments

**A big shout-out to the community and all https://github.com/stnolting/neorv32/graphs/contributors[contributors],

who helped improving this project! ❤️**

https://riscv.org[RISC-V] - instruction sets want to be free!

Continuous integration provided by https://github.com/features/actions[GitHub Actions] and powered by https://github.com/ghdl/ghdl[GHDL].