OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [docs/] [legal.adoc] - Blame information for rev 65

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 zero_gravi
<<<
2
:sectnums:
3
== Legal
4
 
5
// ####################################################################################################################
6
:sectnums!:
7
=== License
8
 
9
**BSD 3-Clause License**
10
 
11
Copyright (c) 2021, Stephan Nolting. All rights reserved.
12
 
13
Redistribution and use in source and binary forms, with or without modification, are permitted provided that
14
the following conditions are met:
15
 
16
. Redistributions of source code must retain the above copyright notice, this list of conditions and the
17
following disclaimer.
18
. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
19
the following disclaimer in the documentation and/or other materials provided with the distribution.
20
. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or
21
promote products derived from this software without specific prior written permission.
22
 
23
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32
ARISING IN ANY WAY OUT OF
33
 
34
 
35
==========================
36
**The NEORV32 RISC-V Processor** +
37
Copyright (c) 2021, by Dipl.-Ing. Stephan Nolting. All rights reserved. +
38
HQ: https://github.com/stnolting/neorv32 +
39
Contact: stnolting@gmail.com +
40
_made in Hanover, Germany_
41
==========================
42
 
43
 
44
<<<
45
// ####################################################################################################################
46
:sectnums!:
47
=== Proprietary Notice
48
 
49
* "GitHub" is a Subsidiary of Microsoft Corporation.
50
* "Vivado" and "Artix" are trademarks of Xilinx Inc.
51 61 zero_gravi
* "AXI", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.
52 60 zero_gravi
* "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.
53
* "Quartus Prime" and "Cyclone" are trademarks of Intel Corporation.
54
* "iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
55
* "Windows" is a trademark of Microsoft Corporation.
56
* "Tera Term" copyright by T. Teranishi.
57
* Timing diagrams made with WaveDrom Editor.
58
* "NeoPixel" is a trademark of Adafruit Industries.
59
* Documentation made with `asciidoctor`.
60
 
61
PDF icons from https://www.flaticon.com and made by
62
link:https://www.freepik.com[Freepik], link:https://www.flaticon.com/authors/good-ware[Good Ware],
63
link:https://www.flaticon.com/authors/pixel-perfect[Pixel perfect], link:https://www.flaticon.com/authors/vectors-market[Vectors Market]
64
 
65
 
66
:sectnums!:
67
=== Disclaimer
68
 
69
This project is released under the BSD 3-Clause license. No copyright infringement
70
intended. Other implied or used projects might have different licensing – see their documentation to get more information.
71
 
72
 
73
:sectnums!:
74
=== Limitation of Liability for External Links
75
 
76
This document contains links to the websites of third parties ("external links"). As the content of these websites
77
is not under our control, we cannot assume any liability for such external content. In all cases, the provider of
78
information of the linked websites is liable for the content and accuracy of the information provided. At the
79
point in time when the links were placed, no infringements of the law were recognizable to us. As soon as an
80
infringement of the law becomes known to us, we will immediately remove the link in question.
81
 
82
 
83
:sectnums!:
84
=== Citing
85
 
86
If you are using the NEORV32 or parts of the project in some kind of publication, please cite it as follows:
87
 
88 62 zero_gravi
.Contributors ❤️
89
[NOTE]
90
Please add as many https://github.com/stnolting/neorv32/graphs/contributors[contributors] as possible to the `authors` field 😉. +
91
This project would not be where it is without them. +
92
Full names can be found in the repository's https://github.com/stnolting/neorv32/blob/master/.mailmap[`.mailmap`].
93
 
94 60 zero_gravi
.BibTeX
95
[source]
96
----
97
@misc{nolting20,
98
  author       = {Nolting, S.},
99
  title        = {The NEORV32 RISC-V Processor},
100
  year         = {2020},
101
  publisher    = {GitHub},
102
  journal      = {GitHub repository},
103
  howpublished = {\url{https://github.com/stnolting/neorv32}}
104
}
105
----
106
 
107 62 zero_gravi
.DOI
108 61 zero_gravi
[TIP]
109 65 zero_gravi
This project also provides a _digital object identifier_ provided by https://zenodo.org[zenodo]:
110
https://doi.org/10.5281/zenodo.5018888[image:https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg[title='zenodo']]
111 61 zero_gravi
 
112
 
113 60 zero_gravi
:sectnums!:
114
=== Acknowledgments
115
 
116
**A big shoutout to all https://github.com/stnolting/neorv32/graphs/contributors[contributors],
117
who helped improving this project! ❤️**
118
 
119
https://riscv.org[RISC-V] - instruction sets want to be free!
120
 
121
 
122 61 zero_gravi
=== Impressum (Imprint)
123 60 zero_gravi
 
124 61 zero_gravi
See https://github.com/stnolting/neorv32/blob/master/docs/impressum.md[`docs/impressum.md`].
125 60 zero_gravi
 
126
 
127 61 zero_gravi
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.