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zero_gravi |
-- #################################################################################################
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # ********************************************************************************************* #
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-- # Main data and address ALU. Include comparator unit. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_alu is
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zero_gravi |
generic (
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CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
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);
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zero_gravi |
port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- co-processor interface --
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
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-- status --
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wait_o : out std_ulogic -- busy due to iterative processing units
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);
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end neorv32_cpu_alu;
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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-- operands --
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zero_gravi |
signal opa, opb, opc : std_ulogic_vector(data_width_c-1 downto 0);
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zero_gravi |
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-- results --
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signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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signal sub_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cmp_equal : std_ulogic;
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signal cmp_less : std_ulogic;
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-- shifter --
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signal shift_cmd : std_ulogic;
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signal shift_cmd_ff : std_ulogic;
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signal shift_start : std_ulogic;
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signal shift_run : std_ulogic;
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signal shift_cnt : std_ulogic_vector(4 downto 0);
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signal shift_sreg : std_ulogic_vector(data_width_c-1 downto 0);
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-- co-processor interface --
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signal cp_cmd_ff : std_ulogic;
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signal cp_run : std_ulogic;
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signal cp_start : std_ulogic;
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signal cp_busy : std_ulogic;
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signal cp_rb_ff0 : std_ulogic;
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signal cp_rb_ff1 : std_ulogic;
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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zero_gravi |
input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
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zero_gravi |
begin
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-- opa (first ALU input operand) --
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zero_gravi |
if (ctrl_i(ctrl_alu_opa_mux_msb_c) = '0') then
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if (ctrl_i(ctrl_alu_opa_mux_lsb_c) = '0') then
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opa <= rs1_i;
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else
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opa <= pc2_i;
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end if;
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else
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opa <= csr_i;
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end if;
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zero_gravi |
-- opb (second ALU input operand) --
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zero_gravi |
if (ctrl_i(ctrl_alu_opb_mux_msb_c) = '0') then
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if (ctrl_i(ctrl_alu_opb_mux_lsb_c) = '0') then
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opb <= rs2_i;
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else
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opb <= imm_i;
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end if;
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else
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opb <= rs1_i;
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end if;
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zero_gravi |
-- opc (second operand for comparison (and SUB)) --
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if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
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opc <= imm_i;
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else
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opc <= rs2_i;
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end if;
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end process input_op_mux;
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-- Comparator Unit ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- less than (x < y) --
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
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cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
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zero_gravi |
cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
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zero_gravi |
sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
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-- equal (x = y) --
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cmp_equal <= '1' when (rs1_i = opc) else '0';
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-- output for branch condition evaluation -
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cmp_o(alu_cmp_equal_c) <= cmp_equal;
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cmp_o(alu_cmp_less_c) <= cmp_less;
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-- Binary Adder ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
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add_o <= add_res; -- direct output
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-- Iterative Shifter Unit -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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shifter_unit: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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zero_gravi |
shift_sreg <= (others => '0');
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zero_gravi |
shift_cnt <= (others => '0');
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shift_cmd_ff <= '0';
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elsif rising_edge(clk_i) then
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shift_cmd_ff <= shift_cmd;
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if (shift_start = '1') then -- trigger new shift
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shift_sreg <= opa; -- shift operand
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zero_gravi |
shift_cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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zero_gravi |
elsif (shift_run = '1') then -- running shift
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shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shift_sreg <= shift_sreg(shift_sreg'left-1 downto 0) & '0';
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shift_sreg <= (shift_sreg(shift_sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shift_sreg(shift_sreg'left downto 1);
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end if;
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end if;
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end if;
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end process shifter_unit;
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-- is shift operation? --
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shift_cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
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shift_start <= '1' when (shift_cmd = '1') and (shift_cmd_ff = '0') else '0';
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-- shift operation running? --
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zero_gravi |
shift_run <= '1' when (or_all_f(shift_cnt) = '1') or (shift_start = '1') else '0';
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zero_gravi |
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-- Coprocessor Interface ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp_interface: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cp_cmd_ff <= '0';
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cp_busy <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= '0';
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elsif rising_edge(clk_i) then
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zero_gravi |
if (CPU_EXTENSION_RISCV_M = true) then -- FIXME add second cp (floating point stuff?)
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zero_gravi |
cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= cp_rb_ff0;
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if (cp_start = '1') then
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cp_busy <= '1';
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elsif ((cp0_valid_i or cp1_valid_i) = '1') then
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cp_busy <= '0';
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cp_rb_ff0 <= '1';
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end if;
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else -- no co-processors implemented
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cp_cmd_ff <= '0';
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cp_busy <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= '0';
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end if;
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end if;
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end process cp_interface;
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-- is co-processor operation? --
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cp_start <= '1' when (ctrl_i(ctrl_cp_use_c) = '1') and (cp_cmd_ff = '0') else '0';
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-- co-processor operation running? --
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cp_run <= cp_busy or cp_start;
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg)
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begin
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case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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9 |
zero_gravi |
when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modifications only)
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2 |
zero_gravi |
when alu_cmd_xor_c => alu_res <= opa xor opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
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zero_gravi |
when alu_cmd_sub_c => alu_res <= sub_res;
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when alu_cmd_add_c => alu_res <= add_res;
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zero_gravi |
when alu_cmd_shift_c => alu_res <= shift_sreg;
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when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
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3 |
zero_gravi |
when others => alu_res <= (others => '0'); -- undefined
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2 |
zero_gravi |
end case;
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end process alu_function_mux;
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-- ALU Result -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wait_o <= shift_run or cp_run; -- wait until iterative units have completed
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res_o <= (cp0_data_i or cp1_data_i) when (cp_rb_ff1 = '1') else alu_res; -- FIXME
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end neorv32_cpu_cpu_rtl;
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