Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - CPU Control >>                                                                   #

-- # ********************************************************************************************* #

-- # CPU operation is split into a fetch engine (responsible for fetching an decompressing instr-  #

-- # uctions), an execute engine (responsible for actually executing the instructions), an inter-  #

-- # rupt and exception handling controller and the RISC-V status and control registers (CSRs).    #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_cpu_control is

  generic (

    -- General --

    CLOCK_FREQUENCY              : natural := 0; -- clock frequency of clk_i in Hz

    HART_ID                      : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID

    BOOTLOADER_USE               : boolean := true;   -- implement processor-internal bootloader?

    CSR_COUNTERS_USE             : boolean := true;   -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?

    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?

    -- Memory configuration: Instruction memory --

    MEM_ISPACE_BASE              : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space

    MEM_ISPACE_SIZE              : natural := 8*1024; -- total size of instruction memory space in byte

    MEM_INT_IMEM_USE             : boolean := true;   -- implement processor-internal instruction memory

    MEM_INT_IMEM_SIZE            : natural := 8*1024; -- size of processor-internal instruction memory in bytes

    MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM

    -- Memory configuration: Data memory --

    MEM_DSPACE_BASE              : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space

    MEM_DSPACE_SIZE              : natural := 4*1024; -- total size of data memory space in byte

    MEM_INT_DMEM_USE             : boolean := true;   -- implement processor-internal data memory

    MEM_INT_DMEM_SIZE            : natural := 4*1024; -- size of processor-internal data memory in bytes

    -- Memory configuration: External memory interface --

    MEM_EXT_USE                  : boolean := false;  -- implement external memory bus interface?

    -- Processor peripherals --

    IO_GPIO_USE                  : boolean := true;   -- implement general purpose input/output port unit (GPIO)?

    IO_MTIME_USE                 : boolean := true;   -- implement machine system timer (MTIME)?

    IO_UART_USE                  : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?

    IO_SPI_USE                   : boolean := true;   -- implement serial peripheral interface (SPI)?

    IO_TWI_USE                   : boolean := true;   -- implement two-wire interface (TWI)?

    IO_PWM_USE                   : boolean := true;   -- implement pulse-width modulation unit (PWM)?

    IO_WDT_USE                   : boolean := true;   -- implement watch dog timer (WDT)?

    IO_CLIC_USE                  : boolean := true;   -- implement core local interrupt controller (CLIC)?

    IO_TRNG_USE                  : boolean := true;   -- implement true random number generator (TRNG)?

    IO_DEVNULL_USE               : boolean := true    -- implement dummy device (DEVNULL)?

  );

  port (

    -- global control --

    clk_i         : in  std_ulogic; -- global clock, rising edge

    rstn_i        : in  std_ulogic; -- global reset, low-active, async

    ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus

    -- status input --

    alu_wait_i    : in  std_ulogic; -- wait for ALU

    bus_wait_i    : in  std_ulogic; -- wait for bus

    -- data input --

    instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction

    cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status

    alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result

    -- data output --

    imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate

    fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch

    curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)

    next_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)

    -- csr data interface --

    csr_wdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data

    csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data

    -- external interrupt --

    clic_irq_i    : in  std_ulogic; -- CLIC interrupt request

    mtime_irq_i   : in  std_ulogic; -- machine timer interrupt

    -- system time input from MTIME --

    time_i        : in  std_ulogic_vector(63 downto 0); -- current system time

    -- bus access exceptions --

    mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0);  -- memory address register

    ma_instr_i    : in  std_ulogic; -- misaligned instruction address

    ma_load_i     : in  std_ulogic; -- misaligned load data address

    ma_store_i    : in  std_ulogic; -- misaligned store data address

    be_instr_i    : in  std_ulogic; -- bus error on instruction access

    be_load_i     : in  std_ulogic; -- bus error on load data access

    be_store_i    : in  std_ulogic; -- bus error on store data access

    bus_busy_i    : in  std_ulogic  -- bus unit is busy

  );

end neorv32_cpu_control;

architecture neorv32_cpu_control_rtl of neorv32_cpu_control is

  -- instruction fetch enginge --

  type fetch_engine_state_t is (IFETCH_RESET, IFETCH_0, IFETCH_1, IFETCH_2, IFETCH_3);

  type fetch_engine_t is record

    state           : fetch_engine_state_t;

    state_nxt       : fetch_engine_state_t;

    i_buf           : std_ulogic_vector(33 downto 0);

    i_buf_nxt       : std_ulogic_vector(33 downto 0);

    i_buf2          : std_ulogic_vector(33 downto 0);

    i_buf2_nxt      : std_ulogic_vector(33 downto 0);

    ci_reg          : std_ulogic_vector(17 downto 0);

    ci_reg_nxt      : std_ulogic_vector(17 downto 0);

    i_buf_state     : std_ulogic_vector(01 downto 0);

    i_buf_state_nxt : std_ulogic_vector(01 downto 0);

    pc_real         : std_ulogic_vector(data_width_c-1 downto 0);

    pc_real_add     : std_ulogic_vector(data_width_c-1 downto 0);

    pc_fetch        : std_ulogic_vector(data_width_c-1 downto 0);

    pc_fetch_add    : std_ulogic_vector(data_width_c-1 downto 0);

    ci_return       : std_ulogic;

    ci_return_nxt   : std_ulogic;

    reset           : std_ulogic;

    bus_err_ack     : std_ulogic;

    bus_reset       : std_ulogic;

  end record;

  signal fetch_engine : fetch_engine_t;

  -- pre-decoder --

  signal ci_instr32 : std_ulogic_vector(31 downto 0);

  signal ci_illegal : std_ulogic;

  -- instrucion prefetch buffer (IPB) --

  type ipb_t is record

    wdata  : std_ulogic_vector(34 downto 0);

    rdata  : std_ulogic_vector(34 downto 0);

    waddr  : std_ulogic_vector(31 downto 0);

    raddr  : std_ulogic_vector(31 downto 0);

    status : std_ulogic;

    free   : std_ulogic;

    avail  : std_ulogic;

    we     : std_ulogic;

    re     : std_ulogic;

    clear  : std_ulogic;

  end record;

  signal ipb : ipb_t;

  -- instruction execution engine --

  type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, STORE, LOAD, LOADSTORE_0, LOADSTORE_1, CSR_ACCESS);

  type execute_engine_t is record

    state        : execute_engine_state_t;

    state_nxt    : execute_engine_state_t;

    state_prev   : execute_engine_state_t;

    i_reg        : std_ulogic_vector(31 downto 0);

    i_reg_nxt    : std_ulogic_vector(31 downto 0);

    is_ci        : std_ulogic; -- current instruction is de-compressed instruction

    is_ci_nxt    : std_ulogic;

    is_jump      : std_ulogic; -- current instruction is jump instruction

    is_jump_nxt  : std_ulogic;

    branch_taken : std_ulogic; -- branch condition fullfilled

    pc           : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction

    pc_nxt       : std_ulogic_vector(data_width_c-1 downto 0);

    next_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed

    last_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction

    sleep        : std_ulogic; -- CPU in sleep mode

    sleep_nxt    : std_ulogic; -- CPU in sleep mode

  end record;

  signal execute_engine : execute_engine_t;

  -- trap controller --

  type trap_ctrl_t is record

    exc_buf       : std_ulogic_vector(exception_width_c-1 downto 0);

    exc_fire      : std_ulogic; -- set if there is a valid source in the exception buffer

    irq_buf       : std_ulogic_vector(interrupt_width_c-1 downto 0);

    irq_fire      : std_ulogic; -- set if there is a valid source in the interrupt buffer

    exc_ack       : std_ulogic; -- acknowledge all exceptions

    irq_ack       : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt

    irq_ack_nxt   : std_ulogic_vector(interrupt_width_c-1 downto 0);

    cause         : std_ulogic_vector(data_width_c-1 downto 0); -- trap ID (for "mcause")

    cause_nxt     : std_ulogic_vector(data_width_c-1 downto 0);

    exc_src       : std_ulogic_vector(exception_width_c-1 downto 0);

    --

    env_start     : std_ulogic; -- start trap handler env

    env_start_ack : std_ulogic; -- start of trap handler acknowledged

    env_end       : std_ulogic; -- end trap handler env

    --

    instr_be      : std_ulogic; -- instruction fetch bus error

    instr_ma      : std_ulogic; -- instruction fetch misaligned address

    instr_il      : std_ulogic; -- illegal instruction

    env_call      : std_ulogic;

    break_point   : std_ulogic;

  end record;

  signal trap_ctrl : trap_ctrl_t;

  -- CPU control signals --

  signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);

  -- fast bus access --

  signal bus_fast_ir : std_ulogic;

  -- RISC-V control and status registers (CSRs) --

  type csr_t is record

    we           : std_ulogic; -- write enable

    we_nxt       : std_ulogic;

    re           : std_ulogic; -- read enable

    re_nxt       : std_ulogic;

    mstatus_mie  : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)

    mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)

    mip_msip     : std_ulogic; -- mip.MSIP: machine software interrupt pending (R/W)

    mie_msie     : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)

    mie_meie     : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)

    mie_mtie     : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)

    mepc         : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)

    mcause       : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)

    mtvec        : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W)

    mtval        : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)

    mscratch     : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)

    mcycle       : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit

    minstret     : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit

    mcycleh      : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)

    minstreth    : std_ulogic_vector(31 downto 0); -- minstreth (R/W)

  end record;

  signal csr : csr_t;

  signal mcycle_msb   : std_ulogic;

  signal minstret_msb : std_ulogic;

  -- illegal instruction check --

  signal illegal_instruction : std_ulogic;

  signal illegal_register    : std_ulogic; -- only for E-extension

  signal illegal_compressed  : std_ulogic; -- only fir C-extension

begin

-- ****************************************************************************************************************************

-- Instruction Fetch

-- ****************************************************************************************************************************

  -- Compressed Instructions Recoding -------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_cpu_decompressor_inst_true:

  if (CPU_EXTENSION_RISCV_C = true) generate

    neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor

    port map (

      -- instruction input --

      ci_instr16_i => fetch_engine.ci_reg(15 downto 0), -- compressed instruction input

      -- instruction output --

      ci_illegal_o => ci_illegal, -- is an illegal compressed instruction

      ci_instr32_o => ci_instr32  -- 32-bit decompressed instruction

    );

  end generate;

  neorv32_cpu_decompressor_inst_false:

  if (CPU_EXTENSION_RISCV_C = false) generate

    ci_instr32 <= (others => '0');

    ci_illegal <= '0';

  end generate;

  -- Fetch Engine FSM Sync ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- for registers that require a specific reset state --

  fetch_engine_fsm_sync_rst: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      fetch_engine.state <= IFETCH_RESET;

    elsif rising_edge(clk_i) then

      if (fetch_engine.reset = '1') then

        fetch_engine.state <= IFETCH_RESET;

      else

        fetch_engine.state <= fetch_engine.state_nxt;

      end if;

    end if;

  end process fetch_engine_fsm_sync_rst;

  -- for registers that DO NOT require a specific reset state --

  fetch_engine_fsm_sync: process(clk_i)

  begin

    if rising_edge(clk_i) then

      if (fetch_engine.state = IFETCH_RESET) then

        fetch_engine.pc_fetch  <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC

        fetch_engine.pc_real   <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC

      else

        fetch_engine.pc_real   <= std_ulogic_vector(unsigned(fetch_engine.pc_real(data_width_c-1 downto 1) & '0')  + unsigned(fetch_engine.pc_real_add(data_width_c-1 downto 1) & '0'));

        fetch_engine.pc_fetch  <= std_ulogic_vector(unsigned(fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0') + unsigned(fetch_engine.pc_fetch_add(data_width_c-1 downto 1) & '0'));

      end if;

      --

      fetch_engine.i_buf       <= fetch_engine.i_buf_nxt;

      fetch_engine.i_buf2      <= fetch_engine.i_buf2_nxt;

      fetch_engine.i_buf_state <= fetch_engine.i_buf_state_nxt;

      --

      fetch_engine.ci_reg      <= fetch_engine.ci_reg_nxt;

      fetch_engine.ci_return   <= fetch_engine.ci_return_nxt;

    end if;

  end process fetch_engine_fsm_sync;

  -- Fetch Engine FSM Comb ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  fetch_engine_fsm_comb: process(fetch_engine, execute_engine, csr, ipb, instr_i, bus_wait_i, bus_busy_i, ci_instr32, be_instr_i, ma_instr_i)

  begin

    -- arbiter defaults --

    fetch_engine.state_nxt       <= fetch_engine.state;

    fetch_engine.pc_fetch_add    <= (others => '0');

    fetch_engine.pc_real_add     <= (others => '0');

    bus_fast_ir                  <= '0';

    fetch_engine.i_buf_nxt       <= fetch_engine.i_buf;

    fetch_engine.i_buf2_nxt      <= fetch_engine.i_buf2;

    fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state;

    fetch_engine.ci_reg_nxt      <= fetch_engine.ci_reg;

    fetch_engine.ci_return_nxt   <= fetch_engine.ci_return;

    fetch_engine.bus_err_ack     <= '0';

    fetch_engine.bus_reset       <= '0';

    -- instruction prefetch buffer interface --

    ipb.we    <= '0';

    ipb.clear <= '0';

    ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);

    ipb.waddr <= fetch_engine.pc_real(data_width_c-1 downto 1) & '0';

    -- state machine --

    case fetch_engine.state is

      when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC

      -- ------------------------------------------------------------

        fetch_engine.i_buf_state_nxt <= (others => '0');

        fetch_engine.ci_return_nxt   <= '0';

        fetch_engine.bus_reset       <= '1'; -- reset bus unit

        ipb.clear                    <= '1'; -- clear instruction prefetch buffer

        fetch_engine.state_nxt       <= IFETCH_0;

      when IFETCH_0 => -- output current PC to bus system, request 32-bit word

      -- ------------------------------------------------------------

        if (bus_busy_i = '0') and (execute_engine.state /= LOAD) and (execute_engine.state /= STORE) and

                                  (execute_engine.state /= LOADSTORE_0) and (execute_engine.state /= LOADSTORE_1) then -- wait if execute engine is using bus unit

          bus_fast_ir            <= '1'; -- fast instruction fetch request (output PC to bus.address)

          fetch_engine.state_nxt <= IFETCH_1;

        end if;

      when IFETCH_1 => -- store data from memory to buffer(s)

      -- ------------------------------------------------------------

        fetch_engine.i_buf_nxt  <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info

        if (bus_wait_i = '0') then -- wait for bus response

          fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;

          fetch_engine.i_buf_state_nxt(1) <= fetch_engine.i_buf_state(0);

          fetch_engine.state_nxt          <= IFETCH_2;

        end if;

        fetch_engine.i_buf_state_nxt(0) <= '1';

        if (be_instr_i = '1') or (ma_instr_i = '1') then -- any fetch exception?

          fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them

        end if;

      when IFETCH_2 => -- construct instruction and issue

      -- ------------------------------------------------------------

        if (fetch_engine.i_buf_state(1) = '1') then

          if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned

            fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00);

            ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);

            if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed

              if (ipb.free = '1') then -- free entry in buffer?

                ipb.we                    <= '1';

                fetch_engine.pc_real_add  <= std_ulogic_vector(to_unsigned(4, data_width_c));

                fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));

                fetch_engine.state_nxt    <= IFETCH_0;

              end if;

            else -- compressed

              fetch_engine.pc_fetch_add  <= std_ulogic_vector(to_unsigned(2, data_width_c));

              fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing

              fetch_engine.state_nxt     <= IFETCH_3;

            end if;

          else -- 16-bit aligned

            fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(31 downto 16);

            ipb.wdata <= fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);

            if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed

              if (ipb.free = '1') then -- free entry in buffer?

                ipb.we                    <= '1';

                fetch_engine.pc_real_add  <= std_ulogic_vector(to_unsigned(4, data_width_c));

                fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));

                fetch_engine.state_nxt    <= IFETCH_0;

              end if;

            else -- compressed

              fetch_engine.pc_fetch_add  <= std_ulogic_vector(to_unsigned(2, data_width_c));

              fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing

              fetch_engine.state_nxt     <= IFETCH_3;

            end if;

          end if;

        else

         fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));

         fetch_engine.state_nxt    <= IFETCH_0;

        end if;

      when IFETCH_3 => -- additional cycle for issueing decompressed instructions

      -- ------------------------------------------------------------

        if (ipb.free = '1') then -- free entry in buffer?

          ipb.we    <= '1';

          ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32;

          fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));

          if (fetch_engine.ci_return = '0') then

            fetch_engine.state_nxt <= IFETCH_0;

          else

            fetch_engine.state_nxt <= IFETCH_2;

          end if;

        end if;

      when others => -- undefined

      -- ------------------------------------------------------------

        fetch_engine.state_nxt <= IFETCH_RESET;

    end case;

  end process fetch_engine_fsm_comb;

-- ****************************************************************************************************************************

-- Instruction Prefetch Buffer

-- ****************************************************************************************************************************

  -- Instruction Prefetch Buffer Stage ------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  instr_prefetch_buffer: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      ipb.status <= '0';

      ipb.rdata  <= (others => '0');

      ipb.raddr  <= (others => '0');

    elsif rising_edge(clk_i) then

      if (ipb.clear = '1') then

        ipb.status <= '0';

      elsif (ipb.we = '1') then

        ipb.status <= '1';

      elsif (ipb.re = '1') then

        ipb.status <= '0';

      end if;

      if (ipb.we = '1') then

        ipb.rdata <= ipb.wdata;

        ipb.raddr <= ipb.waddr;

      end if;

    end if;

  end process instr_prefetch_buffer;

  -- status --

  ipb.free  <= not ipb.status;

  ipb.avail <= ipb.status;

-- ****************************************************************************************************************************

-- Instruction Execution

-- ****************************************************************************************************************************

  -- Immediate Generator --------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  imm_gen: process(clk_i)

  begin

    if rising_edge(clk_i) then

      case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is

        when opcode_store_c => -- S-immediate

          imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);

          imm_o(00)           <= execute_engine.i_reg(07);

        when opcode_branch_c => -- B-immediate

          imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(11)           <= execute_engine.i_reg(07);

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);

          imm_o(00)           <= '0';

        when opcode_lui_c | opcode_auipc_c => -- U-immediate

          imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);

          imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);

          imm_o(11 downto 00) <= (others => '0');

        when opcode_jal_c => -- J-immediate

          imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);

          imm_o(11)           <= execute_engine.i_reg(20);

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);

          imm_o(00)           <= '0';

        when opcode_syscsr_c => -- CSR-immediate

          imm_o(31 downto 05) <= (others => '0');

          imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15);

        when others => -- I-immediate

          imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension

          imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);

          imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);

          imm_o(00)           <= execute_engine.i_reg(20);

      end case;

    end if;

  end process imm_gen;

  -- Branch Condition Check -----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  branch_check: process(execute_engine.i_reg, cmp_i)

  begin

    case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is

      when funct3_beq_c => -- branch if equal

        execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);

      when funct3_bne_c => -- branch if not equal

        execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);

      when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)

        execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);

      when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)

        execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);

      when others => -- undefined

        execute_engine.branch_taken <= '0';

    end case;

  end process branch_check;

  -- Execute Engine FSM Sync ----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- for registers that require a specific reset state --

  execute_engine_fsm_sync_rst: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      if (BOOTLOADER_USE = true) then -- boot from bootloader ROM

        execute_engine.pc      <= boot_base_c(data_width_c-1 downto 1) & '0';

        execute_engine.last_pc <= boot_base_c(data_width_c-1 downto 1) & '0';

      else -- boot from IMEM

        execute_engine.pc      <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0';

        execute_engine.last_pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0';

      end if;

      execute_engine.state      <= SYS_WAIT;

      execute_engine.state_prev <= SYS_WAIT;

      --

      execute_engine.sleep <= '0';

    elsif rising_edge(clk_i) then

      execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';

      if (execute_engine.state = EXECUTE) then

        execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';

      end if;

      execute_engine.state      <= execute_engine.state_nxt;

      execute_engine.state_prev <= execute_engine.state;

      --

      execute_engine.sleep <= execute_engine.sleep_nxt;

    end if;

  end process execute_engine_fsm_sync_rst;

  -- for registers that DO NOT require a specific reset state --

  execute_engine_fsm_sync: process(clk_i)

  begin

    if rising_edge(clk_i) then

      execute_engine.i_reg   <= execute_engine.i_reg_nxt;

      execute_engine.is_ci   <= execute_engine.is_ci_nxt;

      execute_engine.is_jump <= execute_engine.is_jump_nxt;

      -- control signals --

      ctrl <= ctrl_nxt;

    end if;

  end process execute_engine_fsm_sync;

  -- PC output --

  execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 2) when (execute_engine.is_ci = '1') else

                            std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 4);

  fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';

  curr_pc_o  <= execute_engine.pc(data_width_c-1 downto 1) & '0';

  next_pc_o  <= execute_engine.next_pc(data_width_c-1 downto 1) & '0';

  -- CPU Control Bus Output -----------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir)