Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - CPU Control >>                                                                   #

-- # ********************************************************************************************* #

-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an    #

-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction    #

-- # words) and an execute engine (responsible for actually executing the instructions), a trap    #

-- # handling controller and the RISC-V status and control register set (CSRs) including the       #

-- # hardware performance monitor counters.                                                        #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library neorv32;

use neorv32.neorv32_package.all;

entity neorv32_cpu_control is

  generic (

    -- General --

    HW_THREAD_ID                 : natural; -- hardware thread id (32-bit)

    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0); -- cpu boot address

    CPU_DEBUG_ADDR               : std_ulogic_vector(31 downto 0); -- cpu debug mode start address

    -- RISC-V CPU Extensions --

    CPU_EXTENSION_RISCV_A        : boolean; -- implement atomic extension?

    CPU_EXTENSION_RISCV_C        : boolean; -- implement compressed extension?

    CPU_EXTENSION_RISCV_E        : boolean; -- implement embedded RF extension?

    CPU_EXTENSION_RISCV_M        : boolean; -- implement muld/div extension?

    CPU_EXTENSION_RISCV_U        : boolean; -- implement user mode extension?

    CPU_EXTENSION_RISCV_Zbb      : boolean; -- implement basic bit-manipulation sub-extension?

    CPU_EXTENSION_RISCV_Zfinx    : boolean; -- implement 32-bit floating-point extension (using INT reg!)

    CPU_EXTENSION_RISCV_Zicsr    : boolean; -- implement CSR system?

    CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?

    CPU_EXTENSION_RISCV_Zmmul    : boolean; -- implement multiply-only M sub-extension?

    CPU_EXTENSION_RISCV_DEBUG    : boolean; -- implement CPU debug mode?

    -- Extension Options --

    CPU_CNT_WIDTH                : natural; -- total width of CPU cycle and instret counters (0..64)

    CPU_IPB_ENTRIES              : natural; -- entries is instruction prefetch buffer, has to be a power of 2

    -- Physical memory protection (PMP) --

    PMP_NUM_REGIONS              : natural; -- number of regions (0..64)

    PMP_MIN_GRANULARITY          : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes

    -- Hardware Performance Monitors (HPM) --

    HPM_NUM_CNTS                 : natural; -- number of implemented HPM counters (0..29)

    HPM_CNT_WIDTH                : natural  -- total size of HPM counters (0..64)

  );

  port (

    -- global control --

    clk_i         : in  std_ulogic; -- global clock, rising edge

    rstn_i        : in  std_ulogic; -- global reset, low-active, async

    ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus

    -- status input --

    alu_idone_i   : in  std_ulogic; -- ALU iterative operation done

    bus_i_wait_i  : in  std_ulogic; -- wait for bus

    bus_d_wait_i  : in  std_ulogic; -- wait for bus

    excl_state_i  : in  std_ulogic; -- atomic/exclusive access lock status

    -- data input --

    instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction

    cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status

    alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result

    rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1

    -- data output --

    imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate

    fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch

    curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)

    csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data

    -- FPU interface --

    fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags

    -- debug mode (halt) request --

    db_halt_req_i : in  std_ulogic;

    -- interrupts (risc-v compliant) --

    msw_irq_i     : in  std_ulogic; -- machine software interrupt

    mext_irq_i    : in  std_ulogic; -- machine external interrupt

    mtime_irq_i   : in  std_ulogic; -- machine timer interrupt

    -- fast interrupts (custom) --

    firq_i        : in  std_ulogic_vector(15 downto 0);

    -- system time input from MTIME --

    time_i        : in  std_ulogic_vector(63 downto 0); -- current system time

    -- physical memory protection --

    pmp_addr_o    : out pmp_addr_if_t; -- addresses

    pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs

    -- bus access exceptions --

    mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0);  -- memory address register

    ma_instr_i    : in  std_ulogic; -- misaligned instruction address

    ma_load_i     : in  std_ulogic; -- misaligned load data address

    ma_store_i    : in  std_ulogic; -- misaligned store data address

    be_instr_i    : in  std_ulogic; -- bus error on instruction access

    be_load_i     : in  std_ulogic; -- bus error on load data access

    be_store_i    : in  std_ulogic  -- bus error on store data access

  );

end neorv32_cpu_control;

architecture neorv32_cpu_control_rtl of neorv32_cpu_control is

  -- CPU core counter ([m]cycle, [m]instret) width - high/low parts --

  constant cpu_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH < 32), CPU_CNT_WIDTH, 32));

  constant cpu_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH > 32), CPU_CNT_WIDTH-32, 0));

  -- HPM counter width - high/low parts --

  constant hpm_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH < 32), HPM_CNT_WIDTH, 32));

  constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH-32, 0));

  -- instruction fetch engine --

  type fetch_engine_state_t is (IFETCH_REQUEST, IFETCH_ISSUE);

  type fetch_engine_t is record

    state       : fetch_engine_state_t;

    state_nxt   : fetch_engine_state_t;

    state_prev  : fetch_engine_state_t;

    restart     : std_ulogic;

    restart_nxt : std_ulogic;

    pc          : std_ulogic_vector(data_width_c-1 downto 0);

    pc_nxt      : std_ulogic_vector(data_width_c-1 downto 0);

    reset       : std_ulogic;

    bus_err_ack : std_ulogic;

  end record;

  signal fetch_engine : fetch_engine_t;

  -- instruction prefetch buffer (FIFO) interface --

  type ipb_t is record

    wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data

    we    : std_ulogic; -- trigger write

    free  : std_ulogic; -- free entry available?

    clear : std_ulogic; -- clear all entries

    --

    rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data

    re    : std_ulogic; -- read enable

    avail : std_ulogic; -- data available?

  end record;

  signal ipb : ipb_t;

  -- pre-decoder --

  signal ci_instr16 : std_ulogic_vector(15 downto 0);

  signal ci_instr32 : std_ulogic_vector(31 downto 0);

  signal ci_illegal : std_ulogic;

  -- instruction issue engine --

  type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);

  type issue_engine_t is record

    state     : issue_engine_state_t;

    state_nxt : issue_engine_state_t;

    align     : std_ulogic;

    align_nxt : std_ulogic;

    buf       : std_ulogic_vector(2+15 downto 0);

    buf_nxt   : std_ulogic_vector(2+15 downto 0);

  end record;

  signal issue_engine : issue_engine_t;

  -- instruction issue interface --

  type cmd_issue_t is record

    data  : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction

    valid : std_ulogic; -- data word is valid when set

  end record;

  signal cmd_issue : cmd_issue_t;

  -- instruction decoding helper logic --

  type decode_aux_t is record

    alu_immediate   : std_ulogic;

    is_atomic_lr    : std_ulogic;

    is_atomic_sc    : std_ulogic;

    is_float_op     : std_ulogic;

    sys_env_cmd     : std_ulogic_vector(11 downto 0);

    is_m_mul        : std_ulogic;

    is_m_div        : std_ulogic;

    is_bitmanip_imm : std_ulogic;

    is_bitmanip_reg : std_ulogic;

  end record;

  signal decode_aux : decode_aux_t;

  -- instruction execution engine --

  type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT, BRANCH,

                                  FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);

  type execute_engine_t is record

    state        : execute_engine_state_t;

    state_nxt    : execute_engine_state_t;

    state_prev   : execute_engine_state_t;

    --

    i_reg        : std_ulogic_vector(31 downto 0);

    i_reg_nxt    : std_ulogic_vector(31 downto 0);

    i_reg_last   : std_ulogic_vector(31 downto 0); -- last executed instruction

    --

    is_ci        : std_ulogic; -- current instruction is de-compressed instruction

    is_ci_nxt    : std_ulogic;

    --

    branch_taken : std_ulogic; -- branch condition fulfilled

    pc           : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction

    pc_mux_sel   : std_ulogic; -- source select for PC update

    pc_we        : std_ulogic; -- PC update enabled

    next_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed

    next_pc_inc  : std_ulogic_vector(data_width_c-1 downto 0); -- increment to get next PC

    last_pc      : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction

    --

    sleep        : std_ulogic; -- CPU in sleep mode

    sleep_nxt    : std_ulogic;

    branched     : std_ulogic; -- instruction fetch was reset

    branched_nxt : std_ulogic;

  end record;

  signal execute_engine : execute_engine_t;

  -- trap controller --

  type trap_ctrl_t is record

    exc_buf       : std_ulogic_vector(exception_width_c-1 downto 0);

    exc_fire      : std_ulogic; -- set if there is a valid source in the exception buffer

    irq_buf       : std_ulogic_vector(interrupt_width_c-1 downto 0);

    irq_fire      : std_ulogic; -- set if there is a valid source in the interrupt buffer

    exc_ack       : std_ulogic; -- acknowledge all exceptions

    cause         : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR

    cause_nxt     : std_ulogic_vector(6 downto 0);

    db_irq_fire   : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer

    db_irq_en     : std_ulogic; -- set if IRQs are allowed in debug mode

    --

    env_start     : std_ulogic; -- start trap handler env

    env_start_ack : std_ulogic; -- start of trap handler acknowledged

    env_end       : std_ulogic; -- end trap handler env

    --

    instr_be      : std_ulogic; -- instruction fetch bus error

    instr_ma      : std_ulogic; -- instruction fetch misaligned address

    instr_il      : std_ulogic; -- illegal instruction

    env_call      : std_ulogic;

    break_point   : std_ulogic;

  end record;

  signal trap_ctrl : trap_ctrl_t;

  -- CPU main control bus --

  signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);

  -- fast instruction fetch access --

  signal bus_fast_ir : std_ulogic;

  -- RISC-V control and status registers (CSRs) --

  type pmp_ctrl_t     is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);

  type pmp_addr_t     is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);

  type pmp_ctrl_rd_t  is array (0 to 63) of std_ulogic_vector(7 downto 0);

  type mhpmevent_t    is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);

  type mhpmcnt_t      is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0);

  type mhpmcnt_nxt_t  is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0);

  type mhpmcnt_ovfl_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(0 downto 0);

  type mhpmcnt_rd_t   is array (0 to 29) of std_ulogic_vector(31 downto 0);

  type csr_t is record

    addr              : std_ulogic_vector(11 downto 0); -- csr address

    we                : std_ulogic; -- csr write enable

    we_nxt            : std_ulogic;

    wdata             : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data

    rdata             : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data

    --

    mstatus_mie       : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)

    mstatus_mpie      : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)

    mstatus_mpp       : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode

    --

    mie_msie          : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)

    mie_meie          : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)

    mie_mtie          : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)

    mie_firqe         : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)

    --

    mcounteren_cy     : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode

    mcounteren_tm     : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode

    mcounteren_ir     : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode

    --

    mcountinhibit_cy  : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h]

    mcountinhibit_ir  : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]

    mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]

    --

    privilege         : std_ulogic_vector(1 downto 0); -- hart's current privilege mode

    privilege_rd      : std_ulogic_vector(1 downto 0); -- hart's current privilege mode (effective)

    priv_m_mode       : std_ulogic; -- CPU in M-mode

    priv_u_mode       : std_ulogic; -- CPU in u-mode

    --

    mepc              : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)

    mcause            : std_ulogic_vector(5 downto 0); -- mcause: machine trap cause (R/W)

    mtvec             : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00

    mtval             : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W)

    --

    mhpmevent         : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)

    --

    mscratch          : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)

    --

    mcycle            : std_ulogic_vector(31 downto 0); -- mcycle (R/W)

    mcycle_nxt        : std_ulogic_vector(32 downto 0);

    mcycle_ovfl       : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow

    mcycleh           : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)

    minstret          : std_ulogic_vector(31 downto 0); -- minstret (R/W)

    minstret_nxt      : std_ulogic_vector(32 downto 0);

    minstret_ovfl     : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow

    minstreth         : std_ulogic_vector(31 downto 0); -- minstreth (R/W)

    --

    mhpmcounter       : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit

    mhpmcounter_nxt   : mhpmcnt_nxt_t;

    mhpmcounter_ovfl  : mhpmcnt_ovfl_t; -- counter low-to-high-word overflow

    mhpmcounterh      : mhpmcnt_t; -- mhpmcounter*h (R/W)

    mhpmcounter_rd    : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data

    mhpmcounterh_rd   : mhpmcnt_rd_t; -- mhpmcounter*h (R/W): actual read data

    --

    pmpcfg            : pmp_ctrl_t; -- physical memory protection - configuration registers

    pmpcfg_rd         : pmp_ctrl_rd_t; -- physical memory protection - actual read data

    pmpaddr           : pmp_addr_t; -- physical memory protection - address registers

    --

    frm               : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode

    fflags            : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags

    --

    dcsr_ebreakm      : std_ulogic; -- dcsr.ebreakm (R/W): behavior of ebreak instruction on m-mode

    dcsr_ebreaku      : std_ulogic; -- dcsr.ebreaku (R/W): behavior of ebreak instruction on u-mode

    dcsr_step         : std_ulogic; -- dcsr.step (R/W): single-step mode

    dcsr_prv          : std_ulogic_vector(01 downto 0); -- dcsr.prv (R/W): current privilege level when entering debug mode

    dcsr_cause        : std_ulogic_vector(02 downto 0); -- dcsr.cause (R/-): why was debug mode entered

    dcsr_rd           : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register

    dpc               : std_ulogic_vector(data_width_c-1 downto 0); -- dpc (R/W): debug mode program counter

    dscratch0         : std_ulogic_vector(data_width_c-1 downto 0); -- dscratch0 (R/W): debug mode scratch register 0

  end record;

  signal csr : csr_t;

  -- debug mode controller --

  type debug_ctrl_state_t is (DEBUG_OFFLINE, DEBUG_PENDING, DEBUG_ONLINE, DEBUG_EXIT);

  type debug_ctrl_t is record

    state        : debug_ctrl_state_t;

    -- decoded state --

    running      : std_ulogic; -- debug mode active

    pending      : std_ulogic; -- waiting to start debug mode

    -- entering triggers --

    trig_break   : std_ulogic; -- ebreak instruction

    trig_halt    : std_ulogic; -- external request

    trig_step    : std_ulogic; -- single-stepping mode

    -- leave debug mode --

    dret         : std_ulogic; -- executed DRET instruction

    -- misc --

    ext_halt_req : std_ulogic;

  end record;

  signal debug_ctrl : debug_ctrl_t;

  -- (hpm) counter events --

  signal cnt_event, cnt_event_nxt : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);

  signal hpmcnt_trigger           : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);

  -- illegal instruction check --

  signal illegal_opcode_lsbs : std_ulogic; -- if opcode != rv32

  signal illegal_instruction : std_ulogic;

  signal illegal_register    : std_ulogic; -- only for E-extension

  signal illegal_compressed  : std_ulogic; -- only fir C-extension

  -- access (privilege) check --

  signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)

begin

-- ****************************************************************************************************************************

-- Instruction Fetch (always fetch 32-bit-aligned 32-bit chunks of data)

-- ****************************************************************************************************************************

  -- Fetch Engine FSM Sync ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  fetch_engine_fsm_sync: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      fetch_engine.state      <= IFETCH_REQUEST;

      fetch_engine.state_prev <= IFETCH_REQUEST;

      fetch_engine.restart    <= '1';

      fetch_engine.pc         <= (others => def_rst_val_c);

    elsif rising_edge(clk_i) then

      fetch_engine.state      <= fetch_engine.state_nxt;

      fetch_engine.state_prev <= fetch_engine.state;

      fetch_engine.restart    <= fetch_engine.restart_nxt;

      if (fetch_engine.restart = '1') then

        fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC

      else

        fetch_engine.pc <= fetch_engine.pc_nxt;

      end if;

    end if;

  end process fetch_engine_fsm_sync;

  -- PC output --

  fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned

  -- Fetch Engine FSM Comb ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)

  begin

    -- arbiter defaults --

    bus_fast_ir              <= '0';

    fetch_engine.state_nxt   <= fetch_engine.state;

    fetch_engine.pc_nxt      <= fetch_engine.pc;

    fetch_engine.bus_err_ack <= '0';

    fetch_engine.restart_nxt <= fetch_engine.restart or fetch_engine.reset;

    -- instruction prefetch buffer interface --

    ipb.we    <= '0';

    ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word

    ipb.clear <= fetch_engine.restart;

    -- state machine --

    case fetch_engine.state is

      when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word

      -- ------------------------------------------------------------

        if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request?

          bus_fast_ir            <= '1'; -- fast instruction fetch request

          fetch_engine.state_nxt <= IFETCH_ISSUE;

        end if;

        if (fetch_engine.restart = '1') then -- reset request?

          fetch_engine.restart_nxt <= '0';

        end if;

      when IFETCH_ISSUE => -- store instruction data to prefetch buffer

      -- ------------------------------------------------------------

        fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors

        if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response

          fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);

          ipb.we              <= not fetch_engine.restart; -- write to IPB if not being reset

          if (fetch_engine.restart = '1') then -- reset request?

            fetch_engine.restart_nxt <= '0';

          end if;

          fetch_engine.state_nxt <= IFETCH_REQUEST;

        end if;

      when others => -- undefined

      -- ------------------------------------------------------------

        fetch_engine.state_nxt <= IFETCH_REQUEST;

    end case;

  end process fetch_engine_fsm_comb;

-- ****************************************************************************************************************************

-- Instruction Prefetch Buffer

-- ****************************************************************************************************************************

  -- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  instr_prefetch_buffer: neorv32_fifo

  generic map (

    FIFO_DEPTH => CPU_IPB_ENTRIES,  -- number of fifo entries; has to be a power of two; min 1

    FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo

    FIFO_RSYNC => false,            -- we NEED to read data asynchronously

    FIFO_SAFE  => false             -- no safe access required (ensured by FIFO-external control)

  )

  port map (

    -- control --

    clk_i   => clk_i,     -- clock, rising edge

    rstn_i  => '1',       -- async reset, low-active

    clear_i => ipb.clear, -- sync reset, high-active

    level_o => open,

    half_o  => open,

    -- write port --

    wdata_i => ipb.wdata, -- write data

    we_i    => ipb.we,    -- write enable

    free_o  => ipb.free,  -- at least one entry is free when set

    -- read port --

    re_i    => ipb.re,    -- read enable

    rdata_o => ipb.rdata, -- read data

    avail_o => ipb.avail  -- data available when set

  );

-- ****************************************************************************************************************************

-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)

-- ****************************************************************************************************************************

  -- Issue Engine FSM Sync ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  issue_engine_fsm_sync: process(rstn_i, clk_i)

  begin

    if (rstn_i = '0') then

      issue_engine.state <= ISSUE_ACTIVE;

      issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary

      issue_engine.buf   <= (others => def_rst_val_c);

    elsif rising_edge(clk_i) then

      if (ipb.clear = '1') then

        if (CPU_EXTENSION_RISCV_C = true) then

          if (execute_engine.pc(1) = '1') then -- branch to unaligned address?

            issue_engine.state <= ISSUE_REALIGN;

            issue_engine.align <= '1'; -- aligned on 16-bit boundary

          else

            issue_engine.state <= issue_engine.state_nxt;

            issue_engine.align <= '0'; -- aligned on 32-bit boundary

          end if;

        else

          issue_engine.state <= issue_engine.state_nxt;

          issue_engine.align <= '0'; -- always aligned on 32-bit boundaries

        end if;

      else

        issue_engine.state <= issue_engine.state_nxt;

        issue_engine.align <= issue_engine.align_nxt;

      end if;

      issue_engine.buf <= issue_engine.buf_nxt;

    end if;

  end process issue_engine_fsm_sync;

  -- Issue Engine FSM Comb ------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)

  begin

    -- arbiter defaults --

    issue_engine.state_nxt <= issue_engine.state;

    issue_engine.align_nxt <= issue_engine.align;

    issue_engine.buf_nxt   <= issue_engine.buf;

    -- instruction prefetch buffer interface defaults --

    ipb.re <= '0';

    -- instruction issue interface defaults --

    -- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>

    cmd_issue.data  <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);

    cmd_issue.valid <= '0';

    -- state machine --

    case issue_engine.state is

      when ISSUE_ACTIVE => -- issue instruction if available

      -- ------------------------------------------------------------

        if (ipb.avail = '1') then -- instructions available?

          if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word

            if (execute_engine.state = DISPATCH) then -- ready to issue new command?

              cmd_issue.valid      <= '1';

              issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction

              if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"

                ipb.re <= '1';

                cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);

              else -- compressed

                ipb.re <= '1';

                cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;

                issue_engine.align_nxt <= '1';

              end if;

            end if;

          else -- begin check in HIGH instruction half-word

            if (execute_engine.state = DISPATCH) then -- ready to issue new command?

              cmd_issue.valid      <= '1';

              issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction

              if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"

                ipb.re <= '1';

                cmd_issue.data <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));

              else -- compressed

                -- do not read from ipb here!

                cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;

                issue_engine.align_nxt <= '0';

              end if;

            end if;

          end if;

        end if;

      when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address

      -- ------------------------------------------------------------

        issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);

        if (ipb.avail = '1') then -- instructions available?

          ipb.re <= '1';

          issue_engine.state_nxt <= ISSUE_ACTIVE;

        end if;

      when others => -- undefined

      -- ------------------------------------------------------------

        issue_engine.state_nxt <= ISSUE_ACTIVE;

    end case;

  end process issue_engine_fsm_comb;

  -- 16-bit instructions: half-word select --

  ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);

  -- Compressed Instructions Recoding -------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  neorv32_cpu_decompressor_inst_true:

  if (CPU_EXTENSION_RISCV_C = true) generate

    neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor

    port map (

      -- instruction input --

      ci_instr16_i => ci_instr16, -- compressed instruction input

      -- instruction output --

      ci_illegal_o => ci_illegal, -- is an illegal compressed instruction