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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_cp_muldiv.vhd] - Blame information for rev 45

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1 2 zero_gravi
-- #################################################################################################
2 45 zero_gravi
-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension)>>       #
3 2 zero_gravi
-- # ********************************************************************************************* #
4
-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension.                      #
5 6 zero_gravi
-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency               #
6
-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency                         #
7 36 zero_gravi
-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true.                           #
8 2 zero_gravi
-- # ********************************************************************************************* #
9
-- # BSD 3-Clause License                                                                          #
10
-- #                                                                                               #
11 44 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
12 2 zero_gravi
-- #                                                                                               #
13
-- # Redistribution and use in source and binary forms, with or without modification, are          #
14
-- # permitted provided that the following conditions are met:                                     #
15
-- #                                                                                               #
16
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
17
-- #    conditions and the following disclaimer.                                                   #
18
-- #                                                                                               #
19
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
20
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
21
-- #    provided with the distribution.                                                            #
22
-- #                                                                                               #
23
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
24
-- #    endorse or promote products derived from this software without specific prior written      #
25
-- #    permission.                                                                                #
26
-- #                                                                                               #
27
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
28
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
29
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
30
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
31
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
32
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
33
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
34
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
35
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
36
-- # ********************************************************************************************* #
37
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
38
-- #################################################################################################
39
 
40
library ieee;
41
use ieee.std_logic_1164.all;
42
use ieee.numeric_std.all;
43
 
44
library neorv32;
45
use neorv32.neorv32_package.all;
46
 
47
entity neorv32_cpu_cp_muldiv is
48 19 zero_gravi
  generic (
49
    FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
50
  );
51 2 zero_gravi
  port (
52
    -- global control --
53
    clk_i   : in  std_ulogic; -- global clock, rising edge
54
    rstn_i  : in  std_ulogic; -- global reset, low-active, async
55
    ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
56 36 zero_gravi
    start_i : in  std_ulogic; -- trigger operation
57 2 zero_gravi
    -- data input --
58
    rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
59
    rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
60
    -- result and status --
61
    res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
62
    valid_o : out std_ulogic -- data output valid
63
  );
64
end neorv32_cpu_cp_muldiv;
65
 
66
architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
67
 
68 19 zero_gravi
  -- advanced configuration --
69
  constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
70 6 zero_gravi
 
71 44 zero_gravi
  -- operations --
72
  constant cp_op_mul_c    : std_ulogic_vector(2 downto 0) := "000"; -- mul
73
  constant cp_op_mulh_c   : std_ulogic_vector(2 downto 0) := "001"; -- mulh
74
  constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
75
  constant cp_op_mulhu_c  : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
76
  constant cp_op_div_c    : std_ulogic_vector(2 downto 0) := "100"; -- div
77
  constant cp_op_divu_c   : std_ulogic_vector(2 downto 0) := "101"; -- divu
78
  constant cp_op_rem_c    : std_ulogic_vector(2 downto 0) := "110"; -- rem
79
  constant cp_op_remu_c   : std_ulogic_vector(2 downto 0) := "111"; -- remu
80
 
81 2 zero_gravi
  -- controller --
82 22 zero_gravi
  type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED, FAST_MUL);
83 2 zero_gravi
  signal state         : state_t;
84
  signal cnt           : std_ulogic_vector(4 downto 0);
85
  signal cp_op         : std_ulogic_vector(2 downto 0); -- operation to execute
86 39 zero_gravi
  signal cp_op_ff      : std_ulogic_vector(2 downto 0); -- operation that was executed
87 2 zero_gravi
  signal start         : std_ulogic;
88
  signal operation     : std_ulogic;
89 45 zero_gravi
  signal rs1, opx, opy : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
90 2 zero_gravi
  signal opx_is_signed : std_ulogic;
91
  signal opy_is_signed : std_ulogic;
92 6 zero_gravi
  signal opy_is_zero   : std_ulogic;
93 2 zero_gravi
  signal div_res_corr  : std_ulogic;
94 39 zero_gravi
  signal valid         : std_ulogic;
95 2 zero_gravi
 
96
  -- divider core --
97
  signal remainder        : std_ulogic_vector(data_width_c-1 downto 0);
98
  signal quotient         : std_ulogic_vector(data_width_c-1 downto 0);
99
  signal div_sub          : std_ulogic_vector(data_width_c   downto 0);
100
  signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
101
  signal div_sign_comp    : std_ulogic_vector(data_width_c-1 downto 0);
102
  signal div_res          : std_ulogic_vector(data_width_c-1 downto 0);
103
 
104
  -- multiplier core --
105
  signal mul_product    : std_ulogic_vector(63 downto 0);
106 12 zero_gravi
  signal mul_do_add     : std_ulogic_vector(data_width_c downto 0);
107 2 zero_gravi
  signal mul_sign_cycle : std_ulogic;
108
  signal mul_p_sext     : std_ulogic;
109 19 zero_gravi
  signal mul_op_x       : signed(32 downto 0); -- for using DSPs
110
  signal mul_op_y       : signed(32 downto 0); -- for using DSPs
111
  signal mul_buf_ff     : signed(65 downto 0); -- for using DSPs
112
  signal mul_buf2_ff    : signed(65 downto 0); -- for using DSPs
113 2 zero_gravi
 
114
begin
115
 
116
  -- Co-Processor Controller ----------------------------------------------------------------
117
  -- -------------------------------------------------------------------------------------------
118
  coprocessor_ctrl: process(rstn_i, clk_i)
119
  begin
120
    if (rstn_i = '0') then
121
      state        <= IDLE;
122 3 zero_gravi
      opx          <= (others => '0');
123
      opy          <= (others => '0');
124 45 zero_gravi
      rs1          <= (others => '0');
125 3 zero_gravi
      cnt          <= (others => '0');
126
      start        <= '0';
127 39 zero_gravi
      valid        <= '0';
128 3 zero_gravi
      div_res_corr <= '0';
129 6 zero_gravi
      opy_is_zero  <= '0';
130 39 zero_gravi
      cp_op_ff     <= (others => '0');
131 2 zero_gravi
    elsif rising_edge(clk_i) then
132
      -- defaults --
133 39 zero_gravi
      start    <= '0';
134
      valid    <= '0';
135
      cp_op_ff <= cp_op;
136 2 zero_gravi
 
137
      -- FSM --
138
      case state is
139
        when IDLE =>
140 19 zero_gravi
          if (start_i = '1') then
141 45 zero_gravi
            opx   <= rs1_i;
142
            rs1   <= rs1_i;
143
            opy   <= rs2_i;
144 2 zero_gravi
            state <= DECODE;
145
          end if;
146
 
147
        when DECODE =>
148 12 zero_gravi
          --
149 6 zero_gravi
          if (cp_op = cp_op_div_c) then -- result sign compensation for div?
150 2 zero_gravi
            div_res_corr <= opx(opx'left) xor opy(opy'left);
151 6 zero_gravi
          elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
152
            div_res_corr <= opx(opx'left);
153 2 zero_gravi
          else
154
            div_res_corr <= '0';
155
          end if;
156 12 zero_gravi
          --
157
          if (or_all_f(opy) = '0') then -- *divide* by 0?
158 6 zero_gravi
            opy_is_zero <= '1';
159
          else
160
            opy_is_zero <= '0';
161
          end if;
162 12 zero_gravi
          --
163 22 zero_gravi
          cnt   <= "11111";
164 2 zero_gravi
          if (operation = '1') then -- division
165
            state <= INIT_OPX;
166
          else -- multiplication
167 22 zero_gravi
            start <= '1';
168
            if (FAST_MUL_EN = true) then
169
              state <= FAST_MUL;
170 12 zero_gravi
            else
171 22 zero_gravi
              state <= PROCESSING;
172 12 zero_gravi
            end if;
173 2 zero_gravi
          end if;
174
 
175
        when INIT_OPX =>
176
          if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
177
            opx <= div_sign_comp; -- make positive
178
          end if;
179
          state <= INIT_OPY;
180
 
181
        when INIT_OPY =>
182
          start <= '1';
183
          if ((opy(opy'left) and opy_is_signed) = '1') then -- signed division?
184
            opy <= div_sign_comp; -- make positive
185
          end if;
186
          state <= PROCESSING;
187
 
188
        when PROCESSING =>
189
          cnt <= std_ulogic_vector(unsigned(cnt) - 1);
190
          if (cnt = "00000") then
191
            state <= FINALIZE;
192
          end if;
193
 
194 22 zero_gravi
        when FAST_MUL =>
195
          state <= FINALIZE;
196
 
197 2 zero_gravi
        when FINALIZE =>
198
          state <= COMPLETED;
199
 
200
        when COMPLETED =>
201 39 zero_gravi
          valid <= '1';
202
          state <= IDLE;
203 2 zero_gravi
      end case;
204
    end if;
205
  end process coprocessor_ctrl;
206
 
207 36 zero_gravi
  -- co-processor command --
208
  cp_op <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
209
 
210 2 zero_gravi
  -- operation --
211
  operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
212
 
213
  -- opx (rs1) signed? --
214
  opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
215
 
216
  -- opy (rs2) signed? --
217
  opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
218
 
219
 
220 36 zero_gravi
  -- Multiplier Core (signed/unsigned) ------------------------------------------------------
221 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
222
  multiplier_core: process(clk_i)
223
  begin
224
    if rising_edge(clk_i) then
225 36 zero_gravi
      -- ---------------------------------------------------------
226 12 zero_gravi
      if (FAST_MUL_EN = false) then -- use small iterative computation
227
        if (start = '1') then -- start new multiplication
228
          mul_product(63 downto 32) <= (others => '0');
229
          mul_product(31 downto 00) <= opy;
230
        elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
231
          mul_product(63 downto 31) <= mul_do_add(32 downto 0);
232
          mul_product(30 downto 00) <= mul_product(31 downto 1);
233
        end if;
234 36 zero_gravi
      -- ---------------------------------------------------------
235 12 zero_gravi
      else -- use direct approach using (several!) DSP blocks
236
        if (start = '1') then
237 19 zero_gravi
          mul_op_x <= signed((opx(opx'left) and opx_is_signed) & opx);
238
          mul_op_y <= signed((opy(opy'left) and opy_is_signed) & opy);
239 12 zero_gravi
        end if;
240 19 zero_gravi
        mul_buf_ff <= mul_op_x * mul_op_y;
241
        if (dsp_add_reg_stage_c = true) then -- add another reg stage?
242
          mul_buf2_ff <= mul_buf_ff;
243
          mul_product <= std_ulogic_vector(mul_buf2_ff(63 downto 0)); -- let the register balancing do the magic here
244
        else
245
          mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
246
        end if;
247 2 zero_gravi
      end if;
248
    end if;
249
  end process multiplier_core;
250
 
251
  -- MUL: do another addition --
252 4 zero_gravi
  mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
253 2 zero_gravi
  begin
254 12 zero_gravi
    -- current bit of opy to take care of --
255
    if (mul_product(0) = '1') then -- multiply with 1
256
      if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1
257 6 zero_gravi
        mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opx'left) and opx_is_signed) & opx));
258 12 zero_gravi
      else -- multiply with +1
259 6 zero_gravi
        mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opx'left) and opx_is_signed) & opx));
260 2 zero_gravi
      end if;
261 12 zero_gravi
    else -- multiply with 0
262 2 zero_gravi
      mul_do_add <= mul_p_sext & mul_product(63 downto 32);
263
    end if;
264
  end process mul_update;
265
 
266
  -- sign control --
267
  mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
268
  mul_p_sext     <= mul_product(mul_product'left) and opx_is_signed;
269
 
270
 
271 12 zero_gravi
  -- Divider Core (unsigned) ----------------------------------------------------------------
272 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
273
  divider_core: process(clk_i)
274
  begin
275
    if rising_edge(clk_i) then
276
      if (start = '1') then -- start new division
277
        quotient  <= opx;
278
        remainder <= (others => '0');
279
      elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '1') then -- running?
280
        quotient <= quotient(30 downto 0) & (not div_sub(32));
281
        if (div_sub(32) = '0') then -- still overflowing
282
          remainder <= div_sub(31 downto 0);
283
        else -- underflow
284
          remainder <= remainder(30 downto 0) & quotient(31);
285
        end if;
286
      end if;
287
    end if;
288
  end process divider_core;
289
 
290
  -- DIV: try another subtraction --
291
  div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & opy));
292
 
293
  -- Div sign compensation --
294
  div_sign_comp_in <= opx when (state = INIT_OPX) else
295
                      opy when (state = INIT_OPY) else
296
                      quotient when ((cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c)) else remainder;
297
  div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
298
 
299
  -- result sign correction --
300 6 zero_gravi
  div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
301 2 zero_gravi
 
302
 
303
  -- Data Output ----------------------------------------------------------------------------
304
  -- -------------------------------------------------------------------------------------------
305 45 zero_gravi
  operation_result: process(valid, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1, remainder)
306 2 zero_gravi
  begin
307 39 zero_gravi
    if (valid = '1') then
308
      case cp_op_ff is
309 2 zero_gravi
        when cp_op_mul_c =>
310
          res_o <= mul_product(31 downto 00);
311
        when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
312
          res_o <= mul_product(63 downto 32);
313
        when cp_op_div_c =>
314
          res_o <= div_res;
315
        when cp_op_divu_c =>
316
          res_o <= quotient;
317
        when cp_op_rem_c =>
318 6 zero_gravi
          if (opy_is_zero = '0') then
319
            res_o <= div_res;
320
          else
321 45 zero_gravi
            res_o <= rs1;
322 6 zero_gravi
          end if;
323 39 zero_gravi
        when others => -- cp_op_remu_c
324 2 zero_gravi
          res_o <= remainder;
325
      end case;
326 39 zero_gravi
    else
327 40 zero_gravi
      res_o <= (others => '0');
328 2 zero_gravi
    end if;
329
  end process operation_result;
330
 
331 40 zero_gravi
  -- status output --
332
  valid_o <= valid;
333 2 zero_gravi
 
334 40 zero_gravi
 
335 2 zero_gravi
end neorv32_cpu_cp_muldiv_rtl;

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