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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Blame information for rev 49

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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 41 zero_gravi 
  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 40 zero_gravi 
 
55 47 zero_gravi 
  -- "critical" number of PMP regions --
56 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically
57 
  -- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle!
58 
  constant pmp_num_regions_critical_c : natural := 8;
59 
 
60 48 zero_gravi 
  -- Architecture Constants (do not modify!) ------------------------------------------------
61 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
62 47 zero_gravi 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
63 49 zero_gravi 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050104"; -- no touchy!
64 40 zero_gravi 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
65 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
66 42 zero_gravi 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
67 27 zero_gravi 
 
68 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
69 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
70 
  function index_size_f(input : natural) return natural;
71 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
72 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
73 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
74 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
75 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
76 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
77 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
78 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
79 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
80 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
81 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
82 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
83 2 zero_gravi 
 
84 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
85 
  -- -------------------------------------------------------------------------------------------
86 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
87 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
88 49 zero_gravi 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
89 15 zero_gravi 
 
90 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
91 
  -- -------------------------------------------------------------------------------------------
92 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
93 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
94 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
95 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
96 2 zero_gravi 
 
97 23 zero_gravi 
  -- Internal Bootloader ROM --
98 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
99 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
100 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
101 23 zero_gravi 
 
102 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
103 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
104 47 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
105 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
106 2 zero_gravi 
 
107 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
108 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address
109 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
110 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
111 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";
112 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";
113 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";
114 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";
115 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";
116 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";
117 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";
118 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";
119 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";
120 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";
121 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";
122 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";
123 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";
124 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";
125 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";
126 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";
127 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";
128 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";
129 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";
130 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";
131 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";
132 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";
133 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";
134 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";
135 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";
136 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";
137 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";
138 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";
139 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";
140 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";
141 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";
142 
 
143 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
144 47 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address
145 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
146 23 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
147 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
148 2 zero_gravi 
 
149 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
150 47 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address
151 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
152 30 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
153 2 zero_gravi 
 
154 
  -- Watch Dog Timer (WDT) --
155 47 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address
156 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
157 23 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
158 2 zero_gravi 
 
159 
  -- Machine System Timer (MTIME) --
160 47 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address
161 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
162 23 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
163 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
164 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
165 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
166 2 zero_gravi 
 
167 
  -- Universal Asynchronous Receiver/Transmitter (UART) --
168 47 zero_gravi 
  constant uart_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
169 
  constant uart_size_c          : natural := 2*4; -- module's address space in bytes
170 23 zero_gravi 
  constant uart_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
171 
  constant uart_rtx_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
172 2 zero_gravi 
 
173 
  -- Serial Peripheral Interface (SPI) --
174 47 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
175 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
176 23 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
177 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
178 2 zero_gravi 
 
179 
  -- Two Wire Interface (TWI) --
180 47 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address
181 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
182 23 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
183 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
184 2 zero_gravi 
 
185 
  -- Pulse-Width Modulation Controller (PWM) --
186 47 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
187 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
188 23 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
189 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
190 2 zero_gravi 
 
191 49 zero_gravi 
  -- Numerically-Controlled Oscillator (NCO) --
192 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
193 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
194 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
195 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
196 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
197 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
198 
 
199 47 zero_gravi 
  -- reserved --
200 49 zero_gravi 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
201 
--constant reserved_size_c      : natural := 4*4; -- module's address space in bytes
202 12 zero_gravi 
 
203 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
204 47 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
205 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
206 12 zero_gravi 
 
207 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
208 
  -- -------------------------------------------------------------------------------------------
209 
  -- register file --
210 49 zero_gravi 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
211 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
212 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
213 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
214 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
215 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
216 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
217 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
218 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
219 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
220 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
221 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
222 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
223 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
224 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
225 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
226 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
227 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
228 2 zero_gravi 
  -- alu --
229 49 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
230 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
231 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
232 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
233 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
234 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
235 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
236 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
237 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
238 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
239 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
240 2 zero_gravi 
  -- bus interface --
241 49 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
242 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
243 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
244 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
245 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
246 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
247 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
248 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
249 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
250 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
251 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
252 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
253 
  constant ctrl_bus_lock_c      : natural := 41; -- locked/exclusive bus access
254 26 zero_gravi 
  -- co-processors --
255 49 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 42; -- cp select ID lsb
256 
  constant ctrl_cp_id_hsb_c     : natural := 43; -- cp select ID hsb
257 39 zero_gravi 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
258 36 zero_gravi 
  -- current privilege level --
259 39 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
260 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
261 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
262 39 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
263 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
264 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
265 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
266 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
267 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
268 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
269 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
270 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
271 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
272 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
273 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
274 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
275 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
276 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
277 44 zero_gravi 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
278 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
279 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
280 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
281 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
282 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
283 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
284 47 zero_gravi 
  -- CPU status --
285 
  constant ctrl_sleep_c         : natural := 69; -- set when CPU is in sleep mode
286 2 zero_gravi 
  -- control bus size --
287 47 zero_gravi 
  constant ctrl_width_c         : natural := 70; -- control bus size
288 2 zero_gravi 
 
289 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
290 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
291 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
292 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
293 2 zero_gravi 
 
294 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
295 
  -- -------------------------------------------------------------------------------------------
296 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
297 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
298 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
299 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
300 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
301 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
302 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
303 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
304 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
305 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
306 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
307 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
308 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
309 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
310 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
311 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
312 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
313 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
314 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
315 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
316 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
317 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
318 2 zero_gravi 
 
319 
  -- RISC-V Opcodes -------------------------------------------------------------------------
320 
  -- -------------------------------------------------------------------------------------------
321 
  -- alu --
322 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
323 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
324 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
325 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
326 
  -- control flow --
327 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
328 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
329 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
330 
  -- memory access --
331 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
332 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
333 
  -- system/csr --
334 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
335 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
336 39 zero_gravi 
  -- atomic operations (A) --
337 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
338 2 zero_gravi 
 
339 
  -- RISC-V Funct3 --------------------------------------------------------------------------
340 
  -- -------------------------------------------------------------------------------------------
341 
  -- control flow --
342 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
343 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
344 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
345 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
346 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
347 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
348 
  -- memory access --
349 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
350 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
351 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
352 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
353 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
354 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
355 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
356 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
357 
  -- alu --
358 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
359 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
360 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
361 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
362 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
363 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
364 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
365 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
366 
  -- system/csr --
367 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
368 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
369 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
370 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
371 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
372 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
373 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
374 8 zero_gravi 
  -- fence --
375 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
376 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
377 2 zero_gravi 
 
378 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
379 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
380 
  -- system --
381 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
382 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
383 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
384 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
385 
 
386 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
387 
  -- -------------------------------------------------------------------------------------------
388 
  -- atomic operations --
389 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
390 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
391 
 
392 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
393 
  -- -------------------------------------------------------------------------------------------
394 41 zero_gravi 
  -- read/write CSRs --
395 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
396 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
397 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
398 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
399 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
400 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
401 29 zero_gravi 
  --
402 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
403 29 zero_gravi 
  --
404 42 zero_gravi 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
405 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
406 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
407 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
408 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
409 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
410 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
411 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
412 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
413 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
414 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
415 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
416 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
417 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
418 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
419 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
420 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
421 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
422 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
423 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
424 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
425 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
426 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
427 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
428 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
429 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
430 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
431 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
432 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
433 29 zero_gravi 
  --
434 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
435 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
436 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
437 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
438 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
439 29 zero_gravi 
  --
440 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
441 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
442 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
443 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
444 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
445 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
446 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
447 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
448 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
449 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
450 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
451 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
452 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
453 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
454 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
455 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
456 29 zero_gravi 
  --
457 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
458 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
459 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
460 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
461 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
462 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
463 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
464 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
465 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
466 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
467 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
468 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
469 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
470 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
471 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
472 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
473 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
474 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
475 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
476 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
477 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
478 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
479 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
480 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
481 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
482 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
483 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
484 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
485 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
486 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
487 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
488 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
489 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
490 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
491 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
492 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
493 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
494 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
495 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
496 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
497 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
498 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
499 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
500 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
501 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
502 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
503 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
504 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
505 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
506 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
507 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
508 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
509 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
510 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
511 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
512 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
513 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
514 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
515 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
516 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
517 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
518 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
519 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
520 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
521 29 zero_gravi 
  --
522 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
523 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
524 
  --
525 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
526 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
527 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
528 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
529 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
530 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
531 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
532 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
533 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
534 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
535 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
536 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
537 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
538 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
539 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
540 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
541 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
542 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
543 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
544 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
545 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
546 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
547 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
548 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
549 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
550 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
551 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
552 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
553 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
554 
  --
555 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
556 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
557 
  --
558 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
559 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
560 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
561 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
562 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
563 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
564 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
565 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
566 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
567 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
568 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
569 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
570 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
571 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
572 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
573 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
574 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
575 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
576 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
577 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
578 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
579 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
580 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
581 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
582 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
583 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
584 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
585 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
586 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
587 
 
588 41 zero_gravi 
  -- read-only CSRs --
589 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
590 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
591 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
592 29 zero_gravi 
  --
593 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
594 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
595 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
596 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
597 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
598 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
599 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
600 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
601 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
602 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
603 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
604 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
605 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
606 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
607 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
608 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
609 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
610 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
611 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
612 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
613 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
614 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
615 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
616 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
617 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
618 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
619 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
620 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
621 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
622 29 zero_gravi 
  --
623 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
624 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
625 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
626 29 zero_gravi 
  --
627 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
628 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
629 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
630 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
631 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
632 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
633 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
634 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
635 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
636 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
637 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
638 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
639 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
640 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
641 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
642 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
643 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
644 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
645 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
646 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
647 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
648 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
649 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
650 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
651 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
652 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
653 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
654 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
655 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
656 
  --
657 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
658 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
659 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
660 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
661 29 zero_gravi 
 
662 42 zero_gravi 
  -- custom read-only CSRs --
663 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
664 
 
665 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
666 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
667 49 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
668 
  constant cp_sel_atomic_c   : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
669 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
670 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
671 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "100"; -- reserved
672 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "101"; -- reserved
673 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "110"; -- reserved
674 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "111"; -- reserved
675 2 zero_gravi 
 
676 
  -- ALU Function Codes ---------------------------------------------------------------------
677 
  -- -------------------------------------------------------------------------------------------
678 39 zero_gravi 
  -- arithmetic core --
679 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
680 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
681 
  -- logic core --
682 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
683 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
684 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
685 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
686 
  -- function select (actual alu result) --
687 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
688 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
689 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
690 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
691 2 zero_gravi 
 
692 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
693 
  -- -------------------------------------------------------------------------------------------
694 48 zero_gravi 
  -- RISC-V compliant sync. exceptions --
695 
  constant trap_ima_c    : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
696 
  constant trap_iba_c    : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
697 
  constant trap_iil_c    : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
698 
  constant trap_brk_c    : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
699 
  constant trap_lma_c    : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
700 
  constant trap_lbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
701 
  constant trap_sma_c    : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
702 
  constant trap_sbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
703 
  constant trap_uenv_c   : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
704 
  constant trap_menv_c   : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
705 
  -- RISC-V compliant interrupts (async. exceptions) --
706 
  constant trap_msi_c    : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
707 
  constant trap_mti_c    : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
708 
  constant trap_mei_c    : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
709 
  -- NEORV32-specific (custom) interrupts (async. exceptions) --
710 
  constant trap_reset_c  : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0:  hardware reset
711 
  constant trap_firq0_c  : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
712 
  constant trap_firq1_c  : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
713 
  constant trap_firq2_c  : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
714 
  constant trap_firq3_c  : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
715 
  constant trap_firq4_c  : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
716 
  constant trap_firq5_c  : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
717 
  constant trap_firq6_c  : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
718 
  constant trap_firq7_c  : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
719 
  constant trap_firq8_c  : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
720 
  constant trap_firq9_c  : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
721 
  constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
722 
  constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
723 
  constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
724 
  constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
725 
  constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
726 
  constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
727 12 zero_gravi 
 
728 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
729 
  -- -------------------------------------------------------------------------------------------
730 
  -- exception source bits --
731 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
732 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
733 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
734 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
735 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
736 
  constant exception_break_c     : natural :=  5; -- breakpoint
737 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
738 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
739 
  constant exception_saccess_c   : natural :=  8; -- store access fault
740 
  constant exception_laccess_c   : natural :=  9; -- load access fault
741 14 zero_gravi 
  --
742 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
743 2 zero_gravi 
  -- interrupt source bits --
744 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
745 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
746 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
747 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
748 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
749 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
750 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
751 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
752 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
753 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
754 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
755 48 zero_gravi 
  constant interrupt_firq_8_c    : natural := 11; -- fast interrupt channel 8
756 
  constant interrupt_firq_9_c    : natural := 12; -- fast interrupt channel 9
757 
  constant interrupt_firq_10_c   : natural := 13; -- fast interrupt channel 10
758 
  constant interrupt_firq_11_c   : natural := 14; -- fast interrupt channel 11
759 
  constant interrupt_firq_12_c   : natural := 15; -- fast interrupt channel 12
760 
  constant interrupt_firq_13_c   : natural := 16; -- fast interrupt channel 13
761 
  constant interrupt_firq_14_c   : natural := 17; -- fast interrupt channel 14
762 
  constant interrupt_firq_15_c   : natural := 18; -- fast interrupt channel 15
763 14 zero_gravi 
  --
764 48 zero_gravi 
  constant interrupt_width_c     : natural := 19; -- length of this list in bits
765 2 zero_gravi 
 
766 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
767 
  -- -------------------------------------------------------------------------------------------
768 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
769 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
770 15 zero_gravi 
 
771 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
772 
  -- -------------------------------------------------------------------------------------------
773 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
774 
  constant hpmcnt_event_never_c   : natural := 1;
775 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
776 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
777 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
778 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
779 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
780 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
781 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
782 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
783 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
784 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
785 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
786 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
787 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
788 42 zero_gravi 
  --
789 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
790 42 zero_gravi 
 
791 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
792 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
793 
  constant clk_div2_c    : natural := 0;
794 
  constant clk_div4_c    : natural := 1;
795 
  constant clk_div8_c    : natural := 2;
796 
  constant clk_div64_c   : natural := 3;
797 
  constant clk_div128_c  : natural := 4;
798 
  constant clk_div1024_c : natural := 5;
799 
  constant clk_div2048_c : natural := 6;
800 
  constant clk_div4096_c : natural := 7;
801 
 
802 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
803 
  -- -------------------------------------------------------------------------------------------
804 
  component neorv32_top
805 
    generic (
806 
      -- General --
807 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
808 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
809 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
810 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
811 2 zero_gravi 
      -- RISC-V CPU Extensions --
812 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
813 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
814 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
815 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
816 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
817 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
818 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
819 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
820 19 zero_gravi 
      -- Extension Options --
821 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
822 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
823 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
824 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
825 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
826 
      -- Hardware Performance Monitors (HPM) --
827 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
828 23 zero_gravi 
      -- Internal Instruction memory --
829 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
830 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
831 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
832 23 zero_gravi 
      -- Internal Data memory --
833 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
834 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
835 41 zero_gravi 
      -- Internal Cache memory --
836 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
837 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
838 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
839 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
840 23 zero_gravi 
      -- External memory interface --
841 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
842 2 zero_gravi 
      -- Processor peripherals --
843 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
844 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
845 
      IO_UART_EN                   : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
846 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
847 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
848 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
849 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
850 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
851 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
852 49 zero_gravi 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
853 
      IO_NCO_EN                    : boolean := true    -- implement numerically-controlled oscillator (NCO)?
854 2 zero_gravi 
    );
855 
    port (
856 
      -- Global control --
857 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
858 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
859 49 zero_gravi 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
860 36 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- tag
861 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
862 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
863 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
864 
      wb_we_o     : out std_ulogic; -- read/write
865 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
866 
      wb_stb_o    : out std_ulogic; -- strobe
867 
      wb_cyc_o    : out std_ulogic; -- valid cycle
868 39 zero_gravi 
      wb_lock_o   : out std_ulogic; -- locked/exclusive bus access
869 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
870 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
871 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
872 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
873 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
874 49 zero_gravi 
      -- GPIO (available if IO_GPIO_EN = true) --
875 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
876 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
877 49 zero_gravi 
      -- UART (available if IO_UART_EN = true) --
878 34 zero_gravi 
      uart_txd_o  : out std_ulogic; -- UART send data
879 
      uart_rxd_i  : in  std_ulogic := '0'; -- UART receive data
880 49 zero_gravi 
      -- SPI (available if IO_SPI_EN = true) --
881 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
882 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
883 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
884 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
885 49 zero_gravi 
      -- TWI (available if IO_TWI_EN = true) --
886 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
887 
      twi_scl_io  : inout std_logic; -- twi serial clock line
888 49 zero_gravi 
      -- PWM (available if IO_PWM_EN = true) --
889 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
890 47 zero_gravi 
      -- Custom Functions Subsystem IO --
891 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs
892 
      cfs_out_o   : out std_ulogic_vector(31 downto 0); -- custom CSF outputs
893 49 zero_gravi 
      -- NCO output (available if IO_NCO_EN = true) --
894 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
895 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
896 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
897 2 zero_gravi 
      -- Interrupts --
898 48 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
899 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
900 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
901 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
902 2 zero_gravi 
    );
903 
  end component;
904 
 
905 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
906 
  -- -------------------------------------------------------------------------------------------
907 
  component neorv32_cpu
908 
    generic (
909 
      -- General --
910 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
911 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
912 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
913 4 zero_gravi 
      -- RISC-V CPU Extensions --
914 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
915 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
916 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
917 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
918 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
919 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
920 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
921 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
922 19 zero_gravi 
      -- Extension Options --
923 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
924 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
925 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
926 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
927 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
928 
      -- Hardware Performance Monitors (HPM) --
929 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
930 4 zero_gravi 
    );
931 
    port (
932 
      -- global control --
933 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
934 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
935 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
936 12 zero_gravi 
      -- instruction bus interface --
937 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
938 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
939 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
940 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
941 
      i_bus_we_o     : out std_ulogic; -- write enable
942 
      i_bus_re_o     : out std_ulogic; -- read enable
943 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
944 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
945 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
946 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
947 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
948 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
949 12 zero_gravi 
      -- data bus interface --
950 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
951 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
952 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
953 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
954 
      d_bus_we_o     : out std_ulogic; -- write enable
955 
      d_bus_re_o     : out std_ulogic; -- read enable
956 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
957 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
958 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
959 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
960 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
961 39 zero_gravi 
      d_bus_lock_o   : out std_ulogic; -- locked/exclusive access
962 11 zero_gravi 
      -- system time input from MTIME --
963 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
964 
      -- interrupts (risc-v compliant) --
965 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
966 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
967 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
968 
      -- fast interrupts (custom) --
969 48 zero_gravi 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
970 
      firq_ack_o     : out std_ulogic_vector(15 downto 0)
971 4 zero_gravi 
    );
972 
  end component;
973 
 
974 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
975 
  -- -------------------------------------------------------------------------------------------
976 
  component neorv32_cpu_control
977 
    generic (
978 
      -- General --
979 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
980 12 zero_gravi 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
981 2 zero_gravi 
      -- RISC-V CPU Extensions --
982 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
983 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
984 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
985 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
986 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
987 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
988 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
989 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
990 15 zero_gravi 
      -- Physical memory protection (PMP) --
991 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
992 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
993 
      -- Hardware Performance Monitors (HPM) --
994 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
995 2 zero_gravi 
    );
996 
    port (
997 
      -- global control --
998 
      clk_i         : in  std_ulogic; -- global clock, rising edge
999 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1000 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1001 
      -- status input --
1002 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
1003 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
1004 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
1005 2 zero_gravi 
      -- data input --
1006 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1007 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
1008 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
1009 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1010 2 zero_gravi 
      -- data output --
1011 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1012 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1013 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
1014 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1015 14 zero_gravi 
      -- interrupts (risc-v compliant) --
1016 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
1017 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
1018 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
1019 14 zero_gravi 
      -- fast interrupts (custom) --
1020 48 zero_gravi 
      firq_i        : in  std_ulogic_vector(15 downto 0);
1021 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
1022 11 zero_gravi 
      -- system time input from MTIME --
1023 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
1024 15 zero_gravi 
      -- physical memory protection --
1025 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
1026 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
1027 2 zero_gravi 
      -- bus access exceptions --
1028 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
1029 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
1030 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
1031 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1032 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1033 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1034 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1035 2 zero_gravi 
    );
1036 
  end component;
1037 
 
1038 
  -- Component: CPU Register File -----------------------------------------------------------
1039 
  -- -------------------------------------------------------------------------------------------
1040 
  component neorv32_cpu_regfile
1041 
    generic (
1042 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1043 
    );
1044 
    port (
1045 
      -- global control --
1046 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1047 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1048 
      -- data input --
1049 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1050 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1051 
      -- data output --
1052 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1053 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1054 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1055 2 zero_gravi 
    );
1056 
  end component;
1057 
 
1058 
  -- Component: CPU ALU ---------------------------------------------------------------------
1059 
  -- -------------------------------------------------------------------------------------------
1060 
  component neorv32_cpu_alu
1061 11 zero_gravi 
    generic (
1062 34 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
1063 
      FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
1064 11 zero_gravi 
    );
1065 2 zero_gravi 
    port (
1066 
      -- global control --
1067 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1068 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1069 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1070 
      -- data input --
1071 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1072 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1073 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1074 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1075 
      -- data output --
1076 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1077 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1078 2 zero_gravi 
      -- co-processor interface --
1079 49 zero_gravi 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
1080 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
1081 
      cp_result_i : in  cp_data_if_t; -- co-processor result
1082 2 zero_gravi 
      -- status --
1083 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1084 
    );
1085 
  end component;
1086 
 
1087 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1088 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1089 
  component neorv32_cpu_cp_muldiv
1090 19 zero_gravi 
    generic (
1091 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1092 
    );
1093 2 zero_gravi 
    port (
1094 
      -- global control --
1095 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1096 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1097 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1098 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1099 2 zero_gravi 
      -- data input --
1100 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1101 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1102 
      -- result and status --
1103 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1104 
      valid_o : out std_ulogic -- data output valid
1105 
    );
1106 
  end component;
1107 
 
1108 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1109 
  -- -------------------------------------------------------------------------------------------
1110 
  component neorv32_cpu_cp_bitmanip
1111 
    port (
1112 
      -- global control --
1113 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1114 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1115 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1116 
      start_i : in  std_ulogic; -- trigger operation
1117 
      -- data input --
1118 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1119 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1120 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1121 
      -- result and status --
1122 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1123 
      valid_o : out std_ulogic -- data output valid
1124 
    );
1125 
  end component;
1126 
 
1127 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1128 
  -- -------------------------------------------------------------------------------------------
1129 
  component neorv32_cpu_bus
1130 
    generic (
1131 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1132 15 zero_gravi 
      -- Physical memory protection (PMP) --
1133 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1134 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1135 41 zero_gravi 
      -- Bus Timeout --
1136 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1137 2 zero_gravi 
    );
1138 
    port (
1139 
      -- global control --
1140 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1141 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1142 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1143 
      -- cpu instruction fetch interface --
1144 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1145 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1146 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1147 
      --
1148 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1149 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1150 
      -- cpu data access interface --
1151 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1152 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1153 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1154 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1155 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1156 
      --
1157 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1158 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1159 
      be_load_o      : out std_ulogic; -- bus error on load data access
1160 
      be_store_o     : out std_ulogic; -- bus error on store data access
1161 15 zero_gravi 
      -- physical memory protection --
1162 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1163 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1164 12 zero_gravi 
      -- instruction bus --
1165 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1166 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1167 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1168 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1169 
      i_bus_we_o     : out std_ulogic; -- write enable
1170 
      i_bus_re_o     : out std_ulogic; -- read enable
1171 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1172 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1173 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1174 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1175 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
1176 12 zero_gravi 
      -- data bus --
1177 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1178 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1179 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1180 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1181 
      d_bus_we_o     : out std_ulogic; -- write enable
1182 
      d_bus_re_o     : out std_ulogic; -- read enable
1183 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1184 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1185 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1186 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1187 
      d_bus_lock_o   : out std_ulogic  -- locked/exclusive access
1188 2 zero_gravi 
    );
1189 
  end component;
1190 
 
1191 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1192 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1193 45 zero_gravi 
  component neorv32_icache
1194 41 zero_gravi 
    generic (
1195 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1196 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1197 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1198 41 zero_gravi 
    );
1199 
    port (
1200 
      -- global control --
1201 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1202 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1203 
      clear_i       : in  std_ulogic; -- cache clear
1204 
      -- host controller interface --
1205 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1206 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1207 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1208 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1209 
      host_we_i     : in  std_ulogic; -- write enable
1210 
      host_re_i     : in  std_ulogic; -- read enable
1211 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1212 
      host_lock_i   : in  std_ulogic; -- locked/exclusive access
1213 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1214 
      host_err_o    : out std_ulogic; -- bus transfer error
1215 
      -- peripheral bus interface --
1216 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1217 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1218 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1219 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1220 
      bus_we_o      : out std_ulogic; -- write enable
1221 
      bus_re_o      : out std_ulogic; -- read enable
1222 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1223 
      bus_lock_o    : out std_ulogic; -- locked/exclusive access
1224 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1225 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1226 
    );
1227 
  end component;
1228 
 
1229 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1230 
  -- -------------------------------------------------------------------------------------------
1231 
  component neorv32_busswitch
1232 
    generic (
1233 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1234 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1235 
    );
1236 
    port (
1237 
      -- global control --
1238 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1239 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1240 
      -- controller interface a --
1241 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1242 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1243 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1244 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1245 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1246 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1247 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1248 39 zero_gravi 
      ca_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1249 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1250 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1251 
      -- controller interface b --
1252 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1253 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1254 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1255 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1256 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1257 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1258 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1259 39 zero_gravi 
      cb_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1260 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1261 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1262 
      -- peripheral bus --
1263 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1264 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1265 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1266 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1267 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1268 
      p_bus_we_o      : out std_ulogic; -- write enable
1269 
      p_bus_re_o      : out std_ulogic; -- read enable
1270 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1271 39 zero_gravi 
      p_bus_lock_o    : out std_ulogic; -- locked/exclusive access
1272 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1273 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1274 
    );
1275 
  end component;
1276 
 
1277 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1278 
  -- -------------------------------------------------------------------------------------------
1279 
  component neorv32_cpu_decompressor
1280 
    port (
1281 
      -- instruction input --
1282 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1283 
      -- instruction output --
1284 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1285 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1286 
    );
1287 
  end component;
1288 
 
1289 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1290 
  -- -------------------------------------------------------------------------------------------
1291 
  component neorv32_imem
1292 
    generic (
1293 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1294 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1295 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1296 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1297 2 zero_gravi 
    );
1298 
    port (
1299 
      clk_i  : in  std_ulogic; -- global clock line
1300 
      rden_i : in  std_ulogic; -- read enable
1301 
      wren_i : in  std_ulogic; -- write enable
1302 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1303 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1304 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1305 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1306 
      ack_o  : out std_ulogic -- transfer acknowledge
1307 
    );
1308 
  end component;
1309 
 
1310 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1311 
  -- -------------------------------------------------------------------------------------------
1312 
  component neorv32_dmem
1313 
    generic (
1314 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1315 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1316 
    );
1317 
    port (
1318 
      clk_i  : in  std_ulogic; -- global clock line
1319 
      rden_i : in  std_ulogic; -- read enable
1320 
      wren_i : in  std_ulogic; -- write enable
1321 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1322 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1323 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1324 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1325 
      ack_o  : out std_ulogic -- transfer acknowledge
1326 
    );
1327 
  end component;
1328 
 
1329 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1330 
  -- -------------------------------------------------------------------------------------------
1331 
  component neorv32_boot_rom
1332 23 zero_gravi 
    generic (
1333 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1334 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1335 
    );
1336 2 zero_gravi 
    port (
1337 
      clk_i  : in  std_ulogic; -- global clock line
1338 
      rden_i : in  std_ulogic; -- read enable
1339 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1340 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1341 
      ack_o  : out std_ulogic -- transfer acknowledge
1342 
    );
1343 
  end component;
1344 
 
1345 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1346 
  -- -------------------------------------------------------------------------------------------
1347 
  component neorv32_mtime
1348 
    port (
1349 
      -- host access --
1350 
      clk_i     : in  std_ulogic; -- global clock line
1351 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1352 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1353 
      rden_i    : in  std_ulogic; -- read enable
1354 
      wren_i    : in  std_ulogic; -- write enable
1355 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1356 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1357 
      ack_o     : out std_ulogic; -- transfer acknowledge
1358 11 zero_gravi 
      -- time output for CPU --
1359 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1360 2 zero_gravi 
      -- interrupt --
1361 
      irq_o     : out std_ulogic  -- interrupt request
1362 
    );
1363 
  end component;
1364 
 
1365 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1366 
  -- -------------------------------------------------------------------------------------------
1367 
  component neorv32_gpio
1368 
    port (
1369 
      -- host access --
1370 
      clk_i  : in  std_ulogic; -- global clock line
1371 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1372 
      rden_i : in  std_ulogic; -- read enable
1373 
      wren_i : in  std_ulogic; -- write enable
1374 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1375 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1376 
      ack_o  : out std_ulogic; -- transfer acknowledge
1377 
      -- parallel io --
1378 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1379 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1380 2 zero_gravi 
      -- interrupt --
1381 
      irq_o  : out std_ulogic
1382 
    );
1383 
  end component;
1384 
 
1385 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1386 
  -- -------------------------------------------------------------------------------------------
1387 
  component neorv32_wdt
1388 
    port (
1389 
      -- host access --
1390 
      clk_i       : in  std_ulogic; -- global clock line
1391 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1392 
      rden_i      : in  std_ulogic; -- read enable
1393 
      wren_i      : in  std_ulogic; -- write enable
1394 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1395 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1396 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1397 
      ack_o       : out std_ulogic; -- transfer acknowledge
1398 
      -- clock generator --
1399 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1400 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1401 
      -- timeout event --
1402 
      irq_o       : out std_ulogic; -- timeout IRQ
1403 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1404 
    );
1405 
  end component;
1406 
 
1407 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1408 
  -- -------------------------------------------------------------------------------------------
1409 
  component neorv32_uart
1410 
    port (
1411 
      -- host access --
1412 
      clk_i       : in  std_ulogic; -- global clock line
1413 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1414 
      rden_i      : in  std_ulogic; -- read enable
1415 
      wren_i      : in  std_ulogic; -- write enable
1416 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1417 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1418 
      ack_o       : out std_ulogic; -- transfer acknowledge
1419 
      -- clock generator --
1420 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1421 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1422 
      -- com lines --
1423 
      uart_txd_o  : out std_ulogic;
1424 
      uart_rxd_i  : in  std_ulogic;
1425 
      -- interrupts --
1426 48 zero_gravi 
      irq_rxd_o   : out std_ulogic; -- uart data received interrupt
1427 
      irq_txd_o   : out std_ulogic  -- uart transmission done interrupt
1428 2 zero_gravi 
    );
1429 
  end component;
1430 
 
1431 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1432 
  -- -------------------------------------------------------------------------------------------
1433 
  component neorv32_spi
1434 
    port (
1435 
      -- host access --
1436 
      clk_i       : in  std_ulogic; -- global clock line
1437 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1438 
      rden_i      : in  std_ulogic; -- read enable
1439 
      wren_i      : in  std_ulogic; -- write enable
1440 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1441 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1442 
      ack_o       : out std_ulogic; -- transfer acknowledge
1443 
      -- clock generator --
1444 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1445 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1446 
      -- com lines --
1447 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1448 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1449 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1450 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1451 
      -- interrupt --
1452 48 zero_gravi 
      irq_o       : out std_ulogic -- transmission done interrupt
1453 2 zero_gravi 
    );
1454 
  end component;
1455 
 
1456 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1457 
  -- -------------------------------------------------------------------------------------------
1458 
  component neorv32_twi
1459 
    port (
1460 
      -- host access --
1461 
      clk_i       : in  std_ulogic; -- global clock line
1462 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1463 
      rden_i      : in  std_ulogic; -- read enable
1464 
      wren_i      : in  std_ulogic; -- write enable
1465 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1466 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1467 
      ack_o       : out std_ulogic; -- transfer acknowledge
1468 
      -- clock generator --
1469 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1470 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1471 
      -- com lines --
1472 
      twi_sda_io  : inout std_logic; -- serial data line
1473 
      twi_scl_io  : inout std_logic; -- serial clock line
1474 
      -- interrupt --
1475 48 zero_gravi 
      irq_o       : out std_ulogic -- transfer done IRQ
1476 2 zero_gravi 
    );
1477 
  end component;
1478 
 
1479 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1480 
  -- -------------------------------------------------------------------------------------------
1481 
  component neorv32_pwm
1482 
    port (
1483 
      -- host access --
1484 
      clk_i       : in  std_ulogic; -- global clock line
1485 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1486 
      rden_i      : in  std_ulogic; -- read enable
1487 
      wren_i      : in  std_ulogic; -- write enable
1488 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1489 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1490 
      ack_o       : out std_ulogic; -- transfer acknowledge
1491 
      -- clock generator --
1492 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1493 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1494 
      -- pwm output channels --
1495 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1496 
    );
1497 
  end component;
1498 
 
1499 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1500 
  -- -------------------------------------------------------------------------------------------
1501 
  component neorv32_trng
1502 
    port (
1503 
      -- host access --
1504 
      clk_i  : in  std_ulogic; -- global clock line
1505 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1506 
      rden_i : in  std_ulogic; -- read enable
1507 
      wren_i : in  std_ulogic; -- write enable
1508 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1509 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1510 
      ack_o  : out std_ulogic  -- transfer acknowledge
1511 
    );
1512 
  end component;
1513 
 
1514 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1515 
  -- -------------------------------------------------------------------------------------------
1516 
  component neorv32_wishbone
1517 
    generic (
1518 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1519 23 zero_gravi 
      -- Internal instruction memory --
1520 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1521 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1522 23 zero_gravi 
      -- Internal data memory --
1523 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1524 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1525 2 zero_gravi 
    );
1526 
    port (
1527 
      -- global control --
1528 39 zero_gravi 
      clk_i     : in  std_ulogic; -- global clock line
1529 
      rstn_i    : in  std_ulogic; -- global reset line, low-active
1530 2 zero_gravi 
      -- host access --
1531 39 zero_gravi 
      src_i     : in  std_ulogic; -- access type (0: data, 1:instruction)
1532 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1533 
      rden_i    : in  std_ulogic; -- read enable
1534 
      wren_i    : in  std_ulogic; -- write enable
1535 
      ben_i     : in  std_ulogic_vector(03 downto 0); -- byte write enable
1536 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1537 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1538 
      cancel_i  : in  std_ulogic; -- cancel current bus transaction
1539 
      lock_i    : in  std_ulogic; -- locked/exclusive bus access
1540 
      ack_o     : out std_ulogic; -- transfer acknowledge
1541 
      err_o     : out std_ulogic; -- transfer error
1542 
      priv_i    : in  std_ulogic_vector(1 downto 0); -- current CPU privilege level
1543 2 zero_gravi 
      -- wishbone interface --
1544 39 zero_gravi 
      wb_tag_o  : out std_ulogic_vector(2 downto 0); -- tag
1545 
      wb_adr_o  : out std_ulogic_vector(31 downto 0); -- address
1546 
      wb_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
1547 
      wb_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
1548 
      wb_we_o   : out std_ulogic; -- read/write
1549 
      wb_sel_o  : out std_ulogic_vector(03 downto 0); -- byte enable
1550 
      wb_stb_o  : out std_ulogic; -- strobe
1551 
      wb_cyc_o  : out std_ulogic; -- valid cycle
1552 
      wb_lock_o : out std_ulogic; -- locked/exclusive bus access
1553 
      wb_ack_i  : in  std_ulogic; -- transfer acknowledge
1554 
      wb_err_i  : in  std_ulogic  -- transfer error
1555 2 zero_gravi 
    );
1556 
  end component;
1557 
 
1558 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1559 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1560 47 zero_gravi 
  component neorv32_cfs
1561 
    generic (
1562 49 zero_gravi 
      CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000" -- custom CFS configuration generic
1563 23 zero_gravi 
    );
1564 34 zero_gravi 
    port (
1565 
      -- host access --
1566 
      clk_i       : in  std_ulogic; -- global clock line
1567 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1568 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1569 
      rden_i      : in  std_ulogic; -- read enable
1570 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1571 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1572 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1573 
      ack_o       : out std_ulogic; -- transfer acknowledge
1574 47 zero_gravi 
      err_o       : out std_ulogic; -- transfer error
1575 34 zero_gravi 
      -- clock generator --
1576 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1577 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1578 
      -- CPU state --
1579 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1580 
      -- interrupt --
1581 
      irq_o       : out std_ulogic; -- interrupt request
1582 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1583 
      -- custom io (conduit) --
1584 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0); -- custom inputs
1585 
      cfs_out_o   : out std_ulogic_vector(31 downto 0)  -- custom outputs
1586 34 zero_gravi 
    );
1587 
  end component;
1588 
 
1589 49 zero_gravi 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
1590 
  -- -------------------------------------------------------------------------------------------
1591 
  component neorv32_nco
1592 
    port (
1593 
      -- host access --
1594 
      clk_i       : in  std_ulogic; -- global clock line
1595 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1596 
      rden_i      : in  std_ulogic; -- read enable
1597 
      wren_i      : in  std_ulogic; -- write enable
1598 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1599 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1600 
      ack_o       : out std_ulogic; -- transfer acknowledge
1601 
      -- clock generator --
1602 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1603 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1604 
      -- NCO output --
1605 
      nco_o       : out std_ulogic_vector(02 downto 0)
1606 
    );
1607 
  end component;
1608 
 
1609 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1610 
  -- -------------------------------------------------------------------------------------------
1611 12 zero_gravi 
  component neorv32_sysinfo
1612 
    generic (
1613 
      -- General --
1614 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1615 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1616 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1617 23 zero_gravi 
      -- Internal Instruction memory --
1618 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1619 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1620 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1621 23 zero_gravi 
      -- Internal Data memory --
1622 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1623 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1624 
      -- Internal Cache memory --
1625 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1626 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1627 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1628 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1629 23 zero_gravi 
      -- External memory interface --
1630 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1631 12 zero_gravi 
      -- Processor peripherals --
1632 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1633 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1634 
      IO_UART_EN           : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
1635 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1636 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1637 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1638 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1639 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1640 49 zero_gravi 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
1641 
      IO_NCO_EN            : boolean := true    -- implement numerically-controlled oscillator (NCO)?
1642 12 zero_gravi 
    );
1643 
    port (
1644 
      -- host access --
1645 
      clk_i  : in  std_ulogic; -- global clock line
1646 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1647 
      rden_i : in  std_ulogic; -- read enable
1648 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1649 
      ack_o  : out std_ulogic  -- transfer acknowledge
1650 
    );
1651 
  end component;
1652 
 
1653 2 zero_gravi 
end neorv32_package;
1654 
 
1655 
package body neorv32_package is
1656 
 
1657 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1658 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1659 
  function index_size_f(input : natural) return natural is
1660 
  begin
1661 
    for i in 0 to natural'high loop
1662 
      if (2**i >= input) then
1663 
        return i;
1664 
      end if;
1665 
    end loop; -- i
1666 
    return 0;
1667 
  end function index_size_f;
1668 
 
1669 
  -- Function: Conditional select natural ---------------------------------------------------
1670 
  -- -------------------------------------------------------------------------------------------
1671 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1672 
  begin
1673 
    if (cond = true) then
1674 
      return val_t;
1675 
    else
1676 
      return val_f;
1677 
    end if;
1678 
  end function cond_sel_natural_f;
1679 
 
1680 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1681 
  -- -------------------------------------------------------------------------------------------
1682 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1683 
  begin
1684 
    if (cond = true) then
1685 
      return val_t;
1686 
    else
1687 
      return val_f;
1688 
    end if;
1689 
  end function cond_sel_stdulogicvector_f;
1690 
 
1691 
  -- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
1692 
  -- -------------------------------------------------------------------------------------------
1693 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1694 
  begin
1695 
    if (cond = true) then
1696 
      return '1';
1697 
    else
1698 
      return '0';
1699 
    end if;
1700 
  end function bool_to_ulogic_f;
1701 
 
1702 
  -- Function: OR all bits ------------------------------------------------------------------
1703 
  -- -------------------------------------------------------------------------------------------
1704 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1705 
    variable tmp_v : std_ulogic;
1706 
  begin
1707 
    tmp_v := a(a'low);
1708 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1709 
      for i in a'low+1 to a'high loop
1710 
        tmp_v := tmp_v or a(i);
1711 
      end loop; -- i
1712 
    end if;
1713 2 zero_gravi 
    return tmp_v;
1714 
  end function or_all_f;
1715 
 
1716 
  -- Function: AND all bits -----------------------------------------------------------------
1717 
  -- -------------------------------------------------------------------------------------------
1718 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1719 
    variable tmp_v : std_ulogic;
1720 
  begin
1721 
    tmp_v := a(a'low);
1722 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1723 
      for i in a'low+1 to a'high loop
1724 
        tmp_v := tmp_v and a(i);
1725 
      end loop; -- i
1726 
    end if;
1727 2 zero_gravi 
    return tmp_v;
1728 
  end function and_all_f;
1729 
 
1730 
  -- Function: XOR all bits -----------------------------------------------------------------
1731 
  -- -------------------------------------------------------------------------------------------
1732 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1733 
    variable tmp_v : std_ulogic;
1734 
  begin
1735 
    tmp_v := a(a'low);
1736 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1737 
      for i in a'low+1 to a'high loop
1738 
        tmp_v := tmp_v xor a(i);
1739 
      end loop; -- i
1740 
    end if;
1741 2 zero_gravi 
    return tmp_v;
1742 
  end function xor_all_f;
1743 
 
1744 
  -- Function: XNOR all bits ----------------------------------------------------------------
1745 
  -- -------------------------------------------------------------------------------------------
1746 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1747 
    variable tmp_v : std_ulogic;
1748 
  begin
1749 
    tmp_v := a(a'low);
1750 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1751 
      for i in a'low+1 to a'high loop
1752 
        tmp_v := tmp_v xnor a(i);
1753 
      end loop; -- i
1754 
    end if;
1755 2 zero_gravi 
    return tmp_v;
1756 
  end function xnor_all_f;
1757 
 
1758 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1759 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1760 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1761 
    variable output_v : character;
1762 
  begin
1763 
    case input is
1764 7 zero_gravi 
      when x"0"   => output_v := '0';
1765 
      when x"1"   => output_v := '1';
1766 
      when x"2"   => output_v := '2';
1767 
      when x"3"   => output_v := '3';
1768 
      when x"4"   => output_v := '4';
1769 
      when x"5"   => output_v := '5';
1770 
      when x"6"   => output_v := '6';
1771 
      when x"7"   => output_v := '7';
1772 
      when x"8"   => output_v := '8';
1773 
      when x"9"   => output_v := '9';
1774 
      when x"a"   => output_v := 'a';
1775 
      when x"b"   => output_v := 'b';
1776 
      when x"c"   => output_v := 'c';
1777 
      when x"d"   => output_v := 'd';
1778 
      when x"e"   => output_v := 'e';
1779 
      when x"f"   => output_v := 'f';
1780 6 zero_gravi 
      when others => output_v := '?';
1781 
    end case;
1782 
    return output_v;
1783 
  end function to_hexchar_f;
1784 
 
1785 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1786 
  -- -------------------------------------------------------------------------------------------
1787 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1788 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1789 
  begin
1790 
    case input is
1791 
      when '0'       => hex_value_v := x"0";
1792 
      when '1'       => hex_value_v := x"1";
1793 
      when '2'       => hex_value_v := x"2";
1794 
      when '3'       => hex_value_v := x"3";
1795 
      when '4'       => hex_value_v := x"4";
1796 
      when '5'       => hex_value_v := x"5";
1797 
      when '6'       => hex_value_v := x"6";
1798 
      when '7'       => hex_value_v := x"7";
1799 
      when '8'       => hex_value_v := x"8";
1800 
      when '9'       => hex_value_v := x"9";
1801 
      when 'a' | 'A' => hex_value_v := x"a";
1802 
      when 'b' | 'B' => hex_value_v := x"b";
1803 
      when 'c' | 'C' => hex_value_v := x"c";
1804 
      when 'd' | 'D' => hex_value_v := x"d";
1805 
      when 'e' | 'E' => hex_value_v := x"e";
1806 
      when 'f' | 'F' => hex_value_v := x"f";
1807 
      when others    => hex_value_v := (others => 'X');
1808 
    end case;
1809 
    return hex_value_v;
1810 
  end function hexchar_to_stdulogicvector_f;
1811 
 
1812 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1813 
  -- -------------------------------------------------------------------------------------------
1814 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1815 
    variable output_v : std_ulogic_vector(input'range);
1816 
  begin
1817 
    for i in 0 to input'length-1 loop
1818 
      output_v(input'length-i-1) := input(i);
1819 
    end loop; -- i
1820 
    return output_v;
1821 
  end function bit_rev_f;
1822 
 
1823 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1824 
  -- -------------------------------------------------------------------------------------------
1825 
  function is_power_of_two_f(input : natural) return boolean is
1826 
  begin
1827 38 zero_gravi 
    if (input = 1) then -- 2^0
1828 36 zero_gravi 
      return true;
1829 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
1830 
      return true;
1831 36 zero_gravi 
    else
1832 
      return false;
1833 
    end if;
1834 
  end function is_power_of_two_f;
1835 
 
1836 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
1837 
  -- -------------------------------------------------------------------------------------------
1838 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
1839 
    variable output_v : std_ulogic_vector(input'range);
1840 
  begin
1841 
    output_v(07 downto 00) := input(31 downto 24);
1842 
    output_v(15 downto 08) := input(23 downto 16);
1843 
    output_v(23 downto 16) := input(15 downto 08);
1844 
    output_v(31 downto 24) := input(07 downto 00);
1845 
    return output_v;
1846 
  end function bswap32_f;
1847 
 
1848 2 zero_gravi 
end neorv32_package;

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