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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Blame information for rev 50

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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
18 
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
21 
-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 41 zero_gravi 
  constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 40 zero_gravi 
 
55 47 zero_gravi 
  -- "critical" number of PMP regions --
56 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically
57 
  -- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle!
58 
  constant pmp_num_regions_critical_c : natural := 8;
59 
 
60 48 zero_gravi 
  -- Architecture Constants (do not modify!) ------------------------------------------------
61 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
62 47 zero_gravi 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
63 50 zero_gravi 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050107"; -- no touchy!
64 40 zero_gravi 
  constant pmp_max_r_c    : natural := 8; -- max PMP regions - FIXED!
65 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
66 42 zero_gravi 
  constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
67 27 zero_gravi 
 
68 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
69 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
70 
  function index_size_f(input : natural) return natural;
71 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
72 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
73 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
74 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
75 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
76 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
77 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
78 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
79 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
80 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
81 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
82 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
83 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
84 2 zero_gravi 
 
85 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
86 
  -- -------------------------------------------------------------------------------------------
87 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
88 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
89 49 zero_gravi 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
90 15 zero_gravi 
 
91 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
92 
  -- -------------------------------------------------------------------------------------------
93 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
94 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
95 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
96 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
97 2 zero_gravi 
 
98 23 zero_gravi 
  -- Internal Bootloader ROM --
99 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
100 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
101 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
102 23 zero_gravi 
 
103 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
104 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
105 47 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
106 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
107 2 zero_gravi 
 
108 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
109 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address
110 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
111 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
112 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";
113 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";
114 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";
115 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";
116 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";
117 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";
118 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";
119 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";
120 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";
121 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";
122 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";
123 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";
124 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";
125 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";
126 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";
127 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";
128 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";
129 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";
130 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";
131 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";
132 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";
133 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";
134 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";
135 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";
136 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";
137 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";
138 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";
139 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";
140 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";
141 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";
142 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";
143 
 
144 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
145 47 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address
146 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
147 23 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
148 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
149 2 zero_gravi 
 
150 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
151 47 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address
152 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
153 30 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
154 2 zero_gravi 
 
155 
  -- Watch Dog Timer (WDT) --
156 47 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address
157 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
158 23 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
159 2 zero_gravi 
 
160 
  -- Machine System Timer (MTIME) --
161 47 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address
162 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
163 23 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
164 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
165 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
166 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
167 2 zero_gravi 
 
168 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
169 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
170 
  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes
171 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
172 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
173 2 zero_gravi 
 
174 
  -- Serial Peripheral Interface (SPI) --
175 47 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
176 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
177 23 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
178 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
179 2 zero_gravi 
 
180 
  -- Two Wire Interface (TWI) --
181 47 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address
182 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
183 23 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
184 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
185 2 zero_gravi 
 
186 
  -- Pulse-Width Modulation Controller (PWM) --
187 47 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
188 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
189 23 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
190 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
191 2 zero_gravi 
 
192 49 zero_gravi 
  -- Numerically-Controlled Oscillator (NCO) --
193 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
194 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
195 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
196 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
197 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
198 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
199 
 
200 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
201 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
202 
  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes
203 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
204 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
205 
 
206 47 zero_gravi 
  -- reserved --
207 50 zero_gravi 
--constant reserved_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address
208 
--constant reserved_size_c      : natural := 2*4; -- module's address space in bytes
209 12 zero_gravi 
 
210 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
211 47 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
212 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
213 12 zero_gravi 
 
214 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
215 
  -- -------------------------------------------------------------------------------------------
216 
  -- register file --
217 49 zero_gravi 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
218 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
219 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
220 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
221 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
222 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
223 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
224 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
225 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
226 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
227 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
228 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
229 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
230 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
231 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
232 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
233 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
234 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
235 2 zero_gravi 
  -- alu --
236 49 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
237 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
238 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
239 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
240 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
241 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
242 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
243 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
244 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
245 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
246 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
247 2 zero_gravi 
  -- bus interface --
248 49 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
249 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
250 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
251 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
252 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
253 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
254 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
255 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
256 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
257 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
258 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
259 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
260 
  constant ctrl_bus_lock_c      : natural := 41; -- locked/exclusive bus access
261 26 zero_gravi 
  -- co-processors --
262 49 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 42; -- cp select ID lsb
263 
  constant ctrl_cp_id_hsb_c     : natural := 43; -- cp select ID hsb
264 39 zero_gravi 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
265 36 zero_gravi 
  -- current privilege level --
266 39 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
267 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
268 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
269 39 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
270 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
271 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
272 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
273 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
274 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
275 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
276 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
277 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
278 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
279 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
280 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
281 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
282 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
283 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
284 44 zero_gravi 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
285 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
286 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
287 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
288 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
289 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
290 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
291 47 zero_gravi 
  -- CPU status --
292 
  constant ctrl_sleep_c         : natural := 69; -- set when CPU is in sleep mode
293 2 zero_gravi 
  -- control bus size --
294 47 zero_gravi 
  constant ctrl_width_c         : natural := 70; -- control bus size
295 2 zero_gravi 
 
296 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
297 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
298 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
299 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
300 2 zero_gravi 
 
301 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
302 
  -- -------------------------------------------------------------------------------------------
303 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
304 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
305 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
306 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
307 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
308 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
309 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
310 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
311 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
312 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
313 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
314 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
315 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
316 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
317 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
318 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
319 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
320 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
321 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
322 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
323 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
324 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
325 2 zero_gravi 
 
326 
  -- RISC-V Opcodes -------------------------------------------------------------------------
327 
  -- -------------------------------------------------------------------------------------------
328 
  -- alu --
329 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
330 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
331 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
332 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
333 
  -- control flow --
334 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
335 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
336 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
337 
  -- memory access --
338 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
339 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
340 
  -- system/csr --
341 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
342 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
343 39 zero_gravi 
  -- atomic operations (A) --
344 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
345 2 zero_gravi 
 
346 
  -- RISC-V Funct3 --------------------------------------------------------------------------
347 
  -- -------------------------------------------------------------------------------------------
348 
  -- control flow --
349 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
350 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
351 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
352 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
353 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
354 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
355 
  -- memory access --
356 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
357 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
358 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
359 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
360 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
361 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
362 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
363 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
364 
  -- alu --
365 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
366 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
367 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
368 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
369 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
370 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
371 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
372 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
373 
  -- system/csr --
374 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
375 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
376 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
377 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
378 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
379 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
380 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
381 8 zero_gravi 
  -- fence --
382 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
383 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
384 2 zero_gravi 
 
385 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
386 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
387 
  -- system --
388 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
389 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
390 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
391 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
392 
 
393 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
394 
  -- -------------------------------------------------------------------------------------------
395 
  -- atomic operations --
396 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
397 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
398 
 
399 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
400 
  -- -------------------------------------------------------------------------------------------
401 41 zero_gravi 
  -- read/write CSRs --
402 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
403 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
404 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
405 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
406 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
407 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
408 29 zero_gravi 
  --
409 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
410 29 zero_gravi 
  --
411 42 zero_gravi 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
412 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
413 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
414 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
415 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
416 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
417 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
418 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
419 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
420 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
421 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
422 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
423 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
424 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
425 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
426 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
427 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
428 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
429 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
430 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
431 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
432 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
433 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
434 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
435 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
436 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
437 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
438 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
439 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
440 29 zero_gravi 
  --
441 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
442 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
443 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
444 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
445 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
446 29 zero_gravi 
  --
447 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
448 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
449 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
450 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
451 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
452 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
453 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
454 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
455 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
456 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
457 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
458 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
459 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
460 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
461 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
462 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
463 29 zero_gravi 
  --
464 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
465 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
466 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
467 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
468 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
469 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
470 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
471 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
472 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
473 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
474 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
475 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
476 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
477 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
478 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
479 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
480 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
481 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
482 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
483 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
484 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
485 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
486 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
487 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
488 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
489 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
490 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
491 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
492 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
493 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
494 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
495 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
496 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
497 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
498 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
499 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
500 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
501 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
502 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
503 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
504 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
505 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
506 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
507 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
508 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
509 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
510 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
511 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
512 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
513 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
514 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
515 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
516 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
517 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
518 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
519 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
520 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
521 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
522 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
523 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
524 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
525 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
526 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
527 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
528 29 zero_gravi 
  --
529 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
530 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
531 
  --
532 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
533 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
534 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
535 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
536 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
537 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
538 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
539 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
540 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
541 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
542 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
543 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
544 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
545 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
546 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
547 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
548 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
549 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
550 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
551 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
552 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
553 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
554 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
555 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
556 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
557 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
558 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
559 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
560 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
561 
  --
562 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
563 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
564 
  --
565 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
566 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
567 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
568 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
569 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
570 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
571 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
572 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
573 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
574 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
575 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
576 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
577 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
578 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
579 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
580 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
581 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
582 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
583 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
584 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
585 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
586 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
587 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
588 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
589 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
590 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
591 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
592 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
593 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
594 
 
595 41 zero_gravi 
  -- read-only CSRs --
596 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
597 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
598 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
599 29 zero_gravi 
  --
600 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
601 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
602 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
603 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
604 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
605 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
606 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
607 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
608 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
609 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
610 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
611 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
612 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
613 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
614 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
615 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
616 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
617 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
618 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
619 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
620 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
621 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
622 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
623 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
624 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
625 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
626 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
627 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
628 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
629 29 zero_gravi 
  --
630 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
631 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
632 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
633 29 zero_gravi 
  --
634 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
635 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
636 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
637 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
638 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
639 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
640 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
641 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
642 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
643 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
644 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
645 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
646 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
647 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
648 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
649 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
650 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
651 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
652 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
653 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
654 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
655 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
656 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
657 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
658 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
659 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
660 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
661 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
662 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
663 
  --
664 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
665 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
666 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
667 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
668 29 zero_gravi 
 
669 42 zero_gravi 
  -- custom read-only CSRs --
670 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
671 
 
672 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
673 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
674 49 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
675 
  constant cp_sel_atomic_c   : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
676 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
677 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
678 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "100"; -- reserved
679 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "101"; -- reserved
680 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "110"; -- reserved
681 
--constant cp_reserved_c     : std_ulogic_vector(2 downto 0) := "111"; -- reserved
682 2 zero_gravi 
 
683 
  -- ALU Function Codes ---------------------------------------------------------------------
684 
  -- -------------------------------------------------------------------------------------------
685 39 zero_gravi 
  -- arithmetic core --
686 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
687 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
688 
  -- logic core --
689 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
690 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
691 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
692 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
693 
  -- function select (actual alu result) --
694 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
695 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
696 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
697 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
698 2 zero_gravi 
 
699 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
700 
  -- -------------------------------------------------------------------------------------------
701 48 zero_gravi 
  -- RISC-V compliant sync. exceptions --
702 
  constant trap_ima_c    : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
703 
  constant trap_iba_c    : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
704 
  constant trap_iil_c    : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
705 
  constant trap_brk_c    : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
706 
  constant trap_lma_c    : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
707 
  constant trap_lbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
708 
  constant trap_sma_c    : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
709 
  constant trap_sbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
710 
  constant trap_uenv_c   : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
711 
  constant trap_menv_c   : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
712 
  -- RISC-V compliant interrupts (async. exceptions) --
713 
  constant trap_msi_c    : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
714 
  constant trap_mti_c    : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
715 
  constant trap_mei_c    : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
716 
  -- NEORV32-specific (custom) interrupts (async. exceptions) --
717 
  constant trap_reset_c  : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0:  hardware reset
718 
  constant trap_firq0_c  : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
719 
  constant trap_firq1_c  : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
720 
  constant trap_firq2_c  : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
721 
  constant trap_firq3_c  : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
722 
  constant trap_firq4_c  : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
723 
  constant trap_firq5_c  : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
724 
  constant trap_firq6_c  : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
725 
  constant trap_firq7_c  : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
726 
  constant trap_firq8_c  : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
727 
  constant trap_firq9_c  : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
728 
  constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
729 
  constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
730 
  constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
731 
  constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
732 
  constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
733 
  constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
734 12 zero_gravi 
 
735 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
736 
  -- -------------------------------------------------------------------------------------------
737 
  -- exception source bits --
738 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
739 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
740 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
741 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
742 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
743 
  constant exception_break_c     : natural :=  5; -- breakpoint
744 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
745 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
746 
  constant exception_saccess_c   : natural :=  8; -- store access fault
747 
  constant exception_laccess_c   : natural :=  9; -- load access fault
748 14 zero_gravi 
  --
749 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
750 2 zero_gravi 
  -- interrupt source bits --
751 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
752 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
753 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
754 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
755 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
756 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
757 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
758 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
759 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
760 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
761 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
762 48 zero_gravi 
  constant interrupt_firq_8_c    : natural := 11; -- fast interrupt channel 8
763 
  constant interrupt_firq_9_c    : natural := 12; -- fast interrupt channel 9
764 
  constant interrupt_firq_10_c   : natural := 13; -- fast interrupt channel 10
765 
  constant interrupt_firq_11_c   : natural := 14; -- fast interrupt channel 11
766 
  constant interrupt_firq_12_c   : natural := 15; -- fast interrupt channel 12
767 
  constant interrupt_firq_13_c   : natural := 16; -- fast interrupt channel 13
768 
  constant interrupt_firq_14_c   : natural := 17; -- fast interrupt channel 14
769 
  constant interrupt_firq_15_c   : natural := 18; -- fast interrupt channel 15
770 14 zero_gravi 
  --
771 48 zero_gravi 
  constant interrupt_width_c     : natural := 19; -- length of this list in bits
772 2 zero_gravi 
 
773 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
774 
  -- -------------------------------------------------------------------------------------------
775 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
776 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
777 15 zero_gravi 
 
778 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
779 
  -- -------------------------------------------------------------------------------------------
780 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
781 
  constant hpmcnt_event_never_c   : natural := 1;
782 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
783 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
784 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
785 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
786 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
787 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
788 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
789 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
790 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
791 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
792 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
793 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
794 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
795 42 zero_gravi 
  --
796 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
797 42 zero_gravi 
 
798 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
799 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
800 
  constant clk_div2_c    : natural := 0;
801 
  constant clk_div4_c    : natural := 1;
802 
  constant clk_div8_c    : natural := 2;
803 
  constant clk_div64_c   : natural := 3;
804 
  constant clk_div128_c  : natural := 4;
805 
  constant clk_div1024_c : natural := 5;
806 
  constant clk_div2048_c : natural := 6;
807 
  constant clk_div4096_c : natural := 7;
808 
 
809 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
810 
  -- -------------------------------------------------------------------------------------------
811 
  component neorv32_top
812 
    generic (
813 
      -- General --
814 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
815 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
816 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
817 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
818 2 zero_gravi 
      -- RISC-V CPU Extensions --
819 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
820 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
821 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
822 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
823 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
824 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
825 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
826 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
827 19 zero_gravi 
      -- Extension Options --
828 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
829 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
830 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
831 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
832 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
833 
      -- Hardware Performance Monitors (HPM) --
834 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
835 23 zero_gravi 
      -- Internal Instruction memory --
836 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
837 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
838 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
839 23 zero_gravi 
      -- Internal Data memory --
840 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
841 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
842 41 zero_gravi 
      -- Internal Cache memory --
843 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
844 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
845 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
846 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
847 23 zero_gravi 
      -- External memory interface --
848 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
849 2 zero_gravi 
      -- Processor peripherals --
850 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
851 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
852 50 zero_gravi 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
853 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
854 44 zero_gravi 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
855 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
856 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
857 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
858 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
859 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
860 49 zero_gravi 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
861 
      IO_NCO_EN                    : boolean := true    -- implement numerically-controlled oscillator (NCO)?
862 2 zero_gravi 
    );
863 
    port (
864 
      -- Global control --
865 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
866 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
867 49 zero_gravi 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
868 36 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(02 downto 0); -- tag
869 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
870 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
871 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
872 
      wb_we_o     : out std_ulogic; -- read/write
873 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
874 
      wb_stb_o    : out std_ulogic; -- strobe
875 
      wb_cyc_o    : out std_ulogic; -- valid cycle
876 39 zero_gravi 
      wb_lock_o   : out std_ulogic; -- locked/exclusive bus access
877 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
878 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
879 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
880 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
881 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
882 49 zero_gravi 
      -- GPIO (available if IO_GPIO_EN = true) --
883 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
884 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
885 50 zero_gravi 
      -- primary UART0 (available if IO_UART0_EN = true) --
886 
      uart0_txd_o : out std_ulogic; -- UART0 send data
887 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
888 
      -- secondary UART1 (available if IO_UART1_EN = true) --
889 
      uart1_txd_o : out std_ulogic; -- UART1 send data
890 
      uart1_rxd_i : in  std_ulogic := '0'; -- UART1 receive data
891 49 zero_gravi 
      -- SPI (available if IO_SPI_EN = true) --
892 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
893 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
894 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
895 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
896 49 zero_gravi 
      -- TWI (available if IO_TWI_EN = true) --
897 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
898 
      twi_scl_io  : inout std_logic; -- twi serial clock line
899 49 zero_gravi 
      -- PWM (available if IO_PWM_EN = true) --
900 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
901 47 zero_gravi 
      -- Custom Functions Subsystem IO --
902 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs
903 
      cfs_out_o   : out std_ulogic_vector(31 downto 0); -- custom CSF outputs
904 49 zero_gravi 
      -- NCO output (available if IO_NCO_EN = true) --
905 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
906 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
907 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
908 2 zero_gravi 
      -- Interrupts --
909 50 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
910 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
911 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
912 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
913 2 zero_gravi 
    );
914 
  end component;
915 
 
916 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
917 
  -- -------------------------------------------------------------------------------------------
918 
  component neorv32_cpu
919 
    generic (
920 
      -- General --
921 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
922 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
923 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
924 4 zero_gravi 
      -- RISC-V CPU Extensions --
925 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
926 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
927 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
928 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
929 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
930 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
931 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
932 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
933 19 zero_gravi 
      -- Extension Options --
934 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
935 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
936 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
937 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
938 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
939 
      -- Hardware Performance Monitors (HPM) --
940 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
941 4 zero_gravi 
    );
942 
    port (
943 
      -- global control --
944 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
945 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
946 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
947 12 zero_gravi 
      -- instruction bus interface --
948 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
949 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
950 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
951 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
952 
      i_bus_we_o     : out std_ulogic; -- write enable
953 
      i_bus_re_o     : out std_ulogic; -- read enable
954 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
955 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
956 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
957 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
958 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
959 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
960 12 zero_gravi 
      -- data bus interface --
961 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
962 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
963 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
964 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
965 
      d_bus_we_o     : out std_ulogic; -- write enable
966 
      d_bus_re_o     : out std_ulogic; -- read enable
967 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
968 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
969 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
970 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
971 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
972 39 zero_gravi 
      d_bus_lock_o   : out std_ulogic; -- locked/exclusive access
973 11 zero_gravi 
      -- system time input from MTIME --
974 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
975 
      -- interrupts (risc-v compliant) --
976 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
977 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
978 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
979 
      -- fast interrupts (custom) --
980 48 zero_gravi 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
981 
      firq_ack_o     : out std_ulogic_vector(15 downto 0)
982 4 zero_gravi 
    );
983 
  end component;
984 
 
985 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
986 
  -- -------------------------------------------------------------------------------------------
987 
  component neorv32_cpu_control
988 
    generic (
989 
      -- General --
990 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
991 12 zero_gravi 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
992 2 zero_gravi 
      -- RISC-V CPU Extensions --
993 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
994 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
995 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
996 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
997 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
998 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
999 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
1000 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
1001 15 zero_gravi 
      -- Physical memory protection (PMP) --
1002 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0; -- number of regions (0..64)
1003 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1004 
      -- Hardware Performance Monitors (HPM) --
1005 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0      -- number of implemented HPM counters (0..29)
1006 2 zero_gravi 
    );
1007 
    port (
1008 
      -- global control --
1009 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1010 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1011 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1012 
      -- status input --
1013 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
1014 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
1015 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
1016 2 zero_gravi 
      -- data input --
1017 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1018 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
1019 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
1020 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1021 2 zero_gravi 
      -- data output --
1022 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1023 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1024 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
1025 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1026 14 zero_gravi 
      -- interrupts (risc-v compliant) --
1027 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
1028 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
1029 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
1030 14 zero_gravi 
      -- fast interrupts (custom) --
1031 48 zero_gravi 
      firq_i        : in  std_ulogic_vector(15 downto 0);
1032 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
1033 11 zero_gravi 
      -- system time input from MTIME --
1034 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
1035 15 zero_gravi 
      -- physical memory protection --
1036 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
1037 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
1038 2 zero_gravi 
      -- bus access exceptions --
1039 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
1040 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
1041 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
1042 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1043 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1044 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1045 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1046 2 zero_gravi 
    );
1047 
  end component;
1048 
 
1049 
  -- Component: CPU Register File -----------------------------------------------------------
1050 
  -- -------------------------------------------------------------------------------------------
1051 
  component neorv32_cpu_regfile
1052 
    generic (
1053 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1054 
    );
1055 
    port (
1056 
      -- global control --
1057 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1058 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1059 
      -- data input --
1060 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1061 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1062 
      -- data output --
1063 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1064 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1065 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1066 2 zero_gravi 
    );
1067 
  end component;
1068 
 
1069 
  -- Component: CPU ALU ---------------------------------------------------------------------
1070 
  -- -------------------------------------------------------------------------------------------
1071 
  component neorv32_cpu_alu
1072 11 zero_gravi 
    generic (
1073 34 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
1074 
      FAST_SHIFT_EN         : boolean := false -- use barrel shifter for shift operations
1075 11 zero_gravi 
    );
1076 2 zero_gravi 
    port (
1077 
      -- global control --
1078 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1079 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1080 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1081 
      -- data input --
1082 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1083 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1084 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1085 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1086 
      -- data output --
1087 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1088 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1089 2 zero_gravi 
      -- co-processor interface --
1090 49 zero_gravi 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
1091 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
1092 
      cp_result_i : in  cp_data_if_t; -- co-processor result
1093 2 zero_gravi 
      -- status --
1094 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1095 
    );
1096 
  end component;
1097 
 
1098 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1099 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1100 
  component neorv32_cpu_cp_muldiv
1101 19 zero_gravi 
    generic (
1102 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1103 
    );
1104 2 zero_gravi 
    port (
1105 
      -- global control --
1106 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1107 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1108 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1109 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1110 2 zero_gravi 
      -- data input --
1111 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1112 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1113 
      -- result and status --
1114 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1115 
      valid_o : out std_ulogic -- data output valid
1116 
    );
1117 
  end component;
1118 
 
1119 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1120 
  -- -------------------------------------------------------------------------------------------
1121 
  component neorv32_cpu_cp_bitmanip
1122 
    port (
1123 
      -- global control --
1124 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1125 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1126 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1127 
      start_i : in  std_ulogic; -- trigger operation
1128 
      -- data input --
1129 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1130 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1131 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1132 
      -- result and status --
1133 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1134 
      valid_o : out std_ulogic -- data output valid
1135 
    );
1136 
  end component;
1137 
 
1138 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1139 
  -- -------------------------------------------------------------------------------------------
1140 
  component neorv32_cpu_bus
1141 
    generic (
1142 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1143 15 zero_gravi 
      -- Physical memory protection (PMP) --
1144 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1145 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1146 41 zero_gravi 
      -- Bus Timeout --
1147 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1148 2 zero_gravi 
    );
1149 
    port (
1150 
      -- global control --
1151 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1152 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1153 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1154 
      -- cpu instruction fetch interface --
1155 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1156 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1157 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1158 
      --
1159 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1160 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1161 
      -- cpu data access interface --
1162 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1163 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1164 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1165 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1166 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1167 
      --
1168 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1169 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1170 
      be_load_o      : out std_ulogic; -- bus error on load data access
1171 
      be_store_o     : out std_ulogic; -- bus error on store data access
1172 15 zero_gravi 
      -- physical memory protection --
1173 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1174 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1175 12 zero_gravi 
      -- instruction bus --
1176 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1177 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1178 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1179 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1180 
      i_bus_we_o     : out std_ulogic; -- write enable
1181 
      i_bus_re_o     : out std_ulogic; -- read enable
1182 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1183 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1184 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1185 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1186 39 zero_gravi 
      i_bus_lock_o   : out std_ulogic; -- locked/exclusive access
1187 12 zero_gravi 
      -- data bus --
1188 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1189 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1190 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1191 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1192 
      d_bus_we_o     : out std_ulogic; -- write enable
1193 
      d_bus_re_o     : out std_ulogic; -- read enable
1194 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1195 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1196 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1197 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1198 
      d_bus_lock_o   : out std_ulogic  -- locked/exclusive access
1199 2 zero_gravi 
    );
1200 
  end component;
1201 
 
1202 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1203 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1204 45 zero_gravi 
  component neorv32_icache
1205 41 zero_gravi 
    generic (
1206 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1207 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1208 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1209 41 zero_gravi 
    );
1210 
    port (
1211 
      -- global control --
1212 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1213 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1214 
      clear_i       : in  std_ulogic; -- cache clear
1215 
      -- host controller interface --
1216 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1217 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1218 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1219 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1220 
      host_we_i     : in  std_ulogic; -- write enable
1221 
      host_re_i     : in  std_ulogic; -- read enable
1222 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1223 
      host_lock_i   : in  std_ulogic; -- locked/exclusive access
1224 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1225 
      host_err_o    : out std_ulogic; -- bus transfer error
1226 
      -- peripheral bus interface --
1227 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1228 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1229 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1230 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1231 
      bus_we_o      : out std_ulogic; -- write enable
1232 
      bus_re_o      : out std_ulogic; -- read enable
1233 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1234 
      bus_lock_o    : out std_ulogic; -- locked/exclusive access
1235 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1236 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1237 
    );
1238 
  end component;
1239 
 
1240 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1241 
  -- -------------------------------------------------------------------------------------------
1242 
  component neorv32_busswitch
1243 
    generic (
1244 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1245 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1246 
    );
1247 
    port (
1248 
      -- global control --
1249 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1250 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1251 
      -- controller interface a --
1252 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1253 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1254 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1255 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1256 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1257 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1258 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1259 39 zero_gravi 
      ca_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1260 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1261 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1262 
      -- controller interface b --
1263 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1264 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1265 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1266 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1267 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1268 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1269 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1270 39 zero_gravi 
      cb_bus_lock_i   : in  std_ulogic; -- locked/exclusive access
1271 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1272 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1273 
      -- peripheral bus --
1274 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1275 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1276 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1277 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1278 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1279 
      p_bus_we_o      : out std_ulogic; -- write enable
1280 
      p_bus_re_o      : out std_ulogic; -- read enable
1281 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1282 39 zero_gravi 
      p_bus_lock_o    : out std_ulogic; -- locked/exclusive access
1283 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1284 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1285 
    );
1286 
  end component;
1287 
 
1288 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1289 
  -- -------------------------------------------------------------------------------------------
1290 
  component neorv32_cpu_decompressor
1291 
    port (
1292 
      -- instruction input --
1293 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1294 
      -- instruction output --
1295 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1296 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1297 
    );
1298 
  end component;
1299 
 
1300 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1301 
  -- -------------------------------------------------------------------------------------------
1302 
  component neorv32_imem
1303 
    generic (
1304 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1305 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1306 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1307 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1308 2 zero_gravi 
    );
1309 
    port (
1310 
      clk_i  : in  std_ulogic; -- global clock line
1311 
      rden_i : in  std_ulogic; -- read enable
1312 
      wren_i : in  std_ulogic; -- write enable
1313 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1314 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1315 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1316 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1317 
      ack_o  : out std_ulogic -- transfer acknowledge
1318 
    );
1319 
  end component;
1320 
 
1321 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1322 
  -- -------------------------------------------------------------------------------------------
1323 
  component neorv32_dmem
1324 
    generic (
1325 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1326 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1327 
    );
1328 
    port (
1329 
      clk_i  : in  std_ulogic; -- global clock line
1330 
      rden_i : in  std_ulogic; -- read enable
1331 
      wren_i : in  std_ulogic; -- write enable
1332 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1333 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1334 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1335 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1336 
      ack_o  : out std_ulogic -- transfer acknowledge
1337 
    );
1338 
  end component;
1339 
 
1340 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1341 
  -- -------------------------------------------------------------------------------------------
1342 
  component neorv32_boot_rom
1343 23 zero_gravi 
    generic (
1344 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1345 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1346 
    );
1347 2 zero_gravi 
    port (
1348 
      clk_i  : in  std_ulogic; -- global clock line
1349 
      rden_i : in  std_ulogic; -- read enable
1350 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1351 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1352 
      ack_o  : out std_ulogic -- transfer acknowledge
1353 
    );
1354 
  end component;
1355 
 
1356 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1357 
  -- -------------------------------------------------------------------------------------------
1358 
  component neorv32_mtime
1359 
    port (
1360 
      -- host access --
1361 
      clk_i     : in  std_ulogic; -- global clock line
1362 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1363 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1364 
      rden_i    : in  std_ulogic; -- read enable
1365 
      wren_i    : in  std_ulogic; -- write enable
1366 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1367 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1368 
      ack_o     : out std_ulogic; -- transfer acknowledge
1369 11 zero_gravi 
      -- time output for CPU --
1370 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1371 2 zero_gravi 
      -- interrupt --
1372 
      irq_o     : out std_ulogic  -- interrupt request
1373 
    );
1374 
  end component;
1375 
 
1376 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1377 
  -- -------------------------------------------------------------------------------------------
1378 
  component neorv32_gpio
1379 
    port (
1380 
      -- host access --
1381 
      clk_i  : in  std_ulogic; -- global clock line
1382 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1383 
      rden_i : in  std_ulogic; -- read enable
1384 
      wren_i : in  std_ulogic; -- write enable
1385 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1386 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1387 
      ack_o  : out std_ulogic; -- transfer acknowledge
1388 
      -- parallel io --
1389 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1390 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1391 2 zero_gravi 
      -- interrupt --
1392 
      irq_o  : out std_ulogic
1393 
    );
1394 
  end component;
1395 
 
1396 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1397 
  -- -------------------------------------------------------------------------------------------
1398 
  component neorv32_wdt
1399 
    port (
1400 
      -- host access --
1401 
      clk_i       : in  std_ulogic; -- global clock line
1402 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1403 
      rden_i      : in  std_ulogic; -- read enable
1404 
      wren_i      : in  std_ulogic; -- write enable
1405 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1406 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1407 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1408 
      ack_o       : out std_ulogic; -- transfer acknowledge
1409 
      -- clock generator --
1410 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1411 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1412 
      -- timeout event --
1413 
      irq_o       : out std_ulogic; -- timeout IRQ
1414 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1415 
    );
1416 
  end component;
1417 
 
1418 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1419 
  -- -------------------------------------------------------------------------------------------
1420 
  component neorv32_uart
1421 50 zero_gravi 
    generic (
1422 
      UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
1423 
    );
1424 2 zero_gravi 
    port (
1425 
      -- host access --
1426 
      clk_i       : in  std_ulogic; -- global clock line
1427 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1428 
      rden_i      : in  std_ulogic; -- read enable
1429 
      wren_i      : in  std_ulogic; -- write enable
1430 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1431 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1432 
      ack_o       : out std_ulogic; -- transfer acknowledge
1433 
      -- clock generator --
1434 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1435 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1436 
      -- com lines --
1437 
      uart_txd_o  : out std_ulogic;
1438 
      uart_rxd_i  : in  std_ulogic;
1439 
      -- interrupts --
1440 48 zero_gravi 
      irq_rxd_o   : out std_ulogic; -- uart data received interrupt
1441 
      irq_txd_o   : out std_ulogic  -- uart transmission done interrupt
1442 2 zero_gravi 
    );
1443 
  end component;
1444 
 
1445 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1446 
  -- -------------------------------------------------------------------------------------------
1447 
  component neorv32_spi
1448 
    port (
1449 
      -- host access --
1450 
      clk_i       : in  std_ulogic; -- global clock line
1451 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1452 
      rden_i      : in  std_ulogic; -- read enable
1453 
      wren_i      : in  std_ulogic; -- write enable
1454 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1455 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1456 
      ack_o       : out std_ulogic; -- transfer acknowledge
1457 
      -- clock generator --
1458 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1459 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1460 
      -- com lines --
1461 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1462 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1463 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1464 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1465 
      -- interrupt --
1466 48 zero_gravi 
      irq_o       : out std_ulogic -- transmission done interrupt
1467 2 zero_gravi 
    );
1468 
  end component;
1469 
 
1470 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1471 
  -- -------------------------------------------------------------------------------------------
1472 
  component neorv32_twi
1473 
    port (
1474 
      -- host access --
1475 
      clk_i       : in  std_ulogic; -- global clock line
1476 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1477 
      rden_i      : in  std_ulogic; -- read enable
1478 
      wren_i      : in  std_ulogic; -- write enable
1479 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1480 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1481 
      ack_o       : out std_ulogic; -- transfer acknowledge
1482 
      -- clock generator --
1483 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1484 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1485 
      -- com lines --
1486 
      twi_sda_io  : inout std_logic; -- serial data line
1487 
      twi_scl_io  : inout std_logic; -- serial clock line
1488 
      -- interrupt --
1489 48 zero_gravi 
      irq_o       : out std_ulogic -- transfer done IRQ
1490 2 zero_gravi 
    );
1491 
  end component;
1492 
 
1493 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1494 
  -- -------------------------------------------------------------------------------------------
1495 
  component neorv32_pwm
1496 
    port (
1497 
      -- host access --
1498 
      clk_i       : in  std_ulogic; -- global clock line
1499 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1500 
      rden_i      : in  std_ulogic; -- read enable
1501 
      wren_i      : in  std_ulogic; -- write enable
1502 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1503 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1504 
      ack_o       : out std_ulogic; -- transfer acknowledge
1505 
      -- clock generator --
1506 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1507 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1508 
      -- pwm output channels --
1509 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1510 
    );
1511 
  end component;
1512 
 
1513 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1514 
  -- -------------------------------------------------------------------------------------------
1515 
  component neorv32_trng
1516 
    port (
1517 
      -- host access --
1518 
      clk_i  : in  std_ulogic; -- global clock line
1519 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1520 
      rden_i : in  std_ulogic; -- read enable
1521 
      wren_i : in  std_ulogic; -- write enable
1522 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1523 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1524 
      ack_o  : out std_ulogic  -- transfer acknowledge
1525 
    );
1526 
  end component;
1527 
 
1528 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1529 
  -- -------------------------------------------------------------------------------------------
1530 
  component neorv32_wishbone
1531 
    generic (
1532 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1533 23 zero_gravi 
      -- Internal instruction memory --
1534 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1535 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1536 23 zero_gravi 
      -- Internal data memory --
1537 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1538 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1539 2 zero_gravi 
    );
1540 
    port (
1541 
      -- global control --
1542 39 zero_gravi 
      clk_i     : in  std_ulogic; -- global clock line
1543 
      rstn_i    : in  std_ulogic; -- global reset line, low-active
1544 2 zero_gravi 
      -- host access --
1545 39 zero_gravi 
      src_i     : in  std_ulogic; -- access type (0: data, 1:instruction)
1546 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1547 
      rden_i    : in  std_ulogic; -- read enable
1548 
      wren_i    : in  std_ulogic; -- write enable
1549 
      ben_i     : in  std_ulogic_vector(03 downto 0); -- byte write enable
1550 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1551 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1552 
      cancel_i  : in  std_ulogic; -- cancel current bus transaction
1553 
      lock_i    : in  std_ulogic; -- locked/exclusive bus access
1554 
      ack_o     : out std_ulogic; -- transfer acknowledge
1555 
      err_o     : out std_ulogic; -- transfer error
1556 
      priv_i    : in  std_ulogic_vector(1 downto 0); -- current CPU privilege level
1557 2 zero_gravi 
      -- wishbone interface --
1558 39 zero_gravi 
      wb_tag_o  : out std_ulogic_vector(2 downto 0); -- tag
1559 
      wb_adr_o  : out std_ulogic_vector(31 downto 0); -- address
1560 
      wb_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
1561 
      wb_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
1562 
      wb_we_o   : out std_ulogic; -- read/write
1563 
      wb_sel_o  : out std_ulogic_vector(03 downto 0); -- byte enable
1564 
      wb_stb_o  : out std_ulogic; -- strobe
1565 
      wb_cyc_o  : out std_ulogic; -- valid cycle
1566 
      wb_lock_o : out std_ulogic; -- locked/exclusive bus access
1567 
      wb_ack_i  : in  std_ulogic; -- transfer acknowledge
1568 
      wb_err_i  : in  std_ulogic  -- transfer error
1569 2 zero_gravi 
    );
1570 
  end component;
1571 
 
1572 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1573 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1574 47 zero_gravi 
  component neorv32_cfs
1575 
    generic (
1576 49 zero_gravi 
      CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000" -- custom CFS configuration generic
1577 23 zero_gravi 
    );
1578 34 zero_gravi 
    port (
1579 
      -- host access --
1580 
      clk_i       : in  std_ulogic; -- global clock line
1581 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1582 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1583 
      rden_i      : in  std_ulogic; -- read enable
1584 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1585 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1586 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1587 
      ack_o       : out std_ulogic; -- transfer acknowledge
1588 
      -- clock generator --
1589 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1590 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1591 
      -- CPU state --
1592 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1593 
      -- interrupt --
1594 
      irq_o       : out std_ulogic; -- interrupt request
1595 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1596 
      -- custom io (conduit) --
1597 
      cfs_in_i    : in  std_ulogic_vector(31 downto 0); -- custom inputs
1598 
      cfs_out_o   : out std_ulogic_vector(31 downto 0)  -- custom outputs
1599 34 zero_gravi 
    );
1600 
  end component;
1601 
 
1602 49 zero_gravi 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
1603 
  -- -------------------------------------------------------------------------------------------
1604 
  component neorv32_nco
1605 
    port (
1606 
      -- host access --
1607 
      clk_i       : in  std_ulogic; -- global clock line
1608 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1609 
      rden_i      : in  std_ulogic; -- read enable
1610 
      wren_i      : in  std_ulogic; -- write enable
1611 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1612 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1613 
      ack_o       : out std_ulogic; -- transfer acknowledge
1614 
      -- clock generator --
1615 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1616 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1617 
      -- NCO output --
1618 
      nco_o       : out std_ulogic_vector(02 downto 0)
1619 
    );
1620 
  end component;
1621 
 
1622 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1623 
  -- -------------------------------------------------------------------------------------------
1624 12 zero_gravi 
  component neorv32_sysinfo
1625 
    generic (
1626 
      -- General --
1627 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1628 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1629 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1630 23 zero_gravi 
      -- Internal Instruction memory --
1631 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1632 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1633 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1634 23 zero_gravi 
      -- Internal Data memory --
1635 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1636 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1637 
      -- Internal Cache memory --
1638 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1639 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1640 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1641 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1642 23 zero_gravi 
      -- External memory interface --
1643 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1644 12 zero_gravi 
      -- Processor peripherals --
1645 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1646 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1647 50 zero_gravi 
      IO_UART0_EN          : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
1648 
      IO_UART1_EN          : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
1649 44 zero_gravi 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1650 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1651 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1652 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1653 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1654 49 zero_gravi 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
1655 
      IO_NCO_EN            : boolean := true    -- implement numerically-controlled oscillator (NCO)?
1656 12 zero_gravi 
    );
1657 
    port (
1658 
      -- host access --
1659 
      clk_i  : in  std_ulogic; -- global clock line
1660 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1661 
      rden_i : in  std_ulogic; -- read enable
1662 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1663 
      ack_o  : out std_ulogic  -- transfer acknowledge
1664 
    );
1665 
  end component;
1666 
 
1667 2 zero_gravi 
end neorv32_package;
1668 
 
1669 
package body neorv32_package is
1670 
 
1671 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1672 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1673 
  function index_size_f(input : natural) return natural is
1674 
  begin
1675 
    for i in 0 to natural'high loop
1676 
      if (2**i >= input) then
1677 
        return i;
1678 
      end if;
1679 
    end loop; -- i
1680 
    return 0;
1681 
  end function index_size_f;
1682 
 
1683 
  -- Function: Conditional select natural ---------------------------------------------------
1684 
  -- -------------------------------------------------------------------------------------------
1685 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1686 
  begin
1687 
    if (cond = true) then
1688 
      return val_t;
1689 
    else
1690 
      return val_f;
1691 
    end if;
1692 
  end function cond_sel_natural_f;
1693 
 
1694 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1695 
  -- -------------------------------------------------------------------------------------------
1696 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1697 
  begin
1698 
    if (cond = true) then
1699 
      return val_t;
1700 
    else
1701 
      return val_f;
1702 
    end if;
1703 
  end function cond_sel_stdulogicvector_f;
1704 
 
1705 50 zero_gravi 
  -- Function: Conditional select string ----------------------------------------------------
1706 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1707 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
1708 
  begin
1709 
    if (cond = true) then
1710 
      return val_t;
1711 
    else
1712 
      return val_f;
1713 
    end if;
1714 
  end function cond_sel_string_f;
1715 
 
1716 
  -- Function: Convert bool to std_ulogic ---------------------------------------------------
1717 
  -- -------------------------------------------------------------------------------------------
1718 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1719 
  begin
1720 
    if (cond = true) then
1721 
      return '1';
1722 
    else
1723 
      return '0';
1724 
    end if;
1725 
  end function bool_to_ulogic_f;
1726 
 
1727 
  -- Function: OR all bits ------------------------------------------------------------------
1728 
  -- -------------------------------------------------------------------------------------------
1729 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1730 
    variable tmp_v : std_ulogic;
1731 
  begin
1732 
    tmp_v := a(a'low);
1733 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1734 
      for i in a'low+1 to a'high loop
1735 
        tmp_v := tmp_v or a(i);
1736 
      end loop; -- i
1737 
    end if;
1738 2 zero_gravi 
    return tmp_v;
1739 
  end function or_all_f;
1740 
 
1741 
  -- Function: AND all bits -----------------------------------------------------------------
1742 
  -- -------------------------------------------------------------------------------------------
1743 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1744 
    variable tmp_v : std_ulogic;
1745 
  begin
1746 
    tmp_v := a(a'low);
1747 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1748 
      for i in a'low+1 to a'high loop
1749 
        tmp_v := tmp_v and a(i);
1750 
      end loop; -- i
1751 
    end if;
1752 2 zero_gravi 
    return tmp_v;
1753 
  end function and_all_f;
1754 
 
1755 
  -- Function: XOR all bits -----------------------------------------------------------------
1756 
  -- -------------------------------------------------------------------------------------------
1757 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1758 
    variable tmp_v : std_ulogic;
1759 
  begin
1760 
    tmp_v := a(a'low);
1761 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1762 
      for i in a'low+1 to a'high loop
1763 
        tmp_v := tmp_v xor a(i);
1764 
      end loop; -- i
1765 
    end if;
1766 2 zero_gravi 
    return tmp_v;
1767 
  end function xor_all_f;
1768 
 
1769 
  -- Function: XNOR all bits ----------------------------------------------------------------
1770 
  -- -------------------------------------------------------------------------------------------
1771 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1772 
    variable tmp_v : std_ulogic;
1773 
  begin
1774 
    tmp_v := a(a'low);
1775 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1776 
      for i in a'low+1 to a'high loop
1777 
        tmp_v := tmp_v xnor a(i);
1778 
      end loop; -- i
1779 
    end if;
1780 2 zero_gravi 
    return tmp_v;
1781 
  end function xnor_all_f;
1782 
 
1783 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1784 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1785 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1786 
    variable output_v : character;
1787 
  begin
1788 
    case input is
1789 7 zero_gravi 
      when x"0"   => output_v := '0';
1790 
      when x"1"   => output_v := '1';
1791 
      when x"2"   => output_v := '2';
1792 
      when x"3"   => output_v := '3';
1793 
      when x"4"   => output_v := '4';
1794 
      when x"5"   => output_v := '5';
1795 
      when x"6"   => output_v := '6';
1796 
      when x"7"   => output_v := '7';
1797 
      when x"8"   => output_v := '8';
1798 
      when x"9"   => output_v := '9';
1799 
      when x"a"   => output_v := 'a';
1800 
      when x"b"   => output_v := 'b';
1801 
      when x"c"   => output_v := 'c';
1802 
      when x"d"   => output_v := 'd';
1803 
      when x"e"   => output_v := 'e';
1804 
      when x"f"   => output_v := 'f';
1805 6 zero_gravi 
      when others => output_v := '?';
1806 
    end case;
1807 
    return output_v;
1808 
  end function to_hexchar_f;
1809 
 
1810 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1811 
  -- -------------------------------------------------------------------------------------------
1812 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1813 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1814 
  begin
1815 
    case input is
1816 
      when '0'       => hex_value_v := x"0";
1817 
      when '1'       => hex_value_v := x"1";
1818 
      when '2'       => hex_value_v := x"2";
1819 
      when '3'       => hex_value_v := x"3";
1820 
      when '4'       => hex_value_v := x"4";
1821 
      when '5'       => hex_value_v := x"5";
1822 
      when '6'       => hex_value_v := x"6";
1823 
      when '7'       => hex_value_v := x"7";
1824 
      when '8'       => hex_value_v := x"8";
1825 
      when '9'       => hex_value_v := x"9";
1826 
      when 'a' | 'A' => hex_value_v := x"a";
1827 
      when 'b' | 'B' => hex_value_v := x"b";
1828 
      when 'c' | 'C' => hex_value_v := x"c";
1829 
      when 'd' | 'D' => hex_value_v := x"d";
1830 
      when 'e' | 'E' => hex_value_v := x"e";
1831 
      when 'f' | 'F' => hex_value_v := x"f";
1832 
      when others    => hex_value_v := (others => 'X');
1833 
    end case;
1834 
    return hex_value_v;
1835 
  end function hexchar_to_stdulogicvector_f;
1836 
 
1837 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1838 
  -- -------------------------------------------------------------------------------------------
1839 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1840 
    variable output_v : std_ulogic_vector(input'range);
1841 
  begin
1842 
    for i in 0 to input'length-1 loop
1843 
      output_v(input'length-i-1) := input(i);
1844 
    end loop; -- i
1845 
    return output_v;
1846 
  end function bit_rev_f;
1847 
 
1848 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1849 
  -- -------------------------------------------------------------------------------------------
1850 
  function is_power_of_two_f(input : natural) return boolean is
1851 
  begin
1852 38 zero_gravi 
    if (input = 1) then -- 2^0
1853 36 zero_gravi 
      return true;
1854 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
1855 
      return true;
1856 36 zero_gravi 
    else
1857 
      return false;
1858 
    end if;
1859 
  end function is_power_of_two_f;
1860 
 
1861 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
1862 
  -- -------------------------------------------------------------------------------------------
1863 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
1864 
    variable output_v : std_ulogic_vector(input'range);
1865 
  begin
1866 
    output_v(07 downto 00) := input(31 downto 24);
1867 
    output_v(15 downto 08) := input(23 downto 16);
1868 
    output_v(23 downto 16) := input(15 downto 08);
1869 
    output_v(31 downto 24) := input(07 downto 00);
1870 
    return output_v;
1871 
  end function bswap32_f;
1872 
 
1873 2 zero_gravi 
end neorv32_package;

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