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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_spi.vhd] - Blame information for rev 6

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1 2 zero_gravi
-- #################################################################################################
2 6 zero_gravi
-- # << NEORV32 - Serial Peripheral Interface Controller (SPI) >>                                  #
3 2 zero_gravi
-- # ********************************************************************************************* #
4
-- # Frame format: 8/16/24/32-bit RTX, MSB or LSB first, 2 clock modes, 8 clock speeds,            #
5
-- # 8 dedicated CS lines (low-active). Interrupt: SPI_transfer_done                               #
6
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
10
-- #                                                                                               #
11
-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
14
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
16
-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
18
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
21
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
22
-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
24
-- #                                                                                               #
25
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
26
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
27
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
28
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
29
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
31
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
32
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
33
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
34
-- # ********************************************************************************************* #
35
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_spi is
46
  port (
47
    -- host access --
48
    clk_i       : in  std_ulogic; -- global clock line
49
    addr_i      : in  std_ulogic_vector(31 downto 0); -- address
50
    rden_i      : in  std_ulogic; -- read enable
51
    wren_i      : in  std_ulogic; -- write enable
52
    ben_i       : in  std_ulogic_vector(03 downto 0); -- byte write enable
53
    data_i      : in  std_ulogic_vector(31 downto 0); -- data in
54
    data_o      : out std_ulogic_vector(31 downto 0); -- data out
55
    ack_o       : out std_ulogic; -- transfer acknowledge
56
    -- clock generator --
57
    clkgen_en_o : out std_ulogic; -- enable clock generator
58
    clkgen_i    : in  std_ulogic_vector(07 downto 0);
59
    -- com lines --
60 6 zero_gravi
    spi_sck_o   : out std_ulogic; -- SPI serial clock
61
    spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
62
    spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
63 2 zero_gravi
    spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
64
    -- interrupt --
65
    spi_irq_o   : out std_ulogic -- transmission done interrupt
66
  );
67
end neorv32_spi;
68
 
69
architecture neorv32_spi_rtl of neorv32_spi is
70
 
71
  -- IO space: module base address --
72
  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
73
  constant lo_abb_c : natural := index_size_f(spi_size_c); -- low address boundary bit
74
 
75
  -- control reg bits --
76
  constant ctrl_spi_cs0_c    : natural :=  0; -- r/w: spi CS 0
77
  constant ctrl_spi_cs1_c    : natural :=  1; -- r/w: spi CS 1
78
  constant ctrl_spi_cs2_c    : natural :=  2; -- r/w: spi CS 2
79
  constant ctrl_spi_cs3_c    : natural :=  3; -- r/w: spi CS 3
80
  constant ctrl_spi_cs4_c    : natural :=  4; -- r/w: spi CS 4
81
  constant ctrl_spi_cs5_c    : natural :=  5; -- r/w: spi CS 5
82
  constant ctrl_spi_cs6_c    : natural :=  6; -- r/w: spi CS 6
83
  constant ctrl_spi_cs7_c    : natural :=  7; -- r/w: spi CS 7
84
  --
85
  constant ctrl_spi_en_c     : natural :=  8; -- r/w: spi enable
86
  constant ctrl_spi_cpha_c   : natural :=  9; -- r/w: spi clock phase
87
  constant ctrl_spi_prsc0_c  : natural := 10; -- r/w: spi prescaler select bit 0
88
  constant ctrl_spi_prsc1_c  : natural := 11; -- r/w: spi prescaler select bit 1
89
  constant ctrl_spi_prsc2_c  : natural := 12; -- r/w: spi prescaler select bit 2
90
  constant ctrl_spi_dir_c    : natural := 13; -- r/w: shift direction (0: MSB first, 1: LSB first)
91
  constant ctrl_spi_size0_c  : natural := 14; -- r/w: data size (00:  8-bit, 01: 16-bit)
92
  constant ctrl_spi_size1_c  : natural := 15; -- r/w: data size (10: 24-bit, 11: 32-bit)
93
  --
94
  constant ctrl_spi_irq_en_c : natural := 16; -- r/w: spi transmission done interrupt enable
95
  --
96
  constant ctrl_spi_busy_c   : natural := 31; -- r/-: spi transceiver is busy
97
 
98
  -- access control --
99
  signal acc_en : std_ulogic; -- module access enable
100
  signal addr   : std_ulogic_vector(31 downto 0); -- access address
101
  signal wren   : std_ulogic; -- word write enable
102
  signal rden   : std_ulogic; -- read enable
103
 
104
  -- accessible regs --
105
  signal ctrl    : std_ulogic_vector(16 downto 0);
106
  signal tx_data : std_ulogic_vector(31 downto 0);
107
 
108
  -- clock generator --
109
  signal spi_clk : std_ulogic;
110
 
111
  -- spi transceiver --
112
  signal spi_start    : std_ulogic;
113
  signal spi_busy     : std_ulogic;
114
  signal spi_state0   : std_ulogic;
115
  signal spi_state1   : std_ulogic;
116
  signal spi_rtx_sreg : std_ulogic_vector(31 downto 0);
117
  signal spi_rx_data  : std_ulogic_vector(31 downto 0);
118
  signal spi_bitcnt   : std_ulogic_vector(05 downto 0);
119 6 zero_gravi
  signal spi_sdi_ff0  : std_ulogic;
120
  signal spi_sdi_ff1  : std_ulogic;
121 2 zero_gravi
 
122
begin
123
 
124
  -- Access Control -------------------------------------------------------------------------
125
  -- -------------------------------------------------------------------------------------------
126
  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = spi_base_c(hi_abb_c downto lo_abb_c)) else '0';
127
  addr   <= spi_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
128
  wren   <= acc_en and wren_i;
129
  rden   <= acc_en and rden_i;
130
 
131
 
132
  -- Read/Write Access ----------------------------------------------------------------------
133
  -- -------------------------------------------------------------------------------------------
134
  rw_access: process(clk_i)
135
  begin
136
    if rising_edge(clk_i) then
137
      ack_o <= acc_en and (rden_i or wren_i);
138
      spi_start <= '0';
139
      -- write access --
140
      if (wren = '1') then
141
        -- control regsiter --
142
        if (addr = spi_ctrl_addr_c) then
143
          if (ben_i(0) = '1') then
144
            ctrl(07 downto 00) <= data_i(07 downto 00);
145
          end if;
146
          if (ben_i(1) = '1') then
147
            ctrl(15 downto 08) <= data_i(15 downto 08);
148
          end if;
149
          if (ben_i(2) = '1') then
150
            ctrl(16 downto 16) <= data_i(16 downto 16);
151
          end if;
152
        end if;
153
        -- data regsiter --
154
        if (addr = spi_rtx_addr_c) then
155
          spi_start <= '1';
156
          for i in 0 to 3 loop
157
            if (ben_i(i) = '1') then
158
              tx_data(7+i*8 downto 0+i*8) <= data_i(7+i*8 downto 0+i*8);
159
            end if;
160
          end loop; -- i
161
        end if;
162
      end if;
163
      -- read access --
164
      data_o <= (others => '0');
165
      if (rden = '1') then
166
        if (addr = spi_ctrl_addr_c) then
167
          data_o(ctrl_spi_cs0_c)    <= ctrl(ctrl_spi_cs0_c);
168
          data_o(ctrl_spi_cs1_c)    <= ctrl(ctrl_spi_cs1_c);
169
          data_o(ctrl_spi_cs2_c)    <= ctrl(ctrl_spi_cs2_c);
170
          data_o(ctrl_spi_cs3_c)    <= ctrl(ctrl_spi_cs3_c);
171
          data_o(ctrl_spi_cs4_c)    <= ctrl(ctrl_spi_cs4_c);
172
          data_o(ctrl_spi_cs5_c)    <= ctrl(ctrl_spi_cs5_c);
173
          data_o(ctrl_spi_cs6_c)    <= ctrl(ctrl_spi_cs6_c);
174
          data_o(ctrl_spi_cs7_c)    <= ctrl(ctrl_spi_cs7_c);
175
          --
176
          data_o(ctrl_spi_en_c)     <= ctrl(ctrl_spi_en_c);
177
          data_o(ctrl_spi_cpha_c)   <= ctrl(ctrl_spi_cpha_c);
178
          data_o(ctrl_spi_prsc0_c)  <= ctrl(ctrl_spi_prsc0_c);
179
          data_o(ctrl_spi_prsc1_c)  <= ctrl(ctrl_spi_prsc1_c);
180
          data_o(ctrl_spi_prsc2_c)  <= ctrl(ctrl_spi_prsc2_c);
181
          data_o(ctrl_spi_dir_c)    <= ctrl(ctrl_spi_dir_c);
182
          data_o(ctrl_spi_size0_c)  <= ctrl(ctrl_spi_size0_c);
183
          data_o(ctrl_spi_size1_c)  <= ctrl(ctrl_spi_size1_c);
184
          --
185
          data_o(ctrl_spi_irq_en_c) <= ctrl(ctrl_spi_irq_en_c);
186
          --
187
          data_o(ctrl_spi_busy_c)   <= spi_busy;
188
        else -- spi_rtx_addr_c
189
          data_o <= spi_rx_data;
190
        end if;
191
      end if;
192
    end if;
193
  end process rw_access;
194
 
195
  -- direct CS (output is low-active) --  
196
  spi_csn_o(0) <= '0' when (ctrl(ctrl_spi_cs0_c) = '1') else '1';
197
  spi_csn_o(1) <= '0' when (ctrl(ctrl_spi_cs1_c) = '1') else '1';
198
  spi_csn_o(2) <= '0' when (ctrl(ctrl_spi_cs2_c) = '1') else '1';
199
  spi_csn_o(3) <= '0' when (ctrl(ctrl_spi_cs3_c) = '1') else '1';
200
  spi_csn_o(4) <= '0' when (ctrl(ctrl_spi_cs4_c) = '1') else '1';
201
  spi_csn_o(5) <= '0' when (ctrl(ctrl_spi_cs5_c) = '1') else '1';
202
  spi_csn_o(6) <= '0' when (ctrl(ctrl_spi_cs6_c) = '1') else '1';
203
  spi_csn_o(7) <= '0' when (ctrl(ctrl_spi_cs7_c) = '1') else '1';
204
 
205
 
206
  -- Clock Selection ------------------------------------------------------------------------
207
  -- -------------------------------------------------------------------------------------------
208
  -- clock generator enable --
209
  clkgen_en_o <= ctrl(ctrl_spi_en_c);
210
 
211
  -- spi clock select --
212
  spi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_spi_prsc2_c downto ctrl_spi_prsc0_c))));
213
 
214
 
215
  -- SPI Transceiver ------------------------------------------------------------------------
216
  -- -------------------------------------------------------------------------------------------
217
  spi_rtx_unit: process(clk_i)
218
  begin
219
    if rising_edge(clk_i) then
220 6 zero_gravi
      -- input (sdi) synchronizer --
221
      spi_sdi_ff0 <= spi_sdi_i;
222
      spi_sdi_ff1 <= spi_sdi_ff0;
223 2 zero_gravi
 
224
      -- serial engine --
225
      spi_irq_o <= '0';
226
      if (spi_state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled
227
        case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is
228
          when "00"   => spi_bitcnt <= "001000"; -- 8-bit mode
229
          when "01"   => spi_bitcnt <= "010000"; -- 16-bit mode
230
          when "10"   => spi_bitcnt <= "011000"; -- 24-bit mode
231
          when others => spi_bitcnt <= "100000"; -- 32-bit mode
232
        end case;
233
        spi_state1 <= '0';
234 6 zero_gravi
        spi_sdo_o <= '0';
235
        spi_sck_o <= '0';
236 2 zero_gravi
        if (ctrl(ctrl_spi_en_c) = '0') then -- disabled
237
          spi_busy <= '0';
238
        elsif (spi_start = '1') then -- start new transmission
239
          case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is
240
            when "00"   => spi_rtx_sreg <= tx_data(07 downto 0) & x"000000"; -- 8-bit mode
241
            when "01"   => spi_rtx_sreg <= tx_data(15 downto 0) & x"0000"; -- 16-bit mode
242
            when "10"   => spi_rtx_sreg <= tx_data(23 downto 0) & x"00"; -- 24-bit mode
243
            when others => spi_rtx_sreg <= tx_data(31 downto 0); -- 32-bit mode
244
          end case;
245
          spi_busy <= '1';
246
        end if;
247
        spi_state0 <= spi_busy and spi_clk; -- start with next new clock pulse
248
 
249
      else -- transmission in progress
250
        if (spi_state1 = '0') then -- first half of transmission
251
 
252 6 zero_gravi
          spi_sck_o <= ctrl(ctrl_spi_cpha_c);
253 2 zero_gravi
          if (ctrl(ctrl_spi_dir_c) = '0') then
254 6 zero_gravi
            spi_sdo_o <= spi_rtx_sreg(31); -- MSB first
255 2 zero_gravi
          else
256 6 zero_gravi
            spi_sdo_o <= spi_rtx_sreg(0); -- LSB first
257 2 zero_gravi
          end if;
258
          if (spi_clk = '1') then
259
            spi_state1 <= '1';
260
            if (ctrl(ctrl_spi_cpha_c) = '0') then
261
              if (ctrl(ctrl_spi_dir_c) = '0') then
262 6 zero_gravi
                spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1; -- MSB first
263 2 zero_gravi
              else
264 6 zero_gravi
                spi_rtx_sreg <= spi_sdi_ff1 & spi_rtx_sreg(31 downto 1); -- LSB first
265 2 zero_gravi
              end if;
266
            end if;
267
            spi_bitcnt <= std_ulogic_vector(unsigned(spi_bitcnt) - 1);
268
          end if;
269
        else -- second half of transmission
270
 
271 6 zero_gravi
          spi_sck_o <= not ctrl(ctrl_spi_cpha_c);
272 2 zero_gravi
          if (spi_clk = '1') then
273
            spi_state1 <= '0';
274
            if (ctrl(ctrl_spi_cpha_c) = '1') then
275
              if (ctrl(ctrl_spi_dir_c) = '0') then
276 6 zero_gravi
                spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1; -- MSB first
277 2 zero_gravi
              else
278 6 zero_gravi
                spi_rtx_sreg <= spi_sdi_ff1 & spi_rtx_sreg(31 downto 1); -- LSB first
279 2 zero_gravi
              end if;
280
            end if;
281
            if (spi_bitcnt = "000000") then
282
              spi_state0 <= '0';
283
              spi_busy   <= '0';
284
              spi_irq_o  <= ctrl(ctrl_spi_irq_en_c);
285
            end if;
286
          end if;
287
        end if;
288
      end if;
289
    end if;
290
  end process spi_rtx_unit;
291
 
292
  -- SPI receiver output --
293
  spi_rx_output: process(ctrl, spi_rtx_sreg)
294
  begin
295
    case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is
296
      when "00"   => spi_rx_data <= x"000000" & spi_rtx_sreg(7 downto 0); -- 8-bit mode
297
      when "01"   => spi_rx_data <= x"0000" & spi_rtx_sreg(15 downto 0); -- 16-bit mode
298
      when "10"   => spi_rx_data <= x"00" & spi_rtx_sreg(23 downto 0); -- 24-bit mode
299
      when others => spi_rx_data <= spi_rtx_sreg(31 downto 0); -- 32-bit mode
300
    end case;
301
  end process spi_rx_output;
302
 
303
 
304
end neorv32_spi_rtl;

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