OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_sysinfo.vhd] - Blame information for rev 49

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >>                   #
3
-- # ********************************************************************************************* #
4 47 zero_gravi
-- # This unit provides information regarding the NEORV32 processor system configuration -         #
5 18 zero_gravi
-- # mostly derived from the top's configuration generics.                                         #
6 12 zero_gravi
-- # ********************************************************************************************* #
7
-- # BSD 3-Clause License                                                                          #
8
-- #                                                                                               #
9 44 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
10 12 zero_gravi
-- #                                                                                               #
11
-- # Redistribution and use in source and binary forms, with or without modification, are          #
12
-- # permitted provided that the following conditions are met:                                     #
13
-- #                                                                                               #
14
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
15
-- #    conditions and the following disclaimer.                                                   #
16
-- #                                                                                               #
17
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
18
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
19
-- #    provided with the distribution.                                                            #
20
-- #                                                                                               #
21
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
22
-- #    endorse or promote products derived from this software without specific prior written      #
23
-- #    permission.                                                                                #
24
-- #                                                                                               #
25
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
26
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
27
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
28
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
29
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
30
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
31
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
32
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
33
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
34
-- # ********************************************************************************************* #
35
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
36
-- #################################################################################################
37
 
38
library ieee;
39
use ieee.std_logic_1164.all;
40
use ieee.numeric_std.all;
41
 
42
library neorv32;
43
use neorv32.neorv32_package.all;
44
 
45
entity neorv32_sysinfo is
46
  generic (
47
    -- General --
48 41 zero_gravi
    CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
49 44 zero_gravi
    BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
50 41 zero_gravi
    USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
51 23 zero_gravi
    -- Internal Instruction memory --
52 44 zero_gravi
    MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
53 41 zero_gravi
    MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
54
    MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
55 23 zero_gravi
    -- Internal Data memory --
56 44 zero_gravi
    MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
57 41 zero_gravi
    MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
58
    -- Internal Cache memory --
59 44 zero_gravi
    ICACHE_EN            : boolean := true;   -- implement instruction cache
60 41 zero_gravi
    ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
61
    ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
62
    ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
63 23 zero_gravi
    -- External memory interface --
64 44 zero_gravi
    MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
65 12 zero_gravi
    -- Processor peripherals --
66 44 zero_gravi
    IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
67
    IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
68
    IO_UART_EN           : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
69
    IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
70
    IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
71
    IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
72
    IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
73
    IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
74 49 zero_gravi
    IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
75
    IO_NCO_EN            : boolean := true    -- implement numerically-controlled oscillator (NCO)?
76 12 zero_gravi
  );
77
  port (
78
    -- host access --
79
    clk_i  : in  std_ulogic; -- global clock line
80
    addr_i : in  std_ulogic_vector(31 downto 0); -- address
81
    rden_i : in  std_ulogic; -- read enable
82
    data_o : out std_ulogic_vector(31 downto 0); -- data out
83
    ack_o  : out std_ulogic  -- transfer acknowledge
84
  );
85
end neorv32_sysinfo;
86
 
87
architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
88
 
89
  -- IO space: module base address --
90
  constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
91
  constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit
92
 
93
  -- access control --
94
  signal acc_en    : std_ulogic; -- module access enable
95
  signal addr      : std_ulogic_vector(31 downto 0);
96
  signal rden      : std_ulogic;
97
  signal info_addr : std_ulogic_vector(02 downto 0);
98
 
99
  -- system information ROM --
100
  type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
101
  signal sysinfo_mem : info_mem_t;
102
 
103
begin
104
 
105
  -- Access Control -------------------------------------------------------------------------
106
  -- -------------------------------------------------------------------------------------------
107
  acc_en    <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
108
  rden      <= acc_en and rden_i; -- valid read access
109
  addr      <= sysinfo_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
110
  info_addr <= addr(index_size_f(sysinfo_size_c)-1 downto 2);
111
 
112
 
113
  -- Construct Info ROM ---------------------------------------------------------------------
114
  -- -------------------------------------------------------------------------------------------
115
 
116
  -- SYSINFO(0): Processor (primary) clock frequency --
117
  sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
118
 
119 23 zero_gravi
  -- SYSINFO(1): Custom user code/ID --
120 12 zero_gravi
  sysinfo_mem(1) <= USER_CODE;
121
 
122
  -- SYSINFO(2): Implemented processor devices/features --
123 23 zero_gravi
  -- Memory --
124 44 zero_gravi
  sysinfo_mem(2)(00) <= bool_to_ulogic_f(BOOTLOADER_EN);     -- processor-internal bootloader implemented?
125
  sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_EN);        -- external memory bus interface implemented?
126
  sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_EN);   -- processor-internal instruction memory implemented?
127 40 zero_gravi
  sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM);  -- processor-internal instruction memory implemented as ROM?
128 44 zero_gravi
  sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_EN);   -- processor-internal data memory implemented?
129 40 zero_gravi
  sysinfo_mem(2)(05) <= bool_to_ulogic_f(xbus_big_endian_c); -- is external memory bus interface using BIG-endian byte-order?
130 44 zero_gravi
  sysinfo_mem(2)(06) <= bool_to_ulogic_f(ICACHE_EN);         -- processor-internal instruction cache implemented?
131 23 zero_gravi
  --
132 41 zero_gravi
  sysinfo_mem(2)(15 downto 07) <= (others => '0'); -- reserved
133 23 zero_gravi
  -- IO --
134 44 zero_gravi
  sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN);  -- general purpose input/output port unit (GPIO) implemented?
135
  sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented?
136
  sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_EN);  -- universal asynchronous receiver/transmitter (UART) implemented?
137
  sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN);   -- serial peripheral interface (SPI) implemented?
138
  sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN);   -- two-wire interface (TWI) implemented?
139
  sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_EN);   -- pulse-width modulation unit (PWM) implemented?
140
  sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN);   -- watch dog timer (WDT) implemented?
141 47 zero_gravi
  sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN);   -- custom functions subsystem (CFS) implemented?
142 44 zero_gravi
  sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN);  -- true random number generator (TRNG) implemented?
143 49 zero_gravi
  sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_NCO_EN);   -- numerically-controlled oscillator (NCO) implemented?
144 23 zero_gravi
  --
145 49 zero_gravi
  sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
146 12 zero_gravi
 
147 41 zero_gravi
  -- SYSINFO(3): Cache configuration --
148 45 zero_gravi
  sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE),    4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
149
  sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS),    4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block)
150 44 zero_gravi
  sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity)
151 45 zero_gravi
  sysinfo_mem(3)(15 downto 12) <= "0001" when (ICACHE_ASSOCIATIVITY > 1) and (ICACHE_EN = true) else (others => '0'); -- i-cache: replacement strategy (LRU only (yet))
152 41 zero_gravi
  --
153 45 zero_gravi
  sysinfo_mem(3)(19 downto 16) <= (others => '0'); -- reserved - d-cache: log2(block_size)
154
  sysinfo_mem(3)(23 downto 20) <= (others => '0'); -- reserved - d-cache: log2(num_blocks)
155
  sysinfo_mem(3)(27 downto 24) <= (others => '0'); -- reserved - d-cache: log2(associativity)
156
  sysinfo_mem(3)(31 downto 28) <= (others => '0'); -- reserved - d-cache: replacement strategy
157 12 zero_gravi
 
158
  -- SYSINFO(4): Base address of instruction memory space --
159 23 zero_gravi
  sysinfo_mem(4) <= ispace_base_c; -- defined in neorv32_package.vhd file
160 12 zero_gravi
 
161
  -- SYSINFO(5): Base address of data memory space --
162 23 zero_gravi
  sysinfo_mem(5) <= dspace_base_c; -- defined in neorv32_package.vhd file
163 12 zero_gravi
 
164 23 zero_gravi
  -- SYSINFO(6): Size of IMEM in bytes --
165 44 zero_gravi
  sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_INT_IMEM_SIZE, 32)) when (MEM_INT_IMEM_EN = true) else (others => '0');
166 12 zero_gravi
 
167 23 zero_gravi
  -- SYSINFO(7): Size of DMEM in bytes --
168 44 zero_gravi
  sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_INT_DMEM_SIZE, 32)) when (MEM_INT_DMEM_EN = true) else (others => '0');
169 12 zero_gravi
 
170
 
171
  -- Read Access ----------------------------------------------------------------------------
172
  -- -------------------------------------------------------------------------------------------
173
  read_access: process(clk_i)
174
  begin
175
    if rising_edge(clk_i) then
176 23 zero_gravi
      ack_o  <= rden;
177
      data_o <= (others => '0');
178 12 zero_gravi
      if (rden = '1') then
179
        data_o <= sysinfo_mem(to_integer(unsigned(info_addr)));
180
      end if;
181
    end if;
182
  end process read_access;
183
 
184
 
185
end neorv32_sysinfo_rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.