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1 2 zero_gravi
-- #################################################################################################
2 36 zero_gravi
-- # << NEORV32 - Default Testbench >>                                                             #
3 2 zero_gravi
-- # ********************************************************************************************* #
4 45 zero_gravi
-- # The processor is configured to use a maximum of functional units (for testing purpose).       #
5
-- # Use the "User Configuration" section to configure the testbench according to your needs.      #
6 40 zero_gravi
-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information.                               #
7 3 zero_gravi
-- # ********************************************************************************************* #
8 2 zero_gravi
-- # BSD 3-Clause License                                                                          #
9
-- #                                                                                               #
10 42 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
11 2 zero_gravi
-- #                                                                                               #
12
-- # Redistribution and use in source and binary forms, with or without modification, are          #
13
-- # permitted provided that the following conditions are met:                                     #
14
-- #                                                                                               #
15
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
16
-- #    conditions and the following disclaimer.                                                   #
17
-- #                                                                                               #
18
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
19
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
20
-- #    provided with the distribution.                                                            #
21
-- #                                                                                               #
22
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
23
-- #    endorse or promote products derived from this software without specific prior written      #
24
-- #    permission.                                                                                #
25
-- #                                                                                               #
26
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
27
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
28
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
29
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
30
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
31
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
32
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
33
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
34
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
35
-- # ********************************************************************************************* #
36
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
37
-- #################################################################################################
38
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41
use ieee.numeric_std.all;
42
use ieee.math_real.all;
43
 
44
library neorv32;
45
use neorv32.neorv32_package.all;
46 30 zero_gravi
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
47 2 zero_gravi
use std.textio.all;
48
 
49
entity neorv32_tb is
50
end neorv32_tb;
51
 
52
architecture neorv32_tb_rtl of neorv32_tb is
53
 
54
  -- User Configuration ---------------------------------------------------------------------
55
  -- -------------------------------------------------------------------------------------------
56 38 zero_gravi
  -- general --
57 39 zero_gravi
  constant ext_imem_c            : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
58
  constant ext_dmem_c            : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
59 44 zero_gravi
  constant icache_en_c           : boolean := false; -- set true to use processor-internal instruction cache
60 38 zero_gravi
  constant imem_size_c           : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
61 39 zero_gravi
  constant dmem_size_c           : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
62 38 zero_gravi
  constant f_clock_c             : natural := 100000000; -- main clock in Hz
63 50 zero_gravi
  constant baud0_rate_c          : natural := 19200; -- simulation UART0 (primary UART) baud rate
64
  constant baud1_rate_c          : natural := 19200; -- simulation UART1 (secondary UART) baud rate
65 38 zero_gravi
  -- simulated external Wishbone memory A (can be used as external IMEM) --
66 39 zero_gravi
  constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
67 38 zero_gravi
  constant ext_mem_a_size_c      : natural := imem_size_c; -- wishbone memory size in bytes
68 40 zero_gravi
  constant ext_mem_a_latency_c   : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
69 39 zero_gravi
  -- simulated external Wishbone memory B (can be used as external DMEM) --
70
  constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
71
  constant ext_mem_b_size_c      : natural := dmem_size_c; -- wishbone memory size in bytes
72 40 zero_gravi
  constant ext_mem_b_latency_c   : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
73 39 zero_gravi
  -- simulated external Wishbone memory C (can be used as external IO) --
74
  constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
75
  constant ext_mem_c_size_c      : natural := 64; -- wishbone memory size in bytes
76 40 zero_gravi
  constant ext_mem_c_latency_c   : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
77 47 zero_gravi
  -- simulation interrupt trigger --
78
  constant irq_trigger_c         : std_ulogic_vector(31 downto 0) := x"FF000000";
79 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
80
 
81 38 zero_gravi
  -- internals - hands off! --
82 50 zero_gravi
  constant int_imem_c       : boolean := not ext_imem_c;
83
  constant int_dmem_c       : boolean := not ext_dmem_c;
84
  constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c);
85
  constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c);
86
  constant t_clock_c        : time := (1 sec) / f_clock_c;
87 38 zero_gravi
 
88 2 zero_gravi
  -- generators --
89
  signal clk_gen, rst_gen : std_ulogic := '0';
90
 
91 50 zero_gravi
  -- text.io --
92
  file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out";
93
  file file_uart1_tx_out : text open write_mode is "neorv32.testbench_uart1.out";
94 2 zero_gravi
 
95 50 zero_gravi
  -- simulation uart0 receiver --
96 51 zero_gravi
  signal uart0_txd         : std_ulogic; -- local loop-back
97
  signal uart0_cts         : std_ulogic; -- local loop-back
98 50 zero_gravi
  signal uart0_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
99
  signal uart0_rx_busy     : std_ulogic := '0';
100
  signal uart0_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
101
  signal uart0_rx_baud_cnt : real;
102
  signal uart0_rx_bitcnt   : natural;
103
 
104
  -- simulation uart1 receiver --
105 51 zero_gravi
  signal uart1_txd         : std_ulogic; -- local loop-back
106
  signal uart1_cts         : std_ulogic; -- local loop-back
107 50 zero_gravi
  signal uart1_rx_sync     : std_ulogic_vector(04 downto 0) := (others => '1');
108
  signal uart1_rx_busy     : std_ulogic := '0';
109
  signal uart1_rx_sreg     : std_ulogic_vector(08 downto 0) := (others => '0');
110
  signal uart1_rx_baud_cnt : real;
111
  signal uart1_rx_bitcnt   : natural;
112
 
113 2 zero_gravi
  -- gpio --
114 22 zero_gravi
  signal gpio : std_ulogic_vector(31 downto 0);
115 2 zero_gravi
 
116
  -- twi --
117
  signal twi_scl, twi_sda : std_logic;
118
 
119
  -- spi --
120 40 zero_gravi
  signal spi_data : std_ulogic;
121 2 zero_gravi
 
122 40 zero_gravi
  -- irq --
123
  signal msi_ring, mei_ring : std_ulogic;
124 50 zero_gravi
  signal soc_firq_ring      : std_ulogic_vector(5 downto 0);
125 40 zero_gravi
 
126 2 zero_gravi
  -- Wishbone bus --
127
  type wishbone_t is record
128
    addr  : std_ulogic_vector(31 downto 0); -- address
129
    wdata : std_ulogic_vector(31 downto 0); -- master write data
130
    rdata : std_ulogic_vector(31 downto 0); -- master read data
131
    we    : std_ulogic; -- write enable
132
    sel   : std_ulogic_vector(03 downto 0); -- byte enable
133
    stb   : std_ulogic; -- strobe
134
    cyc   : std_ulogic; -- valid cycle
135
    ack   : std_ulogic; -- transfer acknowledge
136
    err   : std_ulogic; -- transfer error
137 36 zero_gravi
    tag   : std_ulogic_vector(2 downto 0); -- tag
138 39 zero_gravi
    lock  : std_ulogic; -- locked/exclusive bus access
139 2 zero_gravi
  end record;
140 47 zero_gravi
  signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
141 2 zero_gravi
 
142 38 zero_gravi
  -- Wishbone memories --
143
  type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
144
  type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
145 39 zero_gravi
  type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
146 38 zero_gravi
  type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
147 30 zero_gravi
 
148
  -- init function --
149
  -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
150 38 zero_gravi
  impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
151
    variable mem_v : ext_mem_a_ram_t;
152 30 zero_gravi
  begin
153
    mem_v := (others => (others => '0'));
154
    for i in 0 to init'length-1 loop -- init only in range of source data array
155 40 zero_gravi
      if (xbus_big_endian_c = true) then
156 30 zero_gravi
        mem_v(i) := init(i);
157 40 zero_gravi
      else
158
        mem_v(i) := bswap32_f(init(i));
159
      end if;
160 30 zero_gravi
    end loop; -- i
161
    return mem_v;
162
  end function init_wbmem;
163
 
164 38 zero_gravi
  -- external memory components --
165 39 zero_gravi
  signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM
166
  signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM
167
  signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO
168 30 zero_gravi
 
169 38 zero_gravi
  type ext_mem_t is record
170
    rdata  : ext_mem_read_latency_t;
171 23 zero_gravi
    acc_en : std_ulogic;
172 38 zero_gravi
    ack    : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
173 23 zero_gravi
  end record;
174 39 zero_gravi
  signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
175 2 zero_gravi
 
176
begin
177
 
178
  -- Clock/Reset Generator ------------------------------------------------------------------
179
  -- -------------------------------------------------------------------------------------------
180
  clk_gen <= not clk_gen after (t_clock_c/2);
181
  rst_gen <= '0', '1' after 60*(t_clock_c/2);
182
 
183
 
184 48 zero_gravi
  -- The Core of the Problem ----------------------------------------------------------------
185 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
186
  neorv32_top_inst: neorv32_top
187
  generic map (
188
    -- General --
189 38 zero_gravi
    CLOCK_FREQUENCY              => f_clock_c,     -- clock frequency of clk_i in Hz
190 44 zero_gravi
    BOOTLOADER_EN                => false,         -- implement processor-internal bootloader?
191 36 zero_gravi
    USER_CODE                    => x"12345678",   -- custom user code
192 49 zero_gravi
    HW_THREAD_ID                 => 0,             -- hardware thread id (hartid) (32-bit)
193 2 zero_gravi
    -- RISC-V CPU Extensions --
194 39 zero_gravi
    CPU_EXTENSION_RISCV_A        => true,          -- implement atomic extension?
195 44 zero_gravi
    CPU_EXTENSION_RISCV_B        => true,          -- implement bit manipulation extensions?
196 8 zero_gravi
    CPU_EXTENSION_RISCV_C        => true,          -- implement compressed extension?
197
    CPU_EXTENSION_RISCV_E        => false,         -- implement embedded RF extension?
198
    CPU_EXTENSION_RISCV_M        => true,          -- implement muld/div extension?
199 15 zero_gravi
    CPU_EXTENSION_RISCV_U        => true,          -- implement user mode extension?
200 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    => true,          -- implement CSR system?
201
    CPU_EXTENSION_RISCV_Zifencei => true,          -- implement instruction stream sync.?
202 19 zero_gravi
    -- Extension Options --
203
    FAST_MUL_EN                  => false,         -- use DSPs for M extension's multiplier
204 34 zero_gravi
    FAST_SHIFT_EN                => false,         -- use barrel shifter for shift operations
205 15 zero_gravi
    -- Physical Memory Protection (PMP) --
206 47 zero_gravi
    PMP_NUM_REGIONS              => 4,             -- number of regions (0..64)
207 42 zero_gravi
    PMP_MIN_GRANULARITY          => 64*1024,       -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
208
    -- Hardware Performance Monitors (HPM) --
209
    HPM_NUM_CNTS                 => 12,            -- number of inmplemnted HPM counters (0..29)
210 23 zero_gravi
    -- Internal Instruction memory --
211 44 zero_gravi
    MEM_INT_IMEM_EN              => int_imem_c ,   -- implement processor-internal instruction memory
212 38 zero_gravi
    MEM_INT_IMEM_SIZE            => imem_size_c,   -- size of processor-internal instruction memory in bytes
213 8 zero_gravi
    MEM_INT_IMEM_ROM             => false,         -- implement processor-internal instruction memory as ROM
214 23 zero_gravi
    -- Internal Data memory --
215 44 zero_gravi
    MEM_INT_DMEM_EN              => int_dmem_c,    -- implement processor-internal data memory
216 39 zero_gravi
    MEM_INT_DMEM_SIZE            => dmem_size_c,   -- size of processor-internal data memory in bytes
217 41 zero_gravi
    -- Internal Cache memory --
218 44 zero_gravi
    ICACHE_EN                    => icache_en_c,   -- implement instruction cache
219 41 zero_gravi
    ICACHE_NUM_BLOCKS            => 8,             -- i-cache: number of blocks (min 2), has to be a power of 2
220
    ICACHE_BLOCK_SIZE            => 64,            -- i-cache: block size in bytes (min 4), has to be a power of 2
221 45 zero_gravi
    ICACHE_ASSOCIATIVITY         => 2,             -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
222 23 zero_gravi
    -- External memory interface --
223 44 zero_gravi
    MEM_EXT_EN                   => true,          -- implement external memory bus interface?
224 2 zero_gravi
    -- Processor peripherals --
225 44 zero_gravi
    IO_GPIO_EN                   => true,          -- implement general purpose input/output port unit (GPIO)?
226
    IO_MTIME_EN                  => true,          -- implement machine system timer (MTIME)?
227 50 zero_gravi
    IO_UART0_EN                  => true,          -- implement primary universal asynchronous receiver/transmitter (UART0)?
228
    IO_UART1_EN                  => true,          -- implement secondary universal asynchronous receiver/transmitter (UART1)?
229 44 zero_gravi
    IO_SPI_EN                    => true,          -- implement serial peripheral interface (SPI)?
230
    IO_TWI_EN                    => true,          -- implement two-wire interface (TWI)?
231
    IO_PWM_EN                    => true,          -- implement pulse-width modulation unit (PWM)?
232
    IO_WDT_EN                    => true,          -- implement watch dog timer (WDT)?
233
    IO_TRNG_EN                   => false,         -- trng cannot be simulated
234 47 zero_gravi
    IO_CFS_EN                    => true,          -- implement custom functions subsystem (CFS)?
235 49 zero_gravi
    IO_CFS_CONFIG                => (others => '0'), -- custom CFS configuration generic
236 52 zero_gravi
    IO_CFS_IN_SIZE               => 32,            -- size of CFS input conduit in bits
237
    IO_CFS_OUT_SIZE              => 32,            -- size of CFS output conduit in bits
238
    IO_NCO_EN                    => true,          -- implement numerically-controlled oscillator (NCO)?
239
    IO_NEOLED_EN                 => true           -- implement NeoPixel-compatible smart LED interface (NEOLED)?
240 2 zero_gravi
  )
241
  port map (
242
    -- Global control --
243 34 zero_gravi
    clk_i       => clk_gen,         -- global clock, rising edge
244
    rstn_i      => rst_gen,         -- global reset, low-active, async
245 49 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_EN = true) --
246 36 zero_gravi
    wb_tag_o    => wb_cpu.tag,      -- tag
247 34 zero_gravi
    wb_adr_o    => wb_cpu.addr,     -- address
248
    wb_dat_i    => wb_cpu.rdata,    -- read data
249
    wb_dat_o    => wb_cpu.wdata,    -- write data
250
    wb_we_o     => wb_cpu.we,       -- read/write
251
    wb_sel_o    => wb_cpu.sel,      -- byte enable
252
    wb_stb_o    => wb_cpu.stb,      -- strobe
253
    wb_cyc_o    => wb_cpu.cyc,      -- valid cycle
254 39 zero_gravi
    wb_lock_o   => wb_cpu.lock,     -- locked/exclusive bus access
255 34 zero_gravi
    wb_ack_i    => wb_cpu.ack,      -- transfer acknowledge
256
    wb_err_i    => wb_cpu.err,      -- transfer error
257 49 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_EN = true) --
258 34 zero_gravi
    fence_o     => open,            -- indicates an executed FENCE operation
259
    fencei_o    => open,            -- indicates an executed FENCEI operation
260 49 zero_gravi
    -- GPIO (available if IO_GPIO_EN = true) --
261 34 zero_gravi
    gpio_o      => gpio,            -- parallel output
262
    gpio_i      => gpio,            -- parallel input
263 50 zero_gravi
    -- primary UART0 (available if IO_UART0_EN = true) --
264
    uart0_txd_o => uart0_txd,       -- UART0 send data
265
    uart0_rxd_i => uart0_txd,       -- UART0 receive data
266 51 zero_gravi
    uart0_rts_o => uart0_cts,       -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
267
    uart0_cts_i => uart0_cts,       -- hw flow control: UART0.TX allowed to transmit, low-active, optional
268 50 zero_gravi
    -- secondary UART1 (available if IO_UART1_EN = true) --
269
    uart1_txd_o => uart1_txd,       -- UART1 send data
270
    uart1_rxd_i => uart1_txd,       -- UART1 receive data
271 51 zero_gravi
    uart1_rts_o => uart1_cts,       -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
272
    uart1_cts_i => uart1_cts,       -- hw flow control: UART1.TX allowed to transmit, low-active, optional
273 49 zero_gravi
    -- SPI (available if IO_SPI_EN = true) --
274 34 zero_gravi
    spi_sck_o   => open,            -- SPI serial clock
275
    spi_sdo_o   => spi_data,        -- controller data out, peripheral data in
276
    spi_sdi_i   => spi_data,        -- controller data in, peripheral data out
277
    spi_csn_o   => open,            -- SPI CS
278 49 zero_gravi
    -- TWI (available if IO_TWI_EN = true) --
279 34 zero_gravi
    twi_sda_io  => twi_sda,         -- twi serial data line
280
    twi_scl_io  => twi_scl,         -- twi serial clock line
281 49 zero_gravi
    -- PWM (available if IO_PWM_EN = true) --
282 34 zero_gravi
    pwm_o       => open,            -- pwm channels
283 47 zero_gravi
    -- Custom Functions Subsystem IO --
284
    cfs_in_i    => (others => '0'), -- custom CFS inputs
285
    cfs_out_o   => open,            -- custom CFS outputs
286 49 zero_gravi
    -- NCO output (available if IO_NCO_EN = true) --
287 52 zero_gravi
    nco_o       => open,            -- numerically-controlled oscillator channels
288
    -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
289
    neoled_o    => open,            -- async serial data line
290 44 zero_gravi
    -- system time input from external MTIME (available if IO_MTIME_EN = false) --
291 40 zero_gravi
    mtime_i     => (others => '0'), -- current system time
292 2 zero_gravi
    -- Interrupts --
293 47 zero_gravi
    soc_firq_i  => soc_firq_ring,   -- fast interrupt channels
294 44 zero_gravi
    mtime_irq_i => '0',             -- machine software interrupt, available if IO_MTIME_EN = false
295 40 zero_gravi
    msw_irq_i   => msi_ring,        -- machine software interrupt
296
    mext_irq_i  => mei_ring         -- machine external interrupt
297 2 zero_gravi
  );
298
 
299 36 zero_gravi
  -- TWI termination (pull-ups) --
300 2 zero_gravi
  twi_scl <= 'H';
301
  twi_sda <= 'H';
302
 
303
 
304 50 zero_gravi
  -- Console UART0 Receiver -----------------------------------------------------------------
305 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
306 50 zero_gravi
  uart0_rx_console: process(clk_gen)
307 3 zero_gravi
    variable i : integer;
308
    variable l : line;
309 2 zero_gravi
  begin
310
    -- "UART" --
311
    if rising_edge(clk_gen) then
312
      -- synchronizer --
313 50 zero_gravi
      uart0_rx_sync <= uart0_rx_sync(3 downto 0) & uart0_txd;
314 2 zero_gravi
      -- arbiter --
315 50 zero_gravi
      if (uart0_rx_busy = '0') then -- idle
316
        uart0_rx_busy     <= '0';
317
        uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
318
        uart0_rx_bitcnt   <= 9;
319
        if (uart0_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
320
          uart0_rx_busy <= '1';
321 2 zero_gravi
        end if;
322
      else
323 50 zero_gravi
        if (uart0_rx_baud_cnt <= 0.0) then
324
          if (uart0_rx_bitcnt = 1) then
325
            uart0_rx_baud_cnt <= round(0.5 * uart0_baud_val_c);
326 2 zero_gravi
          else
327 50 zero_gravi
            uart0_rx_baud_cnt <= round(uart0_baud_val_c);
328 2 zero_gravi
          end if;
329 50 zero_gravi
          if (uart0_rx_bitcnt = 0) then
330
            uart0_rx_busy <= '0'; -- done
331
            i := to_integer(unsigned(uart0_rx_sreg(8 downto 1)));
332 2 zero_gravi
 
333 3 zero_gravi
            if (i < 32) or (i > 32+95) then -- printable char?
334 50 zero_gravi
              report "NEORV32_TB_UART0.TX: (" & integer'image(i) & ")"; -- print code
335 2 zero_gravi
            else
336 50 zero_gravi
              report "NEORV32_TB_UART0.TX: " & character'val(i); -- print ASCII
337 2 zero_gravi
            end if;
338
 
339
            if (i = 10) then -- Linux line break
340 50 zero_gravi
              writeline(file_uart0_tx_out, l);
341 2 zero_gravi
            elsif (i /= 13) then -- Remove additional carriage return
342 3 zero_gravi
              write(l, character'val(i));
343 2 zero_gravi
            end if;
344
          else
345 50 zero_gravi
            uart0_rx_sreg   <= uart0_rx_sync(4) & uart0_rx_sreg(8 downto 1);
346
            uart0_rx_bitcnt <= uart0_rx_bitcnt - 1;
347 2 zero_gravi
          end if;
348
        else
349 50 zero_gravi
          uart0_rx_baud_cnt <= uart0_rx_baud_cnt - 1.0;
350 2 zero_gravi
        end if;
351
      end if;
352
    end if;
353 50 zero_gravi
  end process uart0_rx_console;
354 2 zero_gravi
 
355
 
356 50 zero_gravi
  -- Console UART1 Receiver -----------------------------------------------------------------
357
  -- -------------------------------------------------------------------------------------------
358
  uart1_rx_console: process(clk_gen)
359
    variable i : integer;
360
    variable l : line;
361
  begin
362
    -- "UART" --
363
    if rising_edge(clk_gen) then
364
      -- synchronizer --
365
      uart1_rx_sync <= uart1_rx_sync(3 downto 0) & uart1_txd;
366
      -- arbiter --
367
      if (uart1_rx_busy = '0') then -- idle
368
        uart1_rx_busy     <= '0';
369
        uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
370
        uart1_rx_bitcnt   <= 9;
371
        if (uart1_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
372
          uart1_rx_busy <= '1';
373
        end if;
374
      else
375
        if (uart1_rx_baud_cnt <= 0.0) then
376
          if (uart1_rx_bitcnt = 1) then
377
            uart1_rx_baud_cnt <= round(0.5 * uart1_baud_val_c);
378
          else
379
            uart1_rx_baud_cnt <= round(uart1_baud_val_c);
380
          end if;
381
          if (uart1_rx_bitcnt = 0) then
382
            uart1_rx_busy <= '0'; -- done
383
            i := to_integer(unsigned(uart1_rx_sreg(8 downto 1)));
384
 
385
            if (i < 32) or (i > 32+95) then -- printable char?
386
              report "NEORV32_TB_UART1.TX: (" & integer'image(i) & ")"; -- print code
387
            else
388
              report "NEORV32_TB_UART1.TX: " & character'val(i); -- print ASCII
389
            end if;
390
 
391
            if (i = 10) then -- Linux line break
392
              writeline(file_uart1_tx_out, l);
393
            elsif (i /= 13) then -- Remove additional carriage return
394
              write(l, character'val(i));
395
            end if;
396
          else
397
            uart1_rx_sreg   <= uart1_rx_sync(4) & uart1_rx_sreg(8 downto 1);
398
            uart1_rx_bitcnt <= uart1_rx_bitcnt - 1;
399
          end if;
400
        else
401
          uart1_rx_baud_cnt <= uart1_rx_baud_cnt - 1.0;
402
        end if;
403
      end if;
404
    end if;
405
  end process uart1_rx_console;
406
 
407
 
408 38 zero_gravi
  -- Wishbone Fabric ------------------------------------------------------------------------
409 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
410 38 zero_gravi
  -- CPU broadcast signals --
411
  wb_mem_a.addr  <= wb_cpu.addr;
412 39 zero_gravi
  wb_mem_a.wdata <= wb_cpu.wdata;
413
  wb_mem_a.we    <= wb_cpu.we;
414
  wb_mem_a.sel   <= wb_cpu.sel;
415
  wb_mem_a.tag   <= wb_cpu.tag;
416
  wb_mem_a.cyc   <= wb_cpu.cyc;
417
  wb_mem_a.lock  <= wb_cpu.lock;
418
 
419 38 zero_gravi
  wb_mem_b.addr  <= wb_cpu.addr;
420
  wb_mem_b.wdata <= wb_cpu.wdata;
421
  wb_mem_b.we    <= wb_cpu.we;
422
  wb_mem_b.sel   <= wb_cpu.sel;
423
  wb_mem_b.tag   <= wb_cpu.tag;
424
  wb_mem_b.cyc   <= wb_cpu.cyc;
425 39 zero_gravi
  wb_mem_b.lock  <= wb_cpu.lock;
426
 
427
  wb_mem_c.addr  <= wb_cpu.addr;
428
  wb_mem_c.wdata <= wb_cpu.wdata;
429
  wb_mem_c.we    <= wb_cpu.we;
430
  wb_mem_c.sel   <= wb_cpu.sel;
431
  wb_mem_c.tag   <= wb_cpu.tag;
432
  wb_mem_c.cyc   <= wb_cpu.cyc;
433
  wb_mem_c.lock  <= wb_cpu.lock;
434
 
435 47 zero_gravi
  wb_irq.addr    <= wb_cpu.addr;
436
  wb_irq.wdata   <= wb_cpu.wdata;
437
  wb_irq.we      <= wb_cpu.we;
438
  wb_irq.sel     <= wb_cpu.sel;
439
  wb_irq.tag     <= wb_cpu.tag;
440
  wb_irq.cyc     <= wb_cpu.cyc;
441
  wb_irq.lock    <= wb_cpu.lock;
442 40 zero_gravi
 
443 38 zero_gravi
  -- CPU read-back signals (no mux here since peripherals have "output gates") --
444 47 zero_gravi
  wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
445
  wb_cpu.ack   <= wb_mem_a.ack   or wb_mem_b.ack   or wb_mem_c.ack   or wb_irq.ack;
446
  wb_cpu.err   <= wb_mem_a.err   or wb_mem_b.err   or wb_mem_c.err   or wb_irq.err;
447 38 zero_gravi
 
448
  -- peripheral select via STROBE signal --
449
  wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
450
  wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
451 39 zero_gravi
  wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
452 47 zero_gravi
  wb_irq.stb   <= wb_cpu.stb when (wb_cpu.addr =  irq_trigger_c) else '0';
453 38 zero_gravi
 
454
 
455 39 zero_gravi
  -- Wishbone Memory A (simulated external IMEM) --------------------------------------------
456 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
457
  ext_mem_a_access: process(clk_gen)
458 23 zero_gravi
  begin
459
    if rising_edge(clk_gen) then
460
      -- control --
461 38 zero_gravi
      ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
462
 
463 23 zero_gravi
      -- write access --
464 38 zero_gravi
      if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
465 23 zero_gravi
        for i in 0 to 3 loop
466 38 zero_gravi
          if (wb_mem_a.sel(i) = '1') then
467
            ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_a.wdata(7+i*8 downto 0+i*8);
468 23 zero_gravi
          end if;
469
        end loop; -- i
470 2 zero_gravi
      end if;
471 38 zero_gravi
 
472 23 zero_gravi
      -- read access --
473 38 zero_gravi
      ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
474 23 zero_gravi
      -- virtual read and ack latency --
475 38 zero_gravi
      if (ext_mem_a_latency_c > 1) then
476
        for i in 1 to ext_mem_a_latency_c-1 loop
477
          ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
478
          ext_mem_a.ack(i)   <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
479 23 zero_gravi
        end loop;
480
      end if;
481 38 zero_gravi
 
482
      -- bus output register --
483
      wb_mem_a.err <= '0';
484
      if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
485
        wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
486
        wb_mem_a.ack   <= '1';
487
      else
488
        wb_mem_a.rdata <= (others => '0');
489
        wb_mem_a.ack   <= '0';
490
      end if;
491 23 zero_gravi
    end if;
492 38 zero_gravi
  end process ext_mem_a_access;
493 2 zero_gravi
 
494
 
495 39 zero_gravi
  -- Wishbone Memory B (simulated external DMEM) --------------------------------------------
496 38 zero_gravi
  -- -------------------------------------------------------------------------------------------
497
  ext_mem_b_access: process(clk_gen)
498
  begin
499
    if rising_edge(clk_gen) then
500
      -- control --
501
      ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
502 2 zero_gravi
 
503 38 zero_gravi
      -- write access --
504
      if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
505
        for i in 0 to 3 loop
506
          if (wb_mem_b.sel(i) = '1') then
507
            ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_b.wdata(7+i*8 downto 0+i*8);
508
          end if;
509
        end loop; -- i
510
      end if;
511 3 zero_gravi
 
512 38 zero_gravi
      -- read access --
513
      ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
514
      -- virtual read and ack latency --
515
      if (ext_mem_b_latency_c > 1) then
516
        for i in 1 to ext_mem_b_latency_c-1 loop
517
          ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
518
          ext_mem_b.ack(i)   <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
519
        end loop;
520
      end if;
521
 
522
      -- bus output register --
523
      wb_mem_b.err <= '0';
524
      if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
525
        wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
526
        wb_mem_b.ack   <= '1';
527
      else
528
        wb_mem_b.rdata <= (others => '0');
529
        wb_mem_b.ack   <= '0';
530
      end if;
531
    end if;
532
  end process ext_mem_b_access;
533
 
534
 
535 39 zero_gravi
  -- Wishbone Memory C (simulated external IO) ----------------------------------------------
536
  -- -------------------------------------------------------------------------------------------
537
  ext_mem_c_access: process(clk_gen)
538
  begin
539
    if rising_edge(clk_gen) then
540
      -- control --
541
      ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
542
 
543
      -- write access --
544
      if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
545
        for i in 0 to 3 loop
546
          if (wb_mem_c.sel(i) = '1') then
547
            ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
548
          end if;
549
        end loop; -- i
550
      end if;
551
 
552
      -- read access --
553
      ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
554
      -- virtual read and ack latency --
555
      if (ext_mem_c_latency_c > 1) then
556
        for i in 1 to ext_mem_c_latency_c-1 loop
557
          ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
558
          ext_mem_c.ack(i)   <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
559
        end loop;
560
      end if;
561
 
562
      -- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
563
      wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
564
 
565
      -- bus output register --
566
      if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
567
        wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
568
        wb_mem_c.ack   <= '1';
569
      else
570
        wb_mem_c.rdata <= (others => '0');
571
        wb_mem_c.ack   <= '0';
572
      end if;
573
    end if;
574
  end process ext_mem_c_access;
575
 
576
 
577 40 zero_gravi
  -- Wishbone IRQ Triggers ------------------------------------------------------------------
578
  -- -------------------------------------------------------------------------------------------
579 45 zero_gravi
  irq_trigger: process(clk_gen)
580 40 zero_gravi
  begin
581
    if rising_edge(clk_gen) then
582 47 zero_gravi
      -- bus interface --
583
      wb_irq.rdata  <= (others => '0');
584 48 zero_gravi
      wb_irq.ack    <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
585 47 zero_gravi
      wb_irq.err    <= '0';
586
      -- trigger IRQ using CSR.MIE bit layout --
587
      msi_ring      <= '0';
588
      mei_ring      <= '0';
589
      soc_firq_ring <= (others => '0');
590 48 zero_gravi
      if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
591 47 zero_gravi
        msi_ring         <= wb_irq.wdata(03); -- machine software interrupt
592
        mei_ring         <= wb_irq.wdata(11); -- machine software interrupt
593 50 zero_gravi
        --
594
        soc_firq_ring(0) <= wb_irq.wdata(26); -- fast interrupt SoC channel 0 (-> FIRQ channel 10)
595
        soc_firq_ring(1) <= wb_irq.wdata(27); -- fast interrupt SoC channel 1 (-> FIRQ channel 11)
596
        soc_firq_ring(2) <= wb_irq.wdata(28); -- fast interrupt SoC channel 2 (-> FIRQ channel 12)
597
        soc_firq_ring(3) <= wb_irq.wdata(29); -- fast interrupt SoC channel 3 (-> FIRQ channel 13)
598
        soc_firq_ring(4) <= wb_irq.wdata(30); -- fast interrupt SoC channel 4 (-> FIRQ channel 14)
599
        soc_firq_ring(5) <= wb_irq.wdata(31); -- fast interrupt SoC channel 5 (-> FIRQ channel 15)
600 40 zero_gravi
      end if;
601
    end if;
602 45 zero_gravi
  end process irq_trigger;
603 40 zero_gravi
 
604
 
605 2 zero_gravi
end neorv32_tb_rtl;

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