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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Application Start-Up Code & Minimal Runtime Environment >>              # */
/* # ********************************************************************************************* # */
/* # The start-up code provides a minimal runtime environment that catches all exceptions and      # */
/* # interrupts and delegates them to the handler functions (installed by user via dedicated       # */
/* # install function from the neorv32 runtime environment library).                               # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
  .file "crt0.S"
  .section .text
  .balign 4
  .global _start
 
 
  // IO region
  .equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
 
  // SYSINFO
  .equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4
  .equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
 
 
_start:
  .cfi_startproc
  .cfi_undefined ra
 
// *********************************************************
// Clear register file
// *********************************************************
__crt0_reg_file_clear:
//addi  x0,  x0, 0 // hardwired to zero
  addi  x1,  x0, 0
  addi  x2,  x1, 0
  addi  x3,  x2, 0
  addi  x4,  x3, 0
  addi  x5,  x4, 0
  addi  x6,  x5, 0
  addi  x7,  x6, 0
  addi  x8,  x7, 0
  addi  x9,  x8, 0
  addi x10,  x9, 0
  addi x11, x10, 0
  addi x12, x11, 0
  addi x13, x12, 0
  addi x14, x13, 0
  addi x15, x14, 0
 
// the following registers do not exist in rv32e
// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when
// compiling for a rv32e* architecture
#ifndef __RISCV_EMBEDDED_CPU__
  addi x16, x15, 0
  addi x17, x16, 0
  addi x18, x17, 0
  addi x19, x18, 0
  addi x20, x19, 0
  addi x21, x20, 0
  addi x22, x21, 0
  addi x23, x22, 0
  addi x24, x23, 0
  addi x25, x24, 0
  addi x26, x25, 0
  addi x27, x26, 0
  addi x28, x27, 0
  addi x29, x28, 0
  addi x30, x29, 0
  addi x31, x30, 0
#endif
 
 
// *********************************************************
// TEST AREA / DANGER ZONE
// *********************************************************
__crt0_tests:
  nop
 
 
// *********************************************************
// Setup stack pointer
// *********************************************************
__crt0_stack_pointer_init:
  lw    x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
  lw    x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size
  add   sp, x11, x12
  addi  sp, sp, -4 // stack pointer = last entry
  addi  fp, sp, 0  // frame pointer = stack pointer
 
 
// *********************************************************
// Setup global pointer
// *********************************************************
__crt0_global_pointer_init:
  .option push
  .option norelax
  la gp, __global_pointer$
  .option pop
 
 
// *********************************************************
// Init trap handler base address
// *********************************************************
__crt0_neorv32_trap_init:
  la    x11, __crt0_dummy_trap_handler
  csrw  mtvec, x11 // set address of first-level exception handler
 
 
// *********************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store access fault
// which is captured but actually ignored due to the dummy handler.
// *********************************************************
__crt0_reset_io:
  li x11, IO_BEGIN // start of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x11)
  addi x11, x11, 4
  bne  zero, x11, __crt0_reset_io_loop
 
 
// *********************************************************
// Clear .bss section (byte-wise)
// *********************************************************
__crt0_clear_bss:
  la x11, __crt0_bss_start
  la x12, __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x11, x12, __crt0_clear_bss_loop_end
  sb   zero, 0(x11)
  addi x11, x11, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// *********************************************************
// Copy initialized .data section from ROM to RAM (byte-wise)
// *********************************************************
__crt0_copy_data:
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// *********************************************************
// Call main function (with argc = argv = 0)
// *********************************************************
__crt0_main_entry:
 
  addi x10, zero, 0 // argc = 0
  addi x11, zero, 0 // argv = 0
 
  jal ra, main
 
 
// *********************************************************
// Go to endless sleep mode if main returns
// *********************************************************
__crt0_this_is_the_end:
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
  wfi
__crt0_this_is_the_end_end:
  j __crt0_this_is_the_end_end // in case Ziscr is not available
 
 
// *********************************************************
// dummy trap handler (for exceptions & IRQs)
// tries to move on to next instruction
// *********************************************************
  .global __crt0_dummy_trap_handler
  .balign 4
__crt0_dummy_trap_handler:
 
  addi  sp, sp, -8
  sw      x8, 0(sp)
  sw      x9, 4(sp)
 
  csrr  x8, mcause
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
__crt0_dummy_trap_handler_compute_return:
  csrr  x8, mepc
 
// is compressed instruction?
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8, x8, +2  // only this for compressed instructions
  csrw  mepc, x8    // set return address when compressed instruction
 
  addi  x8, zero, 3
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
 
// is uncompressed instruction
  csrr  x8, mepc
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
 
  lw      x9, 0(sp)
  lw      x8, 4(sp)
  addi  sp, sp, +8
 
  mret
 
  .cfi_endproc
  .end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	6	zero_gravi	`/* # << NEORV32 - crt0.S - Application Start-Up Code & Minimal Runtime Environment >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4	6	zero_gravi	`/* # The start-up code provides a minimal runtime environment that catches all exceptions and # */`
5	2	zero_gravi	`/* # interrupts and delegates them to the handler functions (installed by user via dedicated # */`
6			`/* # install function from the neorv32 runtime environment library). # */`
7			`/* # ********************************************************************************************* # */`
8			`/* # BSD 3-Clause License # */`
9			`/* # # */`
10			`/* # Copyright (c) 2020, Stephan Nolting. All rights reserved. # */`
11			`/* # # */`
12			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
13			`/* # permitted provided that the following conditions are met: # */`
14			`/* # # */`
15			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
16			`/* # conditions and the following disclaimer. # */`
17			`/* # # */`
18			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
19			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
20			`/* # provided with the distribution. # */`
21			`/* # # */`
22			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
23			`/* # endorse or promote products derived from this software without specific prior written # */`
24			`/* # permission. # */`
25			`/* # # */`
26			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
27			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
28			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
29			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
30			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
31			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
32			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
33			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
34			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
35			`/* # ********************************************************************************************* # */`
36			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
37			`/* ################################################################################################# */`
38
39			`.file "crt0.S"`
40			`.section .text`
41			`.balign 4`
42			`.global _start`
43
44
45			`// IO region`
46	14	zero_gravi	`.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region`
47	2	zero_gravi
48	12	zero_gravi	`// SYSINFO`
49	14	zero_gravi	`.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4`
50			`.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC`
51	2	zero_gravi
52	12	zero_gravi
53	2	zero_gravi	`_start:`
54			`.cfi_startproc`
55			`.cfi_undefined ra`
56
57			`// *********************************************************`
58			`// Clear register file`
59			`// *********************************************************`
60			`__crt0_reg_file_clear:`
61	14	zero_gravi	`//addi x0, x0, 0 // hardwired to zero`
62	2	zero_gravi	`addi x1, x0, 0`
63			`addi x2, x1, 0`
64			`addi x3, x2, 0`
65			`addi x4, x3, 0`
66			`addi x5, x4, 0`
67			`addi x6, x5, 0`
68			`addi x7, x6, 0`
69			`addi x8, x7, 0`
70			`addi x9, x8, 0`
71			`addi x10, x9, 0`
72			`addi x11, x10, 0`
73			`addi x12, x11, 0`
74			`addi x13, x12, 0`
75			`addi x14, x13, 0`
76			`addi x15, x14, 0`
77
78			`// the following registers do not exist in rv32e`
79	3	zero_gravi	`// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when`
80	14	zero_gravi	`// compiling for a rv32e* architecture`
81	2	zero_gravi	`#ifndef __RISCV_EMBEDDED_CPU__`
82			`addi x16, x15, 0`
83			`addi x17, x16, 0`
84			`addi x18, x17, 0`
85			`addi x19, x18, 0`
86			`addi x20, x19, 0`
87			`addi x21, x20, 0`
88			`addi x22, x21, 0`
89			`addi x23, x22, 0`
90			`addi x24, x23, 0`
91			`addi x25, x24, 0`
92			`addi x26, x25, 0`
93			`addi x27, x26, 0`
94			`addi x28, x27, 0`
95			`addi x29, x28, 0`
96			`addi x30, x29, 0`
97			`addi x31, x30, 0`
98			`#endif`
99
100
101			`// *********************************************************`
102	14	zero_gravi	`// TEST AREA / DANGER ZONE`
103	2	zero_gravi	`// *********************************************************`
104			`__crt0_tests:`
105			`nop`
106
107
108			`// *********************************************************`
109			`// Setup stack pointer`
110			`// *********************************************************`
111			`__crt0_stack_pointer_init:`
112	12	zero_gravi	`lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address`
113			`lw x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size`
114	2	zero_gravi	`add sp, x11, x12`
115			`addi sp, sp, -4 // stack pointer = last entry`
116			`addi fp, sp, 0 // frame pointer = stack pointer`
117
118
119			`// *********************************************************`
120			`// Setup global pointer`
121			`// *********************************************************`
122			`__crt0_global_pointer_init:`
123			`.option push`
124			`.option norelax`
125			`la gp, __global_pointer$`
126			`.option pop`
127
128
129			`// *********************************************************`
130	14	zero_gravi	`// Init trap handler base address`
131	2	zero_gravi	`// *********************************************************`
132	14	zero_gravi	`__crt0_neorv32_trap_init:`
133			`la x11, __crt0_dummy_trap_handler`
134	6	zero_gravi	`csrw mtvec, x11 // set address of first-level exception handler`
135	2	zero_gravi
136
137			`// *********************************************************`
138			`// Reset/deactivate IO/peripheral devices`
139			`// Devices, that are not implemented, will cause a store access fault`
140			`// which is captured but actually ignored due to the dummy handler.`
141			`// *********************************************************`
142			`__crt0_reset_io:`
143			`li x11, IO_BEGIN // start of processor-internal IO region`
144
145			`__crt0_reset_io_loop:`
146			`sw zero, 0(x11)`
147			`addi x11, x11, 4`
148			`bne zero, x11, __crt0_reset_io_loop`
149
150
151			`// *********************************************************`
152			`// Clear .bss section (byte-wise)`
153			`// *********************************************************`
154			`__crt0_clear_bss:`
155			`la x11, __crt0_bss_start`
156			`la x12, __crt0_bss_end`
157
158			`__crt0_clear_bss_loop:`
159			`bge x11, x12, __crt0_clear_bss_loop_end`
160			`sb zero, 0(x11)`
161			`addi x11, x11, 1`
162			`j __crt0_clear_bss_loop`
163
164			`__crt0_clear_bss_loop_end:`
165
166
167			`// *********************************************************`
168			`// Copy initialized .data section from ROM to RAM (byte-wise)`
169			`// *********************************************************`
170			`__crt0_copy_data:`
171			`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
172			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
173			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
174
175			`__crt0_copy_data_loop:`
176			`bge x12, x13, __crt0_copy_data_loop_end`
177			`lb x14, 0(x11)`
178			`sb x14, 0(x12)`
179			`addi x11, x11, 1`
180			`addi x12, x12, 1`
181			`j __crt0_copy_data_loop`
182
183			`__crt0_copy_data_loop_end:`
184
185
186			`// *********************************************************`
187			`// Call main function (with argc = argv = 0)`
188			`// *********************************************************`
189			`__crt0_main_entry:`
190
191			`addi x10, zero, 0 // argc = 0`
192			`addi x11, zero, 0 // argv = 0`
193
194			`jal ra, main`
195
196
197			`// *********************************************************`
198			`// Go to endless sleep mode if main returns`
199			`// *********************************************************`
200			`__crt0_this_is_the_end:`
201	11	zero_gravi	`csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)`
202	2	zero_gravi	`wfi`
203	11	zero_gravi	`__crt0_this_is_the_end_end:`
204			`j __crt0_this_is_the_end_end // in case Ziscr is not available`
205	2	zero_gravi
206
207			`// *********************************************************`
208	14	zero_gravi	`// dummy trap handler (for exceptions & IRQs)`
209			`// tries to move on to next instruction`
210	2	zero_gravi	`// *********************************************************`
211	14	zero_gravi	`.global __crt0_dummy_trap_handler`
212			`.balign 4`
213			`__crt0_dummy_trap_handler:`
214	2	zero_gravi
215	14	zero_gravi	`addi sp, sp, -8`
216			`sw x8, 0(sp)`
217			`sw x9, 4(sp)`
218	2	zero_gravi
219	14	zero_gravi	`csrr x8, mcause`
220			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
221	2	zero_gravi
222	14	zero_gravi	`__crt0_dummy_trap_handler_compute_return:`
223			`csrr x8, mepc`
224	2	zero_gravi
225	14	zero_gravi	`// is compressed instruction?`
226			`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
227			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
228	2	zero_gravi
229	14	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
230			`csrw mepc, x8 // set return address when compressed instruction`
231	2	zero_gravi
232	14	zero_gravi	`addi x8, zero, 3`
233			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
234	7	zero_gravi
235	14	zero_gravi	`// is uncompressed instruction`
236			`csrr x8, mepc`
237			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
238			`csrw mepc, x8`
239	2	zero_gravi
240	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
241	2	zero_gravi
242	14	zero_gravi	`lw x9, 0(sp)`
243			`lw x8, 4(sp)`
244			`addi sp, sp, +8`
245	2	zero_gravi
246			`mret`
247
248			`.cfi_endproc`
249			`.end`

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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 14