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/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file   "crt0.S"
.section .text.boot
.balign 4
.global _start
 
 
// IO region
.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
 
// SYSINFO
.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4
.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
// *********************************************************
// Clear register file
// Assume 'worst case': rv32e
// *********************************************************
__crt0_reg_file_clear:
//addi  x0,  x0, 0 // hardwired to zero
  addi  x1,  x0, 0
  addi  x2,  x0, 0
  addi  x3,  x0, 0
  addi  x4,  x0, 0
  addi  x5,  x0, 0
  addi  x6,  x0, 0
  addi  x7,  x0, 0
  addi  x8,  x0, 0
  addi  x9,  x0, 0
//addi x10,  x0, 0
//addi x11,  x0, 0
//addi x12,  x0, 0
  addi x13,  x0, 0
  addi x14,  x0, 0
  addi x15,  x0, 0
 
 
// *********************************************************
// Setup stack pointer
// *********************************************************
__crt0_stack_pointer_init:
  lw    x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
  lw    x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size
  add   sp, x11, x12
  addi  sp, sp, -4 // stack pointer = last entry
  addi  fp, sp, 0  // frame pointer = stack pointer
 
 
// *********************************************************
// Setup global pointer
// *********************************************************
#ifndef __BOOTLOADER_START_CODE__
__crt0_global_pointer_init:
.option push
.option norelax
  la gp, __global_pointer$
.option pop
#endif
 
 
// *********************************************************
// Init trap handler base address
// *********************************************************
__crt0_neorv32_trap_init:
  la    x11, __crt0_dummy_trap_handler
  csrw  mtvec, x11 // set address of first-level exception handler
 
 
// *********************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store access fault
// which is captured but actually ignored due to the dummy handler.
// *********************************************************
#ifndef __BOOTLOADER_START_CODE__
__crt0_reset_io:
  li x11, IO_BEGIN // start of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x11)
  addi x11, x11, 4
  bne  zero, x11, __crt0_reset_io_loop
#endif
 
 
// *********************************************************
// Clear .bss section (byte-wise)
// *********************************************************
#ifndef __BOOTLOADER_START_CODE__
__crt0_clear_bss:
  la x11, __crt0_bss_start
  la x12, __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x11, x12, __crt0_clear_bss_loop_end
  sb   zero, 0(x11)
  addi x11, x11, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
#endif
 
 
// *********************************************************
// Copy initialized .data section from ROM to RAM (byte-wise)
// *********************************************************
#ifndef __BOOTLOADER_START_CODE__
__crt0_copy_data:
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
#endif
 
 
// *********************************************************
// Call main function (with argc = argv = 0)
// *********************************************************
__crt0_main_entry:
 
  addi x10, zero, 0 // argc = 0
  addi x11, zero, 0 // argv = 0
 
  jal ra, main
 
 
// *********************************************************
// Go to endless sleep mode if main returns
// *********************************************************
__crt0_this_is_the_end:
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
  wfi
  j . // in case WFI is not available
 
 
// *********************************************************
// dummy trap handler (for exceptions & IRQs)
// tries to move on to next instruction
// *********************************************************
.global __crt0_dummy_trap_handler
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp, sp, -8
  sw      x8, 0(sp)
  sw      x9, 4(sp)
 
  csrr  x8, mcause
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8, mepc
 
// is compressed instruction?
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8, x8, +2  // only this for compressed instructions
  csrw  mepc, x8    // set return address when compressed instruction
 
  addi  x8, zero, 3
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
 
// is uncompressed instruction
  csrr  x8, mepc
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
 
  lw      x9, 0(sp)
  lw      x8, 4(sp)
  addi  sp, sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6			`/* # Copyright (c) 2020, Stephan Nolting. All rights reserved. # */`
7			`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	21	zero_gravi	`.file "crt0.S"`
36			`.section .text.boot`
37			`.balign 4`
38			`.global _start`
39	2	zero_gravi
40
41	21	zero_gravi	`// IO region`
42			`.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region`
43	2	zero_gravi
44	21	zero_gravi	`// SYSINFO`
45			`.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4`
46			`.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC`
47	2	zero_gravi
48	12	zero_gravi
49	2	zero_gravi	`_start:`
50	21	zero_gravi	`.cfi_startproc`
51			`.cfi_undefined ra`
52	2	zero_gravi
53			`// *********************************************************`
54			`// Clear register file`
55	21	zero_gravi	`// Assume 'worst case': rv32e`
56	2	zero_gravi	`// *********************************************************`
57			`__crt0_reg_file_clear:`
58	14	zero_gravi	`//addi x0, x0, 0 // hardwired to zero`
59	2	zero_gravi	`addi x1, x0, 0`
60	20	zero_gravi	`addi x2, x0, 0`
61			`addi x3, x0, 0`
62			`addi x4, x0, 0`
63			`addi x5, x0, 0`
64			`addi x6, x0, 0`
65			`addi x7, x0, 0`
66			`addi x8, x0, 0`
67			`addi x9, x0, 0`
68			`//addi x10, x0, 0`
69			`//addi x11, x0, 0`
70			`//addi x12, x0, 0`
71	21	zero_gravi	`addi x13, x0, 0`
72			`addi x14, x0, 0`
73	20	zero_gravi	`addi x15, x0, 0`
74	2	zero_gravi
75
76			`// *********************************************************`
77			`// Setup stack pointer`
78			`// *********************************************************`
79			`__crt0_stack_pointer_init:`
80	12	zero_gravi	`lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address`
81			`lw x12, SYSINFO_DSPACE_SIZE(zero) // data memory space size`
82	2	zero_gravi	`add sp, x11, x12`
83			`addi sp, sp, -4 // stack pointer = last entry`
84			`addi fp, sp, 0 // frame pointer = stack pointer`
85
86
87			`// *********************************************************`
88			`// Setup global pointer`
89			`// *********************************************************`
90	21	zero_gravi	`#ifndef __BOOTLOADER_START_CODE__`
91	2	zero_gravi	`__crt0_global_pointer_init:`
92	21	zero_gravi	`.option push`
93			`.option norelax`
94	2	zero_gravi	`la gp, __global_pointer$`
95	21	zero_gravi	`.option pop`
96			`#endif`
97	2	zero_gravi
98
99			`// *********************************************************`
100	14	zero_gravi	`// Init trap handler base address`
101	2	zero_gravi	`// *********************************************************`
102	14	zero_gravi	`__crt0_neorv32_trap_init:`
103			`la x11, __crt0_dummy_trap_handler`
104	6	zero_gravi	`csrw mtvec, x11 // set address of first-level exception handler`
105	2	zero_gravi
106
107			`// *********************************************************`
108			`// Reset/deactivate IO/peripheral devices`
109			`// Devices, that are not implemented, will cause a store access fault`
110			`// which is captured but actually ignored due to the dummy handler.`
111			`// *********************************************************`
112	21	zero_gravi	`#ifndef __BOOTLOADER_START_CODE__`
113	2	zero_gravi	`__crt0_reset_io:`
114			`li x11, IO_BEGIN // start of processor-internal IO region`
115
116			`__crt0_reset_io_loop:`
117			`sw zero, 0(x11)`
118			`addi x11, x11, 4`
119			`bne zero, x11, __crt0_reset_io_loop`
120	21	zero_gravi	`#endif`
121	2	zero_gravi
122
123			`// *********************************************************`
124			`// Clear .bss section (byte-wise)`
125			`// *********************************************************`
126	21	zero_gravi	`#ifndef __BOOTLOADER_START_CODE__`
127	2	zero_gravi	`__crt0_clear_bss:`
128			`la x11, __crt0_bss_start`
129			`la x12, __crt0_bss_end`
130
131			`__crt0_clear_bss_loop:`
132			`bge x11, x12, __crt0_clear_bss_loop_end`
133			`sb zero, 0(x11)`
134			`addi x11, x11, 1`
135			`j __crt0_clear_bss_loop`
136
137			`__crt0_clear_bss_loop_end:`
138	21	zero_gravi	`#endif`
139	2	zero_gravi
140
141			`// *********************************************************`
142			`// Copy initialized .data section from ROM to RAM (byte-wise)`
143			`// *********************************************************`
144	21	zero_gravi	`#ifndef __BOOTLOADER_START_CODE__`
145	2	zero_gravi	`__crt0_copy_data:`
146			`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
147			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
148			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
149
150			`__crt0_copy_data_loop:`
151			`bge x12, x13, __crt0_copy_data_loop_end`
152			`lb x14, 0(x11)`
153			`sb x14, 0(x12)`
154			`addi x11, x11, 1`
155			`addi x12, x12, 1`
156			`j __crt0_copy_data_loop`
157
158			`__crt0_copy_data_loop_end:`
159	21	zero_gravi	`#endif`
160	2	zero_gravi
161
162			`// *********************************************************`
163			`// Call main function (with argc = argv = 0)`
164			`// *********************************************************`
165			`__crt0_main_entry:`
166
167			`addi x10, zero, 0 // argc = 0`
168			`addi x11, zero, 0 // argv = 0`
169
170			`jal ra, main`
171
172
173			`// *********************************************************`
174			`// Go to endless sleep mode if main returns`
175			`// *********************************************************`
176			`__crt0_this_is_the_end:`
177	11	zero_gravi	`csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)`
178	2	zero_gravi	`wfi`
179	21	zero_gravi	`j . // in case WFI is not available`
180	2	zero_gravi
181
182			`// *********************************************************`
183	14	zero_gravi	`// dummy trap handler (for exceptions & IRQs)`
184			`// tries to move on to next instruction`
185	2	zero_gravi	`// *********************************************************`
186	21	zero_gravi	`.global __crt0_dummy_trap_handler`
187			`.balign 4`
188	14	zero_gravi	`__crt0_dummy_trap_handler:`
189	2	zero_gravi
190	14	zero_gravi	`addi sp, sp, -8`
191			`sw x8, 0(sp)`
192			`sw x9, 4(sp)`
193	2	zero_gravi
194	14	zero_gravi	`csrr x8, mcause`
195			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
196	2	zero_gravi
197	14	zero_gravi	`csrr x8, mepc`
198	2	zero_gravi
199	14	zero_gravi	`// is compressed instruction?`
200			`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
201			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
202	2	zero_gravi
203	14	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
204			`csrw mepc, x8 // set return address when compressed instruction`
205	2	zero_gravi
206	14	zero_gravi	`addi x8, zero, 3`
207			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
208	7	zero_gravi
209	14	zero_gravi	`// is uncompressed instruction`
210			`csrr x8, mepc`
211			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
212			`csrw mepc, x8`
213	2	zero_gravi
214	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
215	2	zero_gravi
216	14	zero_gravi	`lw x9, 0(sp)`
217			`lw x8, 4(sp)`
218			`addi sp, sp, +8`
219	2	zero_gravi
220			`mret`
221
222	21	zero_gravi	`.cfi_endproc`
223			`.end`

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[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 21