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// #################################################################################################
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// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file neorv32.h
38
 * @author Stephan Nolting
39
 *
40
 * @brief Main NEORV32 core library file.
41
 *
42
 * @details This file defines the addresses of the IO devices and their according
43
 * registers and register bits as well as the available CPU CSRs and flags.
44
 **************************************************************************/
45
 
46
#ifndef neorv32_h
47
#define neorv32_h
48
 
49
// Standard libraries
50
#include <stdint.h>
51
#include <inttypes.h>
52
#include <limits.h>
53
 
54
 
55
/**********************************************************************//**
56
 * Available CPU Control and Status Registers (CSRs)
57
 **************************************************************************/
58
enum NEORV32_CPU_CSRS_enum {
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  CSR_MSTATUS     = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
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  CSR_MISA        = 0x301, /**< 0x301 - misa    (r/-): CPU ISA and extensions (read-only in NEORV32) */
61 6 zero_gravi
  CSR_MIE         = 0x304, /**< 0x304 - mie     (r/w): Machine interrupt-enable register */
62
  CSR_MTVEC       = 0x305, /**< 0x305 - mtvec   (r/w): Machine trap-handler base address (for ALL traps) */
63 2 zero_gravi
 
64
  CSR_MSCRATCH    = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
65
  CSR_MEPC        = 0x341, /**< 0x341 - mepc     (r/w): Machine exception program counter */
66 14 zero_gravi
  CSR_MCAUSE      = 0x342, /**< 0x342 - mcause   (r/-): Machine trap cause */
67 12 zero_gravi
  CSR_MTVAL       = 0x343, /**< 0x343 - mtval    (r/w): Machine bad address or instruction */
68 2 zero_gravi
  CSR_MIP         = 0x344, /**< 0x344 - mip      (r/w): Machine interrupt pending register */
69
 
70 15 zero_gravi
  CSR_PMPCFG0     = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
71
  CSR_PMPCFG1     = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
72
 
73
  CSR_PMPADDR0    = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */
74
  CSR_PMPADDR1    = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */
75
  CSR_PMPADDR2    = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */
76
  CSR_PMPADDR3    = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */
77
  CSR_PMPADDR4    = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */
78
  CSR_PMPADDR5    = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */
79
  CSR_PMPADDR6    = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
80
  CSR_PMPADDR7    = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
81
 
82 11 zero_gravi
  CSR_MCYCLE      = 0xb00, /**< 0xb00 - mcycle    (r/w): Machine cycle counter low word */
83
  CSR_MINSTRET    = 0xb02, /**< 0xb02 - minstret  (r/w): Machine instructions-retired counter low word */
84 12 zero_gravi
  CSR_MCYCLEH     = 0xb80, /**< 0xb80 - mcycleh   (r/w): Machine cycle counter high word - only 20-bit wide!*/
85
  CSR_MINSTRETH   = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */
86 2 zero_gravi
 
87 12 zero_gravi
  CSR_CYCLE       = 0xc00, /**< 0xc00 - cycle    (r/-): Cycle counter low word (from MCYCLE) */
88
  CSR_TIME        = 0xc01, /**< 0xc01 - time     (r/-): Timer low word (from MTIME.TIME_LO) */
89
  CSR_INSTRET     = 0xc02, /**< 0xc02 - instret  (r/-): Instructions-retired counter low word (from MINSTRET) */
90 2 zero_gravi
 
91 12 zero_gravi
  CSR_CYCLEH      = 0xc80, /**< 0xc80 - cycleh   (r/-): Cycle counter high word (from MCYCLEH) - only 20-bit wide! */
92
  CSR_TIMEH       = 0xc81, /**< 0xc81 - timeh    (r/-): Timer high word (from MTIME.TIME_HI) */
93
  CSR_INSTRETH    = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) - only 20-bit wide! */
94 2 zero_gravi
 
95 12 zero_gravi
  CSR_MVENDORID   = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
96
  CSR_MARCHID     = 0xf12, /**< 0xf12 - marchid   (r/-): Architecture ID */
97
  CSR_MIMPID      = 0xf13, /**< 0xf13 - mimpid    (r/-): Implementation ID/version */
98
  CSR_MHARTID     = 0xf14  /**< 0xf14 - mhartid   (r/-): Hardware thread ID (always 0) */
99 2 zero_gravi
};
100
 
101
 
102
/**********************************************************************//**
103
 * CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
104
 **************************************************************************/
105
enum NEORV32_CPU_MSTATUS_enum {
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  CPU_MSTATUS_MIE   =  3, /**< CPU mstatus CSR (3): Machine interrupt enable bit (r/w) */
107
  CPU_MSTATUS_MPIE  =  7, /**< CPU mstatus CSR (7): Machine previous interrupt enable bit (r/w) */
108
  CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): Machine previous privilege mode bit low (r/w) */
109
  CPU_MSTATUS_MPP_H = 12  /**< CPU mstatus CSR (12): Machine previous privilege mode bit high (r/w) */
110 2 zero_gravi
};
111
 
112
 
113
/**********************************************************************//**
114
 * CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
115
 **************************************************************************/
116
enum NEORV32_CPU_MIE_enum {
117 14 zero_gravi
  CPU_MIE_MSIE   =  3, /**< CPU mie CSR (3): Machine software interrupt enable (r/w) */
118
  CPU_MIE_MTIE   =  7, /**< CPU mie CSR (7): Machine timer interrupt enable bit (r/w) */
119
  CPU_MIE_MEIE   = 11, /**< CPU mie CSR (11): Machine external interrupt enable bit (r/w) */
120
  CPU_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): Fast interrupt channel 0 enable bit (r/w) */
121
  CPU_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): Fast interrupt channel 1 enable bit (r/w) */
122
  CPU_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): Fast interrupt channel 2 enable bit (r/w) */
123
  CPU_MIE_FIRQ3E = 19  /**< CPU mie CSR (19): Fast interrupt channel 3 enable bit (r/w) */
124 2 zero_gravi
};
125
 
126
 
127
/**********************************************************************//**
128 12 zero_gravi
 * CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.)
129 2 zero_gravi
 **************************************************************************/
130
enum NEORV32_CPU_MIP_enum {
131 14 zero_gravi
  CPU_MIP_MSIP   =  3, /**< CPU mip CSR (3): Machine software interrupt pending (r/-) */
132
  CPU_MIP_MTIP   =  7, /**< CPU mip CSR (7): Machine timer interrupt pending (r/-) */
133
  CPU_MIP_MEIP   = 11, /**< CPU mip CSR (11): Machine external interrupt pending (r/-) */
134
 
135
  CPU_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): Fast interrupt channel 0 pending (r/-) */
136
  CPU_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): Fast interrupt channel 1 pending (r/-) */
137
  CPU_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): Fast interrupt channel 2 pending (r/-) */
138
  CPU_MIP_FIRQ3P = 19  /**< CPU mip CSR (19): Fast interrupt channel 3 pending (r/-) */
139 2 zero_gravi
};
140
 
141
 
142
/**********************************************************************//**
143 16 zero_gravi
 * CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
144 6 zero_gravi
 **************************************************************************/
145
enum NEORV32_CPU_MISA_enum {
146 15 zero_gravi
  CPU_MISA_C_EXT      =  2, /**< CPU misa CSR  (2): C: Compressed instructions CPU extension available (r/-)*/
147 6 zero_gravi
  CPU_MISA_E_EXT      =  4, /**< CPU misa CSR  (3): E: Embedded CPU extension available (r/-) */
148
  CPU_MISA_I_EXT      =  8, /**< CPU misa CSR  (8): I: Base integer ISA CPU extension available (r/-) */
149 15 zero_gravi
  CPU_MISA_M_EXT      = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
150
  CPU_MISA_U_EXT      = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
151 6 zero_gravi
  CPU_MISA_X_EXT      = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
152
  CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
153
  CPU_MISA_MXL_HI_EXT = 31  /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
154
};
155
 
156
 
157
/**********************************************************************//**
158 14 zero_gravi
 * Trap codes from mcause CSR.
159 2 zero_gravi
 **************************************************************************/
160 12 zero_gravi
enum NEORV32_EXCEPTION_CODES_enum {
161 14 zero_gravi
  TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
162
  TRAP_CODE_I_ACCESS     = 0x00000001, /**< 0.1: Instruction (bus) access fault */
163
  TRAP_CODE_I_ILLEGAL    = 0x00000002, /**< 0.2: Illegal instruction */
164
  TRAP_CODE_BREAKPOINT   = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */
165
  TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */
166
  TRAP_CODE_L_ACCESS     = 0x00000005, /**< 0.5: Load (bus) access fault */
167
  TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
168
  TRAP_CODE_S_ACCESS     = 0x00000007, /**< 0.7: Store (bus) access fault */
169
  TRAP_CODE_MENV_CALL    = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
170
  TRAP_CODE_MSI          = 0x80000003, /**< 1.3: Machine software interrupt */
171
  TRAP_CODE_MTI          = 0x80000007, /**< 1.7: Machine timer interrupt */
172
  TRAP_CODE_MEI          = 0x8000000b, /**< 1.11: Machine external interrupt */
173
  TRAP_CODE_FIRQ_0       = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
174
  TRAP_CODE_FIRQ_1       = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
175
  TRAP_CODE_FIRQ_2       = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
176
  TRAP_CODE_FIRQ_3       = 0x80000013  /**< 1.19: Fast interrupt channel 3 */
177 12 zero_gravi
};
178
 
179
 
180
/**********************************************************************//**
181 2 zero_gravi
 * Processor clock prescalers
182
 **************************************************************************/
183
enum NEORV32_CLOCK_PRSC_enum {
184
  CLK_PRSC_2    =  0, /**< CPU_CLK / 2 */
185
  CLK_PRSC_4    =  1, /**< CPU_CLK / 4 */
186
  CLK_PRSC_8    =  2, /**< CPU_CLK / 8 */
187
  CLK_PRSC_64   =  3, /**< CPU_CLK / 64 */
188
  CLK_PRSC_128  =  4, /**< CPU_CLK / 128 */
189
  CLK_PRSC_1024 =  5, /**< CPU_CLK / 1024 */
190
  CLK_PRSC_2048 =  6, /**< CPU_CLK / 2048 */
191
  CLK_PRSC_4096 =  7  /**< CPU_CLK / 4096 */
192
};
193
 
194
 
195
/**********************************************************************//**
196
 * @name Helper macros for easy memory-mapped register access
197
 **************************************************************************/
198
/**@{*/
199
/** memory-mapped byte (8-bit) read/write register */
200
#define IO_REG8  (volatile uint8_t*)
201
/** memory-mapped half-word (16-bit) read/write register */
202
#define IO_REG16 (volatile uint16_t*)
203
/** memory-mapped word (32-bit) read/write register */
204
#define IO_REG32 (volatile uint32_t*)
205
/** memory-mapped double-word (64-bit) read/write register */
206
#define IO_REG64 (volatile uint64_t*)
207
/** memory-mapped byte (8-bit) read-only register */
208
#define IO_ROM8  (const volatile uint8_t*) 
209
/** memory-mapped half-word (16-bit) read-only register */
210
#define IO_ROM16 (const volatile uint16_t*)
211
/** memory-mapped word (32-bit) read-only register */
212
#define IO_ROM32 (const volatile uint32_t*)
213
/** memory-mapped double-word (64-bit) read-only register */
214
#define IO_ROM64 (const volatile uint64_t*)
215
/**@}*/
216
 
217
 
218
/**********************************************************************//**
219
 * @name Address space sections
220
 **************************************************************************/
221
/**@{*/
222
/** instruction memory base address (r/w/x) */
223 6 zero_gravi
// -> use value from MEM_ISPACE_BASE CSR
224 2 zero_gravi
/** data memory base address (r/w/x) */
225 6 zero_gravi
// -> use value from MEM_DSPACE_BASE CSR
226 2 zero_gravi
/** bootloader memory base address (r/-/x) */
227 6 zero_gravi
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
228 2 zero_gravi
/** peripheral/IO devices memory base address (r/w/x) */
229 6 zero_gravi
#define IO_BASE_ADDRESS (0xFFFFFF80UL)
230 2 zero_gravi
/**@}*/
231
 
232
 
233
/**********************************************************************//**
234
 * @name IO Device: General Purpose Input/Output Port Unit (GPIO)
235
 **************************************************************************/
236
/**@{*/
237
/** GPIO parallel input port (r/-) */
238 6 zero_gravi
#define GPIO_INPUT  (*(IO_ROM32 0xFFFFFF80UL))
239 2 zero_gravi
/** GPIO parallel output port (r/w) */
240 6 zero_gravi
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
241 2 zero_gravi
/**@}*/
242
 
243
 
244
/**********************************************************************//**
245
 * @name IO Device: Watchdog Timer (WDT)
246
 **************************************************************************/
247
/**@{*/
248
/** Watchdog control register (r/w) */
249 6 zero_gravi
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
250 2 zero_gravi
 
251
/** WTD control register bits */
252
enum NEORV32_WDT_CT_enum {
253
  WDT_CT_CLK_SEL0     =  0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
254
  WDT_CT_CLK_SEL1     =  1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
255
  WDT_CT_CLK_SEL2     =  2, /**< WDT control register(2) (r/w): Clock prescaler select bit 2 */
256
  WDT_CT_EN           =  3, /**< WDT control register(3) (r/w): Watchdog enable */
257
  WDT_CT_MODE         =  4, /**< WDT control register(4) (r/w): Watchdog mode; when 0: timeout causes interrupt; when 1: timeout causes processor reset */
258
  WDT_CT_CAUSE        =  5, /**< WDT control register(5) (r/-): Last action (reset/IRQ) cause (0: external reset, 1: watchdog timeout) */
259
  WDT_CT_PWFAIL       =  6, /**< WDT control register(6) (r/-): Last Watchdog action (reset/IRQ) caused by wrong password when 1 */
260
 
261
  WDT_CT_PASSWORD_LSB =  8, /**< WDT control register(8)  (-/w): First bit / position begin for watchdog access password */
262
  WDT_CT_PASSWORD_MSB = 15  /**< WDT control register(15) (-/w): Last bit / position end for watchdog access password */
263
};
264
 
265
/** Watchdog access passwort, must be set in WDT_CT bits 15:8 for every control register access */
266
#define WDT_PASSWORD 0x47
267
/**@}*/
268
 
269
 
270
/**********************************************************************//**
271
 * @name IO Device: Machine System Timer (MTIME)
272
 **************************************************************************/
273
/**@{*/
274 11 zero_gravi
/** MTIME (time register) low word (r/w) */
275
#define MTIME_LO     (*(IO_REG32 0xFFFFFF90UL))
276
/** MTIME (time register) high word (r/w) */
277
#define MTIME_HI     (*(IO_REG32 0xFFFFFF94UL))
278 2 zero_gravi
/** MTIMECMP (time compare register) low word (r/w) */
279 6 zero_gravi
#define MTIMECMP_LO  (*(IO_REG32 0xFFFFFF98UL))
280 2 zero_gravi
/** MTIMECMP (time register) high word (r/w) */
281 6 zero_gravi
#define MTIMECMP_HI  (*(IO_REG32 0xFFFFFF9CUL))
282 2 zero_gravi
 
283 11 zero_gravi
/** MTIME (time register) 64-bit access (r/w) */
284
#define MTIME        (*(IO_REG64 (&MTIME_LO)))
285 2 zero_gravi
/** MTIMECMP (time compare register) low word (r/w) */
286
#define MTIMECMP     (*(IO_REG64 (&MTIMECMP_LO)))
287
/**@}*/
288
 
289
 
290
/**********************************************************************//**
291
 * @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
292
 **************************************************************************/
293
/**@{*/
294
/** UART control register (r/w) */
295 6 zero_gravi
#define UART_CT  (*(IO_REG32 0xFFFFFFA0UL))
296 2 zero_gravi
/** UART receive/transmit data register (r/w) */
297 6 zero_gravi
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
298 2 zero_gravi
 
299
/** UART control register bits */
300
enum NEORV32_UART_CT_enum {
301
  UART_CT_BAUD00  =  0, /**< UART control register(0)  (r/w): BAUD rate config value lsb (12-bi, bit 0) */
302
  UART_CT_BAUD01  =  1, /**< UART control register(1)  (r/w): BAUD rate config value (12-bi, bit 1) */
303
  UART_CT_BAUD02  =  2, /**< UART control register(2)  (r/w): BAUD rate config value (12-bi, bit 2) */
304
  UART_CT_BAUD03  =  3, /**< UART control register(3)  (r/w): BAUD rate config value (12-bi, bit 3) */
305
  UART_CT_BAUD04  =  4, /**< UART control register(4)  (r/w): BAUD rate config value (12-bi, bit 4) */
306
  UART_CT_BAUD05  =  5, /**< UART control register(5)  (r/w): BAUD rate config value (12-bi, bit 4) */
307
  UART_CT_BAUD06  =  6, /**< UART control register(6)  (r/w): BAUD rate config value (12-bi, bit 5) */
308
  UART_CT_BAUD07  =  7, /**< UART control register(7)  (r/w): BAUD rate config value (12-bi, bit 6) */
309
  UART_CT_BAUD08  =  8, /**< UART control register(8)  (r/w): BAUD rate config value (12-bi, bit 7) */
310
  UART_CT_BAUD09  =  9, /**< UART control register(9)  (r/w): BAUD rate config value (12-bi, bit 8) */
311
  UART_CT_BAUD10  = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
312
  UART_CT_BAUD11  = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0)*/
313
 
314
  UART_CT_PRSC0   = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
315
  UART_CT_PRSC1   = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
316
  UART_CT_PRSC2   = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
317
  UART_CT_RXOR    = 27, /**< UART control register(27) (r/-): RX data overrun when set */
318
  UART_CT_EN      = 28, /**< UART control register(28) (r/w): UART global enable */
319
  UART_CT_RX_IRQ  = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
320
  UART_CT_TX_IRQ  = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
321
  UART_CT_TX_BUSY = 31  /**< UART control register(31) (r/-): Transmitter is busy when set */
322
};
323
 
324
/** UART receive/transmit data register bits */
325
enum NEORV32_UART_DATA_enum {
326
  UART_DATA_LSB   =  0, /**< UART receive/transmit data register(0)  (r/w): Receive/transmit data LSB (bit 0) */
327
  UART_DATA_MSB   =  7, /**< UART receive/transmit data register(7)  (r/w): Receive/transmit data MSB (bit 7) */
328
  UART_DATA_AVAIL = 31  /**< UART receive/transmit data register(31) (r/-): RX data available when set */
329
};
330
/**@}*/
331
 
332
 
333
/**********************************************************************//**
334 10 zero_gravi
 * @name IO Device: Serial Peripheral Interface Controller (SPI)
335 2 zero_gravi
 **************************************************************************/
336
/**@{*/
337
/** SPI control register (r/w) */
338 6 zero_gravi
#define SPI_CT  (*(IO_REG32 0xFFFFFFA8UL))
339 2 zero_gravi
/** SPI receive/transmit data register (r/w) */
340 6 zero_gravi
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
341 2 zero_gravi
 
342
/** SPI control register bits */
343
enum NEORV32_SPI_CT_enum {
344
  SPI_CT_CS0    =  0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
345
  SPI_CT_CS1    =  1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
346
  SPI_CT_CS2    =  2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */
347
  SPI_CT_CS3    =  3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
348
  SPI_CT_CS4    =  4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
349
  SPI_CT_CS5    =  5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
350
  SPI_CT_CS6    =  6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
351
  SPI_CT_CS7    =  7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
352
 
353
  SPI_CT_EN     =  8, /**< UART control register(8) (r/w): SPI unit enable */
354
  SPI_CT_CPHA   =  9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
355
  SPI_CT_PRSC0  = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
356
  SPI_CT_PRSC1  = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
357
  SPI_CT_PRSC2  = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
358
  SPI_CT_DIR    = 13, /**< UART control register(13) (r/w): Shift direction (0: MSB first, 1: LSB first) */
359
  SPI_CT_SIZE0  = 14, /**< UART control register(14) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
360
  SPI_CT_SIZE1  = 15, /**< UART control register(15) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
361
 
362
  SPI_CT_IRQ_EN = 16, /**< UART control register(16) (r/w): Transfer done interrupt enable */
363
 
364
  SPI_CT_BUSY   = 31  /**< UART control register(31) (r/-): SPI busy flag */
365
};
366
/**@}*/
367
 
368
 
369
/**********************************************************************//**
370 10 zero_gravi
 * @name IO Device: Two-Wire Interface Controller (TWI)
371 2 zero_gravi
 **************************************************************************/
372
/**@{*/
373
/** TWI control register (r/w) */
374 6 zero_gravi
#define TWI_CT   (*(IO_REG32 0xFFFFFFB0UL))
375 2 zero_gravi
/** TWI receive/transmit data register (r/w) */
376 6 zero_gravi
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
377 2 zero_gravi
 
378
/** TWI control register bits */
379
enum NEORV32_TWI_CT_enum {
380
  TWI_CT_EN     =  0, /**< TWI control register(0) (r/w): TWI enable */
381
  TWI_CT_START  =  1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
382
  TWI_CT_STOP   =  2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
383
  TWI_CT_IRQ_EN =  3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
384
  TWI_CT_PRSC0  =  4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
385
  TWI_CT_PRSC1  =  5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
386
  TWI_CT_PRSC2  =  6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
387 10 zero_gravi
  TWI_CT_MACK   =  7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
388 2 zero_gravi
 
389
  TWI_CT_ACK    = 30, /**< TWI control register(30) (r/-): ACK received when set */
390
  TWI_CT_BUSY   = 31  /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
391
};
392
 
393
/** WTD receive/transmit data register bits */
394
enum NEORV32_TWI_DATA_enum {
395
  TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
396
  TWI_DATA_MSB = 7  /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
397
};
398
/**@}*/
399
 
400
 
401
/**********************************************************************//**
402
 * @name IO Device: Pulse Width Modulation Controller (PWM)
403
 **************************************************************************/
404
/**@{*/
405
/** PWM control register (r/w) */
406 6 zero_gravi
#define PWM_CT   (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
407 2 zero_gravi
/** PWM duty cycle register (4-channels) (r/w) */
408 6 zero_gravi
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
409 2 zero_gravi
 
410
/** PWM control register bits */
411
enum NEORV32_PWM_CT_enum {
412
  PWM_CT_EN    =  0, /**< PWM control register(0) (r/w): PWM controller enable */
413
  PWM_CT_PRSC0 =  1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
414
  PWM_CT_PRSC1 =  2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
415
  PWM_CT_PRSC2 =  3  /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
416
};
417
 
418
/**PWM duty cycle register bits */
419
enum NEORV32_PWM_DUTY_enum {
420
  PWM_DUTY_CH0_LSB =  0, /**< PWM duty cycle register(0)  (r/w): Channel 0 duty cycle (8-bit) LSB */
421
  PWM_DUTY_CH0_MSB =  7, /**< PWM duty cycle register(7)  (r/w): Channel 0 duty cycle (8-bit) MSB */
422
  PWM_DUTY_CH1_LSB =  8, /**< PWM duty cycle register(8)  (r/w): Channel 1 duty cycle (8-bit) LSB */
423
  PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
424
  PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
425
  PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
426
  PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
427
  PWM_DUTY_CH3_MSB = 31  /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
428
};
429
/**@}*/
430
 
431
 
432
/**********************************************************************//**
433
 * @name IO Device: True Random Number Generator (TRNG)
434
 **************************************************************************/
435
/**@{*/
436
/** TRNG control register (r/w) */
437 6 zero_gravi
#define TRNG_CT   (*(IO_REG32 0xFFFFFFC0UL))
438 2 zero_gravi
/** TRNG data register (r/-) */
439 6 zero_gravi
#define TRNG_DATA (*(IO_ROM32 0xFFFFFFC4UL))
440 2 zero_gravi
 
441
/** TRNG control register bits */
442
enum NEORV32_TRNG_CT_enum {
443
  TRNG_CT_TAP_LSB =  0, /**< TRNG control register(0)  (r/w): TAP mask (16-bit) LSB */
444
  TRNG_CT_TAP_MSB = 15, /**< TRNG control register(15) (r/w): TAP mask (16-bit) MSB */
445
  TRNG_CT_EN      = 31  /**< TRNG control register(31) (r/w): TRNG enable */
446
};
447
 
448
/** WTD data register bits */
449
enum NEORV32_TRNG_DUTY_enum {
450
  TRNG_DATA_LSB   =  0, /**< TRNG data register(0)  (r/-): Random data (16-bit) LSB */
451
  TRNG_DATA_MSB   = 15, /**< TRNG data register(15) (r/-): Random data (16-bit) MSB */
452
  TRNG_DATA_VALID = 31  /**< TRNG data register(31) (r/-): Random data output valid */
453
};
454
/**@}*/
455
 
456
 
457 3 zero_gravi
/**********************************************************************//**
458
 * @name IO Device: Dummy Device (DEVNULL)
459
 **************************************************************************/
460
/**@{*/
461 6 zero_gravi
/** DEVNULL data register (r/w) */
462 12 zero_gravi
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFC8UL))
463 3 zero_gravi
/**@}*/
464
 
465
 
466 12 zero_gravi
/**********************************************************************//**
467
 * @name IO Device: System Configuration Info Memory (SYSINFO)
468
 **************************************************************************/
469
/**@{*/
470
/** SYSINFO(0): Clock speed */
471
#define SYSINFO_CLK         (*(IO_ROM32 0xFFFFFFE0UL))
472
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
473
#define SYSINFO_USER_CODE   (*(IO_ROM32 0xFFFFFFE4UL))
474
/** SYSINFO(2): Clock speed */
475
#define SYSINFO_FEATURES    (*(IO_ROM32 0xFFFFFFE8UL))
476
/** SYSINFO(3): reserved */
477
#define SYSINFO_reserved1   (*(IO_ROM32 0xFFFFFFECUL))
478
/** SYSINFO(4): Instruction memory address space base */
479
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
480
/** SYSINFO(5): Data memory address space base */
481
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
482
/** SYSINFO(6): Instruction memory address space size in bytes */
483
#define SYSINFO_ISPACE_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
484
/** SYSINFO(7): Data memory address space size in bytes */
485
#define SYSINFO_DSPACE_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
486
/**@}*/
487
 
488
 
489
/**********************************************************************//**
490
 * SYSINFO_FEATURES (r/-): Implemented processor devices/features
491
 **************************************************************************/
492
 enum NEORV32_SYSINFO_FEATURES_enum {
493
  SYSINFO_FEATURES_BOOTLOADER       =  0, /**< SYSINFO_FEATURES  (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
494
  SYSINFO_FEATURES_MEM_EXT          =  1, /**< SYSINFO_FEATURES  (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
495
  SYSINFO_FEATURES_MEM_INT_IMEM     =  2, /**< SYSINFO_FEATURES  (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
496
  SYSINFO_FEATURES_MEM_INT_IMEM_ROM =  3, /**< SYSINFO_FEATURES  (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
497
  SYSINFO_FEATURES_MEM_INT_DMEM     =  4, /**< SYSINFO_FEATURES  (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
498
 
499
  SYSINFO_FEATURES_IO_GPIO          = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
500
  SYSINFO_FEATURES_IO_MTIME         = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
501
  SYSINFO_FEATURES_IO_UART          = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
502
  SYSINFO_FEATURES_IO_SPI           = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
503
  SYSINFO_FEATURES_IO_TWI           = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
504
  SYSINFO_FEATURES_IO_PWM           = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
505
  SYSINFO_FEATURES_IO_WDT           = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
506 14 zero_gravi
 
507 12 zero_gravi
  SYSINFO_FEATURES_IO_TRNG          = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
508
  SYSINFO_FEATURES_IO_DEVNULL       = 25  /**< SYSINFO_FEATURES (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
509
};
510
 
511
 
512 2 zero_gravi
// ----------------------------------------------------------------------------
513
// Include all IO driver headers
514
// ----------------------------------------------------------------------------
515
// cpu core
516
#include "neorv32_cpu.h"
517
 
518
// neorv32 runtime environment
519
#include "neorv32_rte.h"
520
 
521
// io/peripheral devices
522
#include "neorv32_gpio.h"
523
#include "neorv32_mtime.h"
524
#include "neorv32_pwm.h"
525
#include "neorv32_spi.h"
526
#include "neorv32_trng.h"
527
#include "neorv32_twi.h"
528
#include "neorv32_uart.h"
529
#include "neorv32_wdt.h"
530
 
531
#endif // neorv32_h

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