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// #################################################################################################
2
// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
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// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
32
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
34
 
35
 
36
/**********************************************************************//**
37
 * @file neorv32.h
38
 * @author Stephan Nolting
39
 *
40 20 zero_gravi
 * @brief Main NEORV32 core library include file.
41 2 zero_gravi
 **************************************************************************/
42
 
43
#ifndef neorv32_h
44
#define neorv32_h
45
 
46
// Standard libraries
47
#include <stdint.h>
48
#include <inttypes.h>
49
#include <limits.h>
50
 
51
 
52
/**********************************************************************//**
53
 * Available CPU Control and Status Registers (CSRs)
54
 **************************************************************************/
55
enum NEORV32_CPU_CSRS_enum {
56 6 zero_gravi
  CSR_MSTATUS     = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
57 12 zero_gravi
  CSR_MISA        = 0x301, /**< 0x301 - misa    (r/-): CPU ISA and extensions (read-only in NEORV32) */
58 6 zero_gravi
  CSR_MIE         = 0x304, /**< 0x304 - mie     (r/w): Machine interrupt-enable register */
59
  CSR_MTVEC       = 0x305, /**< 0x305 - mtvec   (r/w): Machine trap-handler base address (for ALL traps) */
60 2 zero_gravi
 
61
  CSR_MSCRATCH    = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
62
  CSR_MEPC        = 0x341, /**< 0x341 - mepc     (r/w): Machine exception program counter */
63 14 zero_gravi
  CSR_MCAUSE      = 0x342, /**< 0x342 - mcause   (r/-): Machine trap cause */
64 12 zero_gravi
  CSR_MTVAL       = 0x343, /**< 0x343 - mtval    (r/w): Machine bad address or instruction */
65 2 zero_gravi
  CSR_MIP         = 0x344, /**< 0x344 - mip      (r/w): Machine interrupt pending register */
66
 
67 15 zero_gravi
  CSR_PMPCFG0     = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
68
  CSR_PMPCFG1     = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
69
 
70
  CSR_PMPADDR0    = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */
71
  CSR_PMPADDR1    = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */
72
  CSR_PMPADDR2    = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */
73
  CSR_PMPADDR3    = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */
74
  CSR_PMPADDR4    = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */
75
  CSR_PMPADDR5    = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */
76
  CSR_PMPADDR6    = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
77
  CSR_PMPADDR7    = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
78
 
79 11 zero_gravi
  CSR_MCYCLE      = 0xb00, /**< 0xb00 - mcycle    (r/w): Machine cycle counter low word */
80
  CSR_MINSTRET    = 0xb02, /**< 0xb02 - minstret  (r/w): Machine instructions-retired counter low word */
81 18 zero_gravi
 
82 12 zero_gravi
  CSR_MCYCLEH     = 0xb80, /**< 0xb80 - mcycleh   (r/w): Machine cycle counter high word - only 20-bit wide!*/
83
  CSR_MINSTRETH   = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word - only 20-bit wide! */
84 2 zero_gravi
 
85 12 zero_gravi
  CSR_CYCLE       = 0xc00, /**< 0xc00 - cycle    (r/-): Cycle counter low word (from MCYCLE) */
86
  CSR_TIME        = 0xc01, /**< 0xc01 - time     (r/-): Timer low word (from MTIME.TIME_LO) */
87
  CSR_INSTRET     = 0xc02, /**< 0xc02 - instret  (r/-): Instructions-retired counter low word (from MINSTRET) */
88 2 zero_gravi
 
89 12 zero_gravi
  CSR_CYCLEH      = 0xc80, /**< 0xc80 - cycleh   (r/-): Cycle counter high word (from MCYCLEH) - only 20-bit wide! */
90
  CSR_TIMEH       = 0xc81, /**< 0xc81 - timeh    (r/-): Timer high word (from MTIME.TIME_HI) */
91
  CSR_INSTRETH    = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) - only 20-bit wide! */
92 2 zero_gravi
 
93 12 zero_gravi
  CSR_MVENDORID   = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
94
  CSR_MARCHID     = 0xf12, /**< 0xf12 - marchid   (r/-): Architecture ID */
95
  CSR_MIMPID      = 0xf13, /**< 0xf13 - mimpid    (r/-): Implementation ID/version */
96 22 zero_gravi
  CSR_MHARTID     = 0xf14, /**< 0xf14 - mhartid   (r/-): Hardware thread ID (always 0) */
97
 
98
  CSR_MZEXT       = 0xfc0  /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
99 2 zero_gravi
};
100
 
101
 
102
/**********************************************************************//**
103
 * CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
104
 **************************************************************************/
105
enum NEORV32_CPU_MSTATUS_enum {
106 15 zero_gravi
  CPU_MSTATUS_MIE   =  3, /**< CPU mstatus CSR (3): Machine interrupt enable bit (r/w) */
107
  CPU_MSTATUS_MPIE  =  7, /**< CPU mstatus CSR (7): Machine previous interrupt enable bit (r/w) */
108
  CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): Machine previous privilege mode bit low (r/w) */
109
  CPU_MSTATUS_MPP_H = 12  /**< CPU mstatus CSR (12): Machine previous privilege mode bit high (r/w) */
110 2 zero_gravi
};
111
 
112
 
113
/**********************************************************************//**
114
 * CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
115
 **************************************************************************/
116
enum NEORV32_CPU_MIE_enum {
117 14 zero_gravi
  CPU_MIE_MSIE   =  3, /**< CPU mie CSR (3): Machine software interrupt enable (r/w) */
118
  CPU_MIE_MTIE   =  7, /**< CPU mie CSR (7): Machine timer interrupt enable bit (r/w) */
119
  CPU_MIE_MEIE   = 11, /**< CPU mie CSR (11): Machine external interrupt enable bit (r/w) */
120
  CPU_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): Fast interrupt channel 0 enable bit (r/w) */
121
  CPU_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): Fast interrupt channel 1 enable bit (r/w) */
122
  CPU_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): Fast interrupt channel 2 enable bit (r/w) */
123
  CPU_MIE_FIRQ3E = 19  /**< CPU mie CSR (19): Fast interrupt channel 3 enable bit (r/w) */
124 2 zero_gravi
};
125
 
126
 
127
/**********************************************************************//**
128 12 zero_gravi
 * CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.)
129 2 zero_gravi
 **************************************************************************/
130
enum NEORV32_CPU_MIP_enum {
131 14 zero_gravi
  CPU_MIP_MSIP   =  3, /**< CPU mip CSR (3): Machine software interrupt pending (r/-) */
132
  CPU_MIP_MTIP   =  7, /**< CPU mip CSR (7): Machine timer interrupt pending (r/-) */
133
  CPU_MIP_MEIP   = 11, /**< CPU mip CSR (11): Machine external interrupt pending (r/-) */
134
 
135
  CPU_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): Fast interrupt channel 0 pending (r/-) */
136
  CPU_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): Fast interrupt channel 1 pending (r/-) */
137
  CPU_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): Fast interrupt channel 2 pending (r/-) */
138
  CPU_MIP_FIRQ3P = 19  /**< CPU mip CSR (19): Fast interrupt channel 3 pending (r/-) */
139 2 zero_gravi
};
140
 
141
 
142
/**********************************************************************//**
143 16 zero_gravi
 * CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
144 6 zero_gravi
 **************************************************************************/
145
enum NEORV32_CPU_MISA_enum {
146 15 zero_gravi
  CPU_MISA_C_EXT      =  2, /**< CPU misa CSR  (2): C: Compressed instructions CPU extension available (r/-)*/
147 6 zero_gravi
  CPU_MISA_E_EXT      =  4, /**< CPU misa CSR  (3): E: Embedded CPU extension available (r/-) */
148
  CPU_MISA_I_EXT      =  8, /**< CPU misa CSR  (8): I: Base integer ISA CPU extension available (r/-) */
149 15 zero_gravi
  CPU_MISA_M_EXT      = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
150
  CPU_MISA_U_EXT      = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
151 6 zero_gravi
  CPU_MISA_X_EXT      = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
152
  CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
153
  CPU_MISA_MXL_HI_EXT = 31  /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
154
};
155
 
156
 
157
/**********************************************************************//**
158 14 zero_gravi
 * Trap codes from mcause CSR.
159 2 zero_gravi
 **************************************************************************/
160 12 zero_gravi
enum NEORV32_EXCEPTION_CODES_enum {
161 14 zero_gravi
  TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
162
  TRAP_CODE_I_ACCESS     = 0x00000001, /**< 0.1: Instruction (bus) access fault */
163
  TRAP_CODE_I_ILLEGAL    = 0x00000002, /**< 0.2: Illegal instruction */
164
  TRAP_CODE_BREAKPOINT   = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */
165
  TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */
166
  TRAP_CODE_L_ACCESS     = 0x00000005, /**< 0.5: Load (bus) access fault */
167
  TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
168
  TRAP_CODE_S_ACCESS     = 0x00000007, /**< 0.7: Store (bus) access fault */
169
  TRAP_CODE_MENV_CALL    = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
170
  TRAP_CODE_MSI          = 0x80000003, /**< 1.3: Machine software interrupt */
171
  TRAP_CODE_MTI          = 0x80000007, /**< 1.7: Machine timer interrupt */
172
  TRAP_CODE_MEI          = 0x8000000b, /**< 1.11: Machine external interrupt */
173
  TRAP_CODE_FIRQ_0       = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
174
  TRAP_CODE_FIRQ_1       = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
175
  TRAP_CODE_FIRQ_2       = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
176
  TRAP_CODE_FIRQ_3       = 0x80000013  /**< 1.19: Fast interrupt channel 3 */
177 12 zero_gravi
};
178
 
179
 
180
/**********************************************************************//**
181 2 zero_gravi
 * Processor clock prescalers
182
 **************************************************************************/
183
enum NEORV32_CLOCK_PRSC_enum {
184
  CLK_PRSC_2    =  0, /**< CPU_CLK / 2 */
185
  CLK_PRSC_4    =  1, /**< CPU_CLK / 4 */
186
  CLK_PRSC_8    =  2, /**< CPU_CLK / 8 */
187
  CLK_PRSC_64   =  3, /**< CPU_CLK / 64 */
188
  CLK_PRSC_128  =  4, /**< CPU_CLK / 128 */
189
  CLK_PRSC_1024 =  5, /**< CPU_CLK / 1024 */
190
  CLK_PRSC_2048 =  6, /**< CPU_CLK / 2048 */
191
  CLK_PRSC_4096 =  7  /**< CPU_CLK / 4096 */
192
};
193
 
194
 
195
/**********************************************************************//**
196
 * @name Helper macros for easy memory-mapped register access
197
 **************************************************************************/
198
/**@{*/
199
/** memory-mapped byte (8-bit) read/write register */
200
#define IO_REG8  (volatile uint8_t*)
201
/** memory-mapped half-word (16-bit) read/write register */
202
#define IO_REG16 (volatile uint16_t*)
203
/** memory-mapped word (32-bit) read/write register */
204
#define IO_REG32 (volatile uint32_t*)
205
/** memory-mapped double-word (64-bit) read/write register */
206
#define IO_REG64 (volatile uint64_t*)
207
/** memory-mapped byte (8-bit) read-only register */
208
#define IO_ROM8  (const volatile uint8_t*) 
209
/** memory-mapped half-word (16-bit) read-only register */
210
#define IO_ROM16 (const volatile uint16_t*)
211
/** memory-mapped word (32-bit) read-only register */
212
#define IO_ROM32 (const volatile uint32_t*)
213
/** memory-mapped double-word (64-bit) read-only register */
214
#define IO_ROM64 (const volatile uint64_t*)
215
/**@}*/
216
 
217
 
218
/**********************************************************************//**
219
 * @name Address space sections
220
 **************************************************************************/
221
/**@{*/
222
/** instruction memory base address (r/w/x) */
223 23 zero_gravi
// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
224 2 zero_gravi
/** data memory base address (r/w/x) */
225 23 zero_gravi
// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
226 2 zero_gravi
/** bootloader memory base address (r/-/x) */
227 6 zero_gravi
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
228 2 zero_gravi
/** peripheral/IO devices memory base address (r/w/x) */
229 6 zero_gravi
#define IO_BASE_ADDRESS (0xFFFFFF80UL)
230 2 zero_gravi
/**@}*/
231
 
232
 
233
/**********************************************************************//**
234
 * @name IO Device: General Purpose Input/Output Port Unit (GPIO)
235
 **************************************************************************/
236
/**@{*/
237 23 zero_gravi
/** read access: GPIO parallel input port 32-bit (r/-), write_access: pin-change IRQ for each input pin (-/w) */
238
#define GPIO_INPUT  (*(IO_REG32 0xFFFFFF80UL))
239 22 zero_gravi
/** GPIO parallel output port 32-bit (r/w) */
240 6 zero_gravi
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
241 2 zero_gravi
/**@}*/
242
 
243
 
244
/**********************************************************************//**
245 18 zero_gravi
 * @name IO Device: Dummy Device (DEVNULL)
246
 **************************************************************************/
247
/**@{*/
248
/** DEVNULL data register (r/w) */
249
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFF88UL))
250
/**@}*/
251
 
252
 
253
/**********************************************************************//**
254 2 zero_gravi
 * @name IO Device: Watchdog Timer (WDT)
255
 **************************************************************************/
256
/**@{*/
257
/** Watchdog control register (r/w) */
258 6 zero_gravi
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
259 2 zero_gravi
 
260
/** WTD control register bits */
261
enum NEORV32_WDT_CT_enum {
262
  WDT_CT_CLK_SEL0     =  0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
263
  WDT_CT_CLK_SEL1     =  1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
264
  WDT_CT_CLK_SEL2     =  2, /**< WDT control register(2) (r/w): Clock prescaler select bit 2 */
265
  WDT_CT_EN           =  3, /**< WDT control register(3) (r/w): Watchdog enable */
266
  WDT_CT_MODE         =  4, /**< WDT control register(4) (r/w): Watchdog mode; when 0: timeout causes interrupt; when 1: timeout causes processor reset */
267
  WDT_CT_CAUSE        =  5, /**< WDT control register(5) (r/-): Last action (reset/IRQ) cause (0: external reset, 1: watchdog timeout) */
268
  WDT_CT_PWFAIL       =  6, /**< WDT control register(6) (r/-): Last Watchdog action (reset/IRQ) caused by wrong password when 1 */
269
 
270
  WDT_CT_PASSWORD_LSB =  8, /**< WDT control register(8)  (-/w): First bit / position begin for watchdog access password */
271
  WDT_CT_PASSWORD_MSB = 15  /**< WDT control register(15) (-/w): Last bit / position end for watchdog access password */
272
};
273
 
274
/** Watchdog access passwort, must be set in WDT_CT bits 15:8 for every control register access */
275
#define WDT_PASSWORD 0x47
276
/**@}*/
277
 
278
 
279
/**********************************************************************//**
280
 * @name IO Device: Machine System Timer (MTIME)
281
 **************************************************************************/
282
/**@{*/
283 11 zero_gravi
/** MTIME (time register) low word (r/w) */
284
#define MTIME_LO     (*(IO_REG32 0xFFFFFF90UL))
285
/** MTIME (time register) high word (r/w) */
286
#define MTIME_HI     (*(IO_REG32 0xFFFFFF94UL))
287 2 zero_gravi
/** MTIMECMP (time compare register) low word (r/w) */
288 6 zero_gravi
#define MTIMECMP_LO  (*(IO_REG32 0xFFFFFF98UL))
289 2 zero_gravi
/** MTIMECMP (time register) high word (r/w) */
290 6 zero_gravi
#define MTIMECMP_HI  (*(IO_REG32 0xFFFFFF9CUL))
291 2 zero_gravi
 
292 11 zero_gravi
/** MTIME (time register) 64-bit access (r/w) */
293
#define MTIME        (*(IO_REG64 (&MTIME_LO)))
294 2 zero_gravi
/** MTIMECMP (time compare register) low word (r/w) */
295
#define MTIMECMP     (*(IO_REG64 (&MTIMECMP_LO)))
296
/**@}*/
297
 
298
 
299
/**********************************************************************//**
300
 * @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
301
 **************************************************************************/
302
/**@{*/
303
/** UART control register (r/w) */
304 6 zero_gravi
#define UART_CT  (*(IO_REG32 0xFFFFFFA0UL))
305 2 zero_gravi
/** UART receive/transmit data register (r/w) */
306 6 zero_gravi
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
307 2 zero_gravi
 
308
/** UART control register bits */
309
enum NEORV32_UART_CT_enum {
310
  UART_CT_BAUD00  =  0, /**< UART control register(0)  (r/w): BAUD rate config value lsb (12-bi, bit 0) */
311
  UART_CT_BAUD01  =  1, /**< UART control register(1)  (r/w): BAUD rate config value (12-bi, bit 1) */
312
  UART_CT_BAUD02  =  2, /**< UART control register(2)  (r/w): BAUD rate config value (12-bi, bit 2) */
313
  UART_CT_BAUD03  =  3, /**< UART control register(3)  (r/w): BAUD rate config value (12-bi, bit 3) */
314
  UART_CT_BAUD04  =  4, /**< UART control register(4)  (r/w): BAUD rate config value (12-bi, bit 4) */
315
  UART_CT_BAUD05  =  5, /**< UART control register(5)  (r/w): BAUD rate config value (12-bi, bit 4) */
316
  UART_CT_BAUD06  =  6, /**< UART control register(6)  (r/w): BAUD rate config value (12-bi, bit 5) */
317
  UART_CT_BAUD07  =  7, /**< UART control register(7)  (r/w): BAUD rate config value (12-bi, bit 6) */
318
  UART_CT_BAUD08  =  8, /**< UART control register(8)  (r/w): BAUD rate config value (12-bi, bit 7) */
319
  UART_CT_BAUD09  =  9, /**< UART control register(9)  (r/w): BAUD rate config value (12-bi, bit 8) */
320
  UART_CT_BAUD10  = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
321
  UART_CT_BAUD11  = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0)*/
322
 
323
  UART_CT_PRSC0   = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
324
  UART_CT_PRSC1   = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
325
  UART_CT_PRSC2   = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
326
  UART_CT_RXOR    = 27, /**< UART control register(27) (r/-): RX data overrun when set */
327
  UART_CT_EN      = 28, /**< UART control register(28) (r/w): UART global enable */
328
  UART_CT_RX_IRQ  = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
329
  UART_CT_TX_IRQ  = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
330
  UART_CT_TX_BUSY = 31  /**< UART control register(31) (r/-): Transmitter is busy when set */
331
};
332
 
333
/** UART receive/transmit data register bits */
334
enum NEORV32_UART_DATA_enum {
335
  UART_DATA_LSB   =  0, /**< UART receive/transmit data register(0)  (r/w): Receive/transmit data LSB (bit 0) */
336
  UART_DATA_MSB   =  7, /**< UART receive/transmit data register(7)  (r/w): Receive/transmit data MSB (bit 7) */
337
  UART_DATA_AVAIL = 31  /**< UART receive/transmit data register(31) (r/-): RX data available when set */
338
};
339
/**@}*/
340
 
341
 
342
/**********************************************************************//**
343 10 zero_gravi
 * @name IO Device: Serial Peripheral Interface Controller (SPI)
344 2 zero_gravi
 **************************************************************************/
345
/**@{*/
346
/** SPI control register (r/w) */
347 6 zero_gravi
#define SPI_CT  (*(IO_REG32 0xFFFFFFA8UL))
348 2 zero_gravi
/** SPI receive/transmit data register (r/w) */
349 6 zero_gravi
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
350 2 zero_gravi
 
351
/** SPI control register bits */
352
enum NEORV32_SPI_CT_enum {
353
  SPI_CT_CS0    =  0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
354
  SPI_CT_CS1    =  1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
355
  SPI_CT_CS2    =  2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */
356
  SPI_CT_CS3    =  3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
357
  SPI_CT_CS4    =  4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
358
  SPI_CT_CS5    =  5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
359
  SPI_CT_CS6    =  6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
360
  SPI_CT_CS7    =  7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
361
 
362
  SPI_CT_EN     =  8, /**< UART control register(8) (r/w): SPI unit enable */
363
  SPI_CT_CPHA   =  9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
364
  SPI_CT_PRSC0  = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
365
  SPI_CT_PRSC1  = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
366
  SPI_CT_PRSC2  = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
367
  SPI_CT_DIR    = 13, /**< UART control register(13) (r/w): Shift direction (0: MSB first, 1: LSB first) */
368
  SPI_CT_SIZE0  = 14, /**< UART control register(14) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
369
  SPI_CT_SIZE1  = 15, /**< UART control register(15) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
370
 
371
  SPI_CT_IRQ_EN = 16, /**< UART control register(16) (r/w): Transfer done interrupt enable */
372
 
373
  SPI_CT_BUSY   = 31  /**< UART control register(31) (r/-): SPI busy flag */
374
};
375
/**@}*/
376
 
377
 
378
/**********************************************************************//**
379 10 zero_gravi
 * @name IO Device: Two-Wire Interface Controller (TWI)
380 2 zero_gravi
 **************************************************************************/
381
/**@{*/
382
/** TWI control register (r/w) */
383 6 zero_gravi
#define TWI_CT   (*(IO_REG32 0xFFFFFFB0UL))
384 2 zero_gravi
/** TWI receive/transmit data register (r/w) */
385 6 zero_gravi
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
386 2 zero_gravi
 
387
/** TWI control register bits */
388
enum NEORV32_TWI_CT_enum {
389
  TWI_CT_EN     =  0, /**< TWI control register(0) (r/w): TWI enable */
390
  TWI_CT_START  =  1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
391
  TWI_CT_STOP   =  2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
392
  TWI_CT_IRQ_EN =  3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
393
  TWI_CT_PRSC0  =  4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
394
  TWI_CT_PRSC1  =  5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
395
  TWI_CT_PRSC2  =  6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
396 10 zero_gravi
  TWI_CT_MACK   =  7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
397 2 zero_gravi
 
398
  TWI_CT_ACK    = 30, /**< TWI control register(30) (r/-): ACK received when set */
399
  TWI_CT_BUSY   = 31  /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
400
};
401
 
402
/** WTD receive/transmit data register bits */
403
enum NEORV32_TWI_DATA_enum {
404
  TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
405
  TWI_DATA_MSB = 7  /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
406
};
407
/**@}*/
408
 
409
 
410
/**********************************************************************//**
411
 * @name IO Device: Pulse Width Modulation Controller (PWM)
412
 **************************************************************************/
413
/**@{*/
414
/** PWM control register (r/w) */
415 6 zero_gravi
#define PWM_CT   (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
416 2 zero_gravi
/** PWM duty cycle register (4-channels) (r/w) */
417 6 zero_gravi
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
418 2 zero_gravi
 
419
/** PWM control register bits */
420
enum NEORV32_PWM_CT_enum {
421
  PWM_CT_EN    =  0, /**< PWM control register(0) (r/w): PWM controller enable */
422
  PWM_CT_PRSC0 =  1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
423
  PWM_CT_PRSC1 =  2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
424
  PWM_CT_PRSC2 =  3  /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
425
};
426
 
427
/**PWM duty cycle register bits */
428
enum NEORV32_PWM_DUTY_enum {
429
  PWM_DUTY_CH0_LSB =  0, /**< PWM duty cycle register(0)  (r/w): Channel 0 duty cycle (8-bit) LSB */
430
  PWM_DUTY_CH0_MSB =  7, /**< PWM duty cycle register(7)  (r/w): Channel 0 duty cycle (8-bit) MSB */
431
  PWM_DUTY_CH1_LSB =  8, /**< PWM duty cycle register(8)  (r/w): Channel 1 duty cycle (8-bit) LSB */
432
  PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
433
  PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
434
  PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
435
  PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
436
  PWM_DUTY_CH3_MSB = 31  /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
437
};
438
/**@}*/
439
 
440
 
441
/**********************************************************************//**
442
 * @name IO Device: True Random Number Generator (TRNG)
443
 **************************************************************************/
444
/**@{*/
445 23 zero_gravi
/** TRNG control/data register (r/w) */
446 6 zero_gravi
#define TRNG_CT   (*(IO_REG32 0xFFFFFFC0UL))
447 2 zero_gravi
 
448 23 zero_gravi
/** TRNG control/data register bits */
449 2 zero_gravi
enum NEORV32_TRNG_CT_enum {
450 23 zero_gravi
  TRNG_CT_DATA_LSB =  0, /**< TRNG data/control register(0)  (r/-): Random data (8-bit) LSB */
451
  TRNG_CT_DATA_MSB =  7, /**< TRNG data/control register(7)  (r/-): Random data (8-bit) MSB */
452
  TRNG_CT_VALID    = 15, /**< TRNG data/control register(15) (r/-): Random data output valid */
453
  TRNG_CT_ERROR_0  = 16, /**< TRNG data/control register(16) (r/-): Stuck-at-zero error */
454
  TRNG_CT_ERROR_1  = 17, /**< TRNG data/control register(17) (r/-): Stuck-at-one error */
455
  TRNG_CT_EN       = 31  /**< TRNG data/control register(31) (r/w): TRNG enable */
456 2 zero_gravi
};
457 23 zero_gravi
/**@}*/
458
/**@}*/
459 2 zero_gravi
 
460 23 zero_gravi
 
461
/**********************************************************************//**
462
 * @name IO Device: Custom Functions Unit (CFU)
463
 **************************************************************************/
464
/**@{*/
465
/** CFU register 0 ((r)/(w)) */
466
#define CFU_REG_0 (*(IO_REG32 0xFFFFFFD0UL)) // (r)/(w): CFU register 0, user-defined
467
/** CFU register 1 ((r)/(w)) */
468
#define CFU_REG_1 (*(IO_REG32 0xFFFFFFD4UL)) // (r)/(w): CFU register 1, user-defined
469
/** CFU register 2 ((r)/(w)) */
470
#define CFU_REG_2 (*(IO_REG32 0xFFFFFFD8UL)) // (r)/(w): CFU register 2, user-defined
471
/** CFU register 3 ((r)/(w)) */
472
#define CFU_REG_3 (*(IO_REG32 0xFFFFFFDCUL)) // (r)/(w): CFU register 3, user-defined
473 2 zero_gravi
/**@}*/
474
 
475
 
476 3 zero_gravi
/**********************************************************************//**
477 12 zero_gravi
 * @name IO Device: System Configuration Info Memory (SYSINFO)
478
 **************************************************************************/
479
/**@{*/
480
/** SYSINFO(0): Clock speed */
481
#define SYSINFO_CLK         (*(IO_ROM32 0xFFFFFFE0UL))
482
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
483
#define SYSINFO_USER_CODE   (*(IO_ROM32 0xFFFFFFE4UL))
484
/** SYSINFO(2): Clock speed */
485
#define SYSINFO_FEATURES    (*(IO_ROM32 0xFFFFFFE8UL))
486
/** SYSINFO(3): reserved */
487 23 zero_gravi
#define SYSINFO_reserved    (*(IO_ROM32 0xFFFFFFECUL))
488 12 zero_gravi
/** SYSINFO(4): Instruction memory address space base */
489
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
490
/** SYSINFO(5): Data memory address space base */
491
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
492 23 zero_gravi
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
493
#define SYSINFO_IMEM_SIZE   (*(IO_ROM32 0xFFFFFFF8UL))
494
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
495
#define SYSINFO_DMEM_SIZE   (*(IO_ROM32 0xFFFFFFFCUL))
496 12 zero_gravi
/**@}*/
497
 
498
 
499
/**********************************************************************//**
500
 * SYSINFO_FEATURES (r/-): Implemented processor devices/features
501
 **************************************************************************/
502
 enum NEORV32_SYSINFO_FEATURES_enum {
503
  SYSINFO_FEATURES_BOOTLOADER       =  0, /**< SYSINFO_FEATURES  (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
504
  SYSINFO_FEATURES_MEM_EXT          =  1, /**< SYSINFO_FEATURES  (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
505
  SYSINFO_FEATURES_MEM_INT_IMEM     =  2, /**< SYSINFO_FEATURES  (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
506
  SYSINFO_FEATURES_MEM_INT_IMEM_ROM =  3, /**< SYSINFO_FEATURES  (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
507
  SYSINFO_FEATURES_MEM_INT_DMEM     =  4, /**< SYSINFO_FEATURES  (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
508
 
509
  SYSINFO_FEATURES_IO_GPIO          = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
510
  SYSINFO_FEATURES_IO_MTIME         = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
511
  SYSINFO_FEATURES_IO_UART          = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
512
  SYSINFO_FEATURES_IO_SPI           = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
513
  SYSINFO_FEATURES_IO_TWI           = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
514
  SYSINFO_FEATURES_IO_PWM           = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
515
  SYSINFO_FEATURES_IO_WDT           = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
516 23 zero_gravi
  SYSINFO_FEATURES_IO_CFU           = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit implemented when 1 (via IO_CFU_USE generic) */
517 12 zero_gravi
  SYSINFO_FEATURES_IO_TRNG          = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
518 23 zero_gravi
  SYSINFO_FEATURES_IO_DEVNULL       = 25  /**< SYSINFO_FEATURES (25) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */
519 12 zero_gravi
};
520
 
521
 
522 2 zero_gravi
// ----------------------------------------------------------------------------
523
// Include all IO driver headers
524
// ----------------------------------------------------------------------------
525
// cpu core
526
#include "neorv32_cpu.h"
527
 
528
// neorv32 runtime environment
529
#include "neorv32_rte.h"
530
 
531
// io/peripheral devices
532
#include "neorv32_gpio.h"
533
#include "neorv32_mtime.h"
534
#include "neorv32_pwm.h"
535
#include "neorv32_spi.h"
536
#include "neorv32_trng.h"
537
#include "neorv32_twi.h"
538
#include "neorv32_uart.h"
539
#include "neorv32_wdt.h"
540
 
541
#endif // neorv32_h

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