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// #################################################################################################
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// # << NEORV32: neorv32.h - Main Core Library File >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32.h
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* @author Stephan Nolting
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*
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* @brief Main NEORV32 core library include file.
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**************************************************************************/
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#ifndef neorv32_h
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#define neorv32_h
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// Standard libraries
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#include <stdint.h>
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#include <inttypes.h>
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#include <limits.h>
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/**********************************************************************//**
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* Available CPU Control and Status Registers (CSRs)
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**************************************************************************/
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enum NEORV32_CPU_CSRS_enum {
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CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
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CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
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CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
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CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
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CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
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CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
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CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
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CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
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CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
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CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
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CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
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CSR_PMPADDR0 = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */
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CSR_PMPADDR1 = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */
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CSR_PMPADDR2 = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */
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CSR_PMPADDR3 = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */
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CSR_PMPADDR4 = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */
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CSR_PMPADDR5 = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */
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CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
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CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
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CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
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CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
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CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
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CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
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CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
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CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
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CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
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CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */
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CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
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};
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/**********************************************************************//**
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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**************************************************************************/
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enum NEORV32_CPU_MSTATUS_enum {
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CPU_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): Machine interrupt enable bit (r/w) */
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CPU_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): Machine previous interrupt enable bit (r/w) */
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CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): Machine previous privilege mode bit low (r/w) */
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CPU_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): Machine previous privilege mode bit high (r/w) */
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};
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/**********************************************************************//**
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* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
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**************************************************************************/
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enum NEORV32_CPU_MIE_enum {
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CPU_MIE_MSIE = 3, /**< CPU mie CSR (3): Machine software interrupt enable (r/w) */
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CPU_MIE_MTIE = 7, /**< CPU mie CSR (7): Machine timer interrupt enable bit (r/w) */
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CPU_MIE_MEIE = 11, /**< CPU mie CSR (11): Machine external interrupt enable bit (r/w) */
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CPU_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): Fast interrupt channel 0 enable bit (r/w) */
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CPU_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): Fast interrupt channel 1 enable bit (r/w) */
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CPU_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): Fast interrupt channel 2 enable bit (r/w) */
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CPU_MIE_FIRQ3E = 19 /**< CPU mie CSR (19): Fast interrupt channel 3 enable bit (r/w) */
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};
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/**********************************************************************//**
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* CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.)
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**************************************************************************/
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enum NEORV32_CPU_MIP_enum {
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CPU_MIP_MSIP = 3, /**< CPU mip CSR (3): Machine software interrupt pending (r/-) */
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CPU_MIP_MTIP = 7, /**< CPU mip CSR (7): Machine timer interrupt pending (r/-) */
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CPU_MIP_MEIP = 11, /**< CPU mip CSR (11): Machine external interrupt pending (r/-) */
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CPU_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): Fast interrupt channel 0 pending (r/-) */
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CPU_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): Fast interrupt channel 1 pending (r/-) */
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CPU_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): Fast interrupt channel 2 pending (r/-) */
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CPU_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): Fast interrupt channel 3 pending (r/-) */
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};
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/**********************************************************************//**
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* CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
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**************************************************************************/
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enum NEORV32_CPU_MISA_enum {
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CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
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CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CPU_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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};
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/**********************************************************************//**
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* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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**************************************************************************/
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enum NEORV32_CPU_MZEXT_enum {
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CPU_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
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CPU_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
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CPU_MZEXT_PMP = 2 /**< CPU mzext CSR (2): PMP extension available when set (r/-) */
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};
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/**********************************************************************//**
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* Trap codes from mcause CSR.
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**************************************************************************/
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enum NEORV32_EXCEPTION_CODES_enum {
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TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
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TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
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TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */
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TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */
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TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */
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TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */
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TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
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TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */
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TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
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TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */
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TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */
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TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */
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TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
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TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
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TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
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TRAP_CODE_FIRQ_3 = 0x80000013 /**< 1.19: Fast interrupt channel 3 */
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};
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/**********************************************************************//**
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* Processor clock prescalers
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**************************************************************************/
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enum NEORV32_CLOCK_PRSC_enum {
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CLK_PRSC_2 = 0, /**< CPU_CLK / 2 */
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CLK_PRSC_4 = 1, /**< CPU_CLK / 4 */
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CLK_PRSC_8 = 2, /**< CPU_CLK / 8 */
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CLK_PRSC_64 = 3, /**< CPU_CLK / 64 */
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CLK_PRSC_128 = 4, /**< CPU_CLK / 128 */
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CLK_PRSC_1024 = 5, /**< CPU_CLK / 1024 */
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CLK_PRSC_2048 = 6, /**< CPU_CLK / 2048 */
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CLK_PRSC_4096 = 7 /**< CPU_CLK / 4096 */
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};
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/**********************************************************************//**
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* Official NEORV32 open-source architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
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**************************************************************************/
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#define NEORV32_ARCHID 19
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/**********************************************************************//**
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* @name Helper macros for easy memory-mapped register access
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**************************************************************************/
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/**@{*/
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/** memory-mapped byte (8-bit) read/write register */
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#define IO_REG8 (volatile uint8_t*)
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/** memory-mapped half-word (16-bit) read/write register */
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#define IO_REG16 (volatile uint16_t*)
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/** memory-mapped word (32-bit) read/write register */
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#define IO_REG32 (volatile uint32_t*)
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/** memory-mapped double-word (64-bit) read/write register */
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#define IO_REG64 (volatile uint64_t*)
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/** memory-mapped byte (8-bit) read-only register */
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#define IO_ROM8 (const volatile uint8_t*)
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/** memory-mapped half-word (16-bit) read-only register */
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#define IO_ROM16 (const volatile uint16_t*)
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/** memory-mapped word (32-bit) read-only register */
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#define IO_ROM32 (const volatile uint32_t*)
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/** memory-mapped double-word (64-bit) read-only register */
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#define IO_ROM64 (const volatile uint64_t*)
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/**@}*/
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/**********************************************************************//**
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* @name Address space sections
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**************************************************************************/
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/**@{*/
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/** instruction memory base address (r/w/x) */
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zero_gravi |
// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
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zero_gravi |
/** data memory base address (r/w/x) */
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zero_gravi |
// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
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2 |
zero_gravi |
/** bootloader memory base address (r/-/x) */
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zero_gravi |
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
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zero_gravi |
/** peripheral/IO devices memory base address (r/w/x) */
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zero_gravi |
#define IO_BASE_ADDRESS (0xFFFFFF80UL)
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/**@}*/
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/**********************************************************************//**
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* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
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| 251 |
|
|
**************************************************************************/
|
| 252 |
|
|
/**@{*/
|
| 253 |
23 |
zero_gravi |
/** read access: GPIO parallel input port 32-bit (r/-), write_access: pin-change IRQ for each input pin (-/w) */
|
| 254 |
|
|
#define GPIO_INPUT (*(IO_REG32 0xFFFFFF80UL))
|
| 255 |
22 |
zero_gravi |
/** GPIO parallel output port 32-bit (r/w) */
|
| 256 |
6 |
zero_gravi |
#define GPIO_OUTPUT (*(IO_REG32 0xFFFFFF84UL))
|
| 257 |
2 |
zero_gravi |
/**@}*/
|
| 258 |
|
|
|
| 259 |
|
|
|
| 260 |
|
|
/**********************************************************************//**
|
| 261 |
30 |
zero_gravi |
* @name IO Device: True Random Number Generator (TRNG)
|
| 262 |
18 |
zero_gravi |
**************************************************************************/
|
| 263 |
|
|
/**@{*/
|
| 264 |
30 |
zero_gravi |
/** TRNG control/data register (r/w) */
|
| 265 |
|
|
#define TRNG_CT (*(IO_REG32 0xFFFFFF88UL))
|
| 266 |
|
|
|
| 267 |
|
|
/** TRNG control/data register bits */
|
| 268 |
|
|
enum NEORV32_TRNG_CT_enum {
|
| 269 |
|
|
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data (8-bit) LSB */
|
| 270 |
|
|
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data (8-bit) MSB */
|
| 271 |
|
|
TRNG_CT_VALID = 15, /**< TRNG data/control register(15) (r/-): Random data output valid */
|
| 272 |
|
|
TRNG_CT_ERROR_0 = 16, /**< TRNG data/control register(16) (r/-): Stuck-at-zero error */
|
| 273 |
|
|
TRNG_CT_ERROR_1 = 17, /**< TRNG data/control register(17) (r/-): Stuck-at-one error */
|
| 274 |
|
|
TRNG_CT_EN = 31 /**< TRNG data/control register(31) (r/w): TRNG enable */
|
| 275 |
|
|
};
|
| 276 |
18 |
zero_gravi |
/**@}*/
|
| 277 |
30 |
zero_gravi |
/**@}*/
|
| 278 |
18 |
zero_gravi |
|
| 279 |
|
|
|
| 280 |
|
|
/**********************************************************************//**
|
| 281 |
2 |
zero_gravi |
* @name IO Device: Watchdog Timer (WDT)
|
| 282 |
|
|
**************************************************************************/
|
| 283 |
|
|
/**@{*/
|
| 284 |
|
|
/** Watchdog control register (r/w) */
|
| 285 |
6 |
zero_gravi |
#define WDT_CT (*(IO_REG32 0xFFFFFF8CUL))
|
| 286 |
2 |
zero_gravi |
|
| 287 |
|
|
/** WTD control register bits */
|
| 288 |
|
|
enum NEORV32_WDT_CT_enum {
|
| 289 |
|
|
WDT_CT_CLK_SEL0 = 0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */
|
| 290 |
|
|
WDT_CT_CLK_SEL1 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */
|
| 291 |
|
|
WDT_CT_CLK_SEL2 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 2 */
|
| 292 |
|
|
WDT_CT_EN = 3, /**< WDT control register(3) (r/w): Watchdog enable */
|
| 293 |
|
|
WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode; when 0: timeout causes interrupt; when 1: timeout causes processor reset */
|
| 294 |
|
|
WDT_CT_CAUSE = 5, /**< WDT control register(5) (r/-): Last action (reset/IRQ) cause (0: external reset, 1: watchdog timeout) */
|
| 295 |
|
|
WDT_CT_PWFAIL = 6, /**< WDT control register(6) (r/-): Last Watchdog action (reset/IRQ) caused by wrong password when 1 */
|
| 296 |
|
|
|
| 297 |
|
|
WDT_CT_PASSWORD_LSB = 8, /**< WDT control register(8) (-/w): First bit / position begin for watchdog access password */
|
| 298 |
|
|
WDT_CT_PASSWORD_MSB = 15 /**< WDT control register(15) (-/w): Last bit / position end for watchdog access password */
|
| 299 |
|
|
};
|
| 300 |
|
|
|
| 301 |
|
|
/** Watchdog access passwort, must be set in WDT_CT bits 15:8 for every control register access */
|
| 302 |
|
|
#define WDT_PASSWORD 0x47
|
| 303 |
|
|
/**@}*/
|
| 304 |
|
|
|
| 305 |
|
|
|
| 306 |
|
|
/**********************************************************************//**
|
| 307 |
|
|
* @name IO Device: Machine System Timer (MTIME)
|
| 308 |
|
|
**************************************************************************/
|
| 309 |
|
|
/**@{*/
|
| 310 |
11 |
zero_gravi |
/** MTIME (time register) low word (r/w) */
|
| 311 |
|
|
#define MTIME_LO (*(IO_REG32 0xFFFFFF90UL))
|
| 312 |
|
|
/** MTIME (time register) high word (r/w) */
|
| 313 |
|
|
#define MTIME_HI (*(IO_REG32 0xFFFFFF94UL))
|
| 314 |
2 |
zero_gravi |
/** MTIMECMP (time compare register) low word (r/w) */
|
| 315 |
6 |
zero_gravi |
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
|
| 316 |
2 |
zero_gravi |
/** MTIMECMP (time register) high word (r/w) */
|
| 317 |
6 |
zero_gravi |
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
|
| 318 |
2 |
zero_gravi |
|
| 319 |
11 |
zero_gravi |
/** MTIME (time register) 64-bit access (r/w) */
|
| 320 |
|
|
#define MTIME (*(IO_REG64 (&MTIME_LO)))
|
| 321 |
2 |
zero_gravi |
/** MTIMECMP (time compare register) low word (r/w) */
|
| 322 |
|
|
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO)))
|
| 323 |
|
|
/**@}*/
|
| 324 |
|
|
|
| 325 |
|
|
|
| 326 |
|
|
/**********************************************************************//**
|
| 327 |
|
|
* @name IO Device: Universal Asynchronous Receiver and Transmitter (UART)
|
| 328 |
|
|
**************************************************************************/
|
| 329 |
|
|
/**@{*/
|
| 330 |
|
|
/** UART control register (r/w) */
|
| 331 |
6 |
zero_gravi |
#define UART_CT (*(IO_REG32 0xFFFFFFA0UL))
|
| 332 |
2 |
zero_gravi |
/** UART receive/transmit data register (r/w) */
|
| 333 |
6 |
zero_gravi |
#define UART_DATA (*(IO_REG32 0xFFFFFFA4UL))
|
| 334 |
2 |
zero_gravi |
|
| 335 |
|
|
/** UART control register bits */
|
| 336 |
|
|
enum NEORV32_UART_CT_enum {
|
| 337 |
30 |
zero_gravi |
UART_CT_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bi, bit 0) */
|
| 338 |
|
|
UART_CT_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bi, bit 1) */
|
| 339 |
|
|
UART_CT_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bi, bit 2) */
|
| 340 |
|
|
UART_CT_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bi, bit 3) */
|
| 341 |
|
|
UART_CT_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bi, bit 4) */
|
| 342 |
|
|
UART_CT_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bi, bit 4) */
|
| 343 |
|
|
UART_CT_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bi, bit 5) */
|
| 344 |
|
|
UART_CT_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bi, bit 6) */
|
| 345 |
|
|
UART_CT_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bi, bit 7) */
|
| 346 |
|
|
UART_CT_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bi, bit 8) */
|
| 347 |
|
|
UART_CT_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bi, bit 9) */
|
| 348 |
|
|
UART_CT_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bi, bit 0) */
|
| 349 |
2 |
zero_gravi |
|
| 350 |
30 |
zero_gravi |
UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
|
| 351 |
|
|
|
| 352 |
|
|
UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
|
| 353 |
|
|
UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
|
| 354 |
|
|
UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
|
| 355 |
|
|
UART_CT_RXOR = 27, /**< UART control register(27) (r/-): RX data overrun when set */
|
| 356 |
|
|
UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */
|
| 357 |
|
|
UART_CT_RX_IRQ = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
|
| 358 |
|
|
UART_CT_TX_IRQ = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
|
| 359 |
|
|
UART_CT_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
|
| 360 |
2 |
zero_gravi |
};
|
| 361 |
|
|
|
| 362 |
|
|
/** UART receive/transmit data register bits */
|
| 363 |
|
|
enum NEORV32_UART_DATA_enum {
|
| 364 |
|
|
UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */
|
| 365 |
|
|
UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */
|
| 366 |
|
|
UART_DATA_AVAIL = 31 /**< UART receive/transmit data register(31) (r/-): RX data available when set */
|
| 367 |
|
|
};
|
| 368 |
|
|
/**@}*/
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
/**********************************************************************//**
|
| 372 |
10 |
zero_gravi |
* @name IO Device: Serial Peripheral Interface Controller (SPI)
|
| 373 |
2 |
zero_gravi |
**************************************************************************/
|
| 374 |
|
|
/**@{*/
|
| 375 |
|
|
/** SPI control register (r/w) */
|
| 376 |
6 |
zero_gravi |
#define SPI_CT (*(IO_REG32 0xFFFFFFA8UL))
|
| 377 |
2 |
zero_gravi |
/** SPI receive/transmit data register (r/w) */
|
| 378 |
6 |
zero_gravi |
#define SPI_DATA (*(IO_REG32 0xFFFFFFACUL))
|
| 379 |
2 |
zero_gravi |
|
| 380 |
|
|
/** SPI control register bits */
|
| 381 |
|
|
enum NEORV32_SPI_CT_enum {
|
| 382 |
|
|
SPI_CT_CS0 = 0, /**< UART control register(0) (r/w): Direct chip select line 0 (output is low when set) */
|
| 383 |
|
|
SPI_CT_CS1 = 1, /**< UART control register(1) (r/w): Direct chip select line 1 (output is low when set) */
|
| 384 |
|
|
SPI_CT_CS2 = 2, /**< UART control register(2) (r/w): Direct chip select line 2 (output is low when set) */
|
| 385 |
|
|
SPI_CT_CS3 = 3, /**< UART control register(3) (r/w): Direct chip select line 3 (output is low when set) */
|
| 386 |
|
|
SPI_CT_CS4 = 4, /**< UART control register(4) (r/w): Direct chip select line 4 (output is low when set) */
|
| 387 |
|
|
SPI_CT_CS5 = 5, /**< UART control register(5) (r/w): Direct chip select line 5 (output is low when set) */
|
| 388 |
|
|
SPI_CT_CS6 = 6, /**< UART control register(6) (r/w): Direct chip select line 6 (output is low when set) */
|
| 389 |
|
|
SPI_CT_CS7 = 7, /**< UART control register(7) (r/w): Direct chip select line 7 (output is low when set) */
|
| 390 |
|
|
|
| 391 |
|
|
SPI_CT_EN = 8, /**< UART control register(8) (r/w): SPI unit enable */
|
| 392 |
|
|
SPI_CT_CPHA = 9, /**< UART control register(9) (r/w): Clock polarity (idle polarity) */
|
| 393 |
|
|
SPI_CT_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
|
| 394 |
|
|
SPI_CT_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
|
| 395 |
|
|
SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
|
| 396 |
|
|
SPI_CT_DIR = 13, /**< UART control register(13) (r/w): Shift direction (0: MSB first, 1: LSB first) */
|
| 397 |
|
|
SPI_CT_SIZE0 = 14, /**< UART control register(14) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
|
| 398 |
|
|
SPI_CT_SIZE1 = 15, /**< UART control register(15) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
|
| 399 |
|
|
|
| 400 |
|
|
SPI_CT_IRQ_EN = 16, /**< UART control register(16) (r/w): Transfer done interrupt enable */
|
| 401 |
|
|
|
| 402 |
|
|
SPI_CT_BUSY = 31 /**< UART control register(31) (r/-): SPI busy flag */
|
| 403 |
|
|
};
|
| 404 |
|
|
/**@}*/
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
/**********************************************************************//**
|
| 408 |
10 |
zero_gravi |
* @name IO Device: Two-Wire Interface Controller (TWI)
|
| 409 |
2 |
zero_gravi |
**************************************************************************/
|
| 410 |
|
|
/**@{*/
|
| 411 |
|
|
/** TWI control register (r/w) */
|
| 412 |
6 |
zero_gravi |
#define TWI_CT (*(IO_REG32 0xFFFFFFB0UL))
|
| 413 |
2 |
zero_gravi |
/** TWI receive/transmit data register (r/w) */
|
| 414 |
6 |
zero_gravi |
#define TWI_DATA (*(IO_REG32 0xFFFFFFB4UL))
|
| 415 |
2 |
zero_gravi |
|
| 416 |
|
|
/** TWI control register bits */
|
| 417 |
|
|
enum NEORV32_TWI_CT_enum {
|
| 418 |
|
|
TWI_CT_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
|
| 419 |
|
|
TWI_CT_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
|
| 420 |
|
|
TWI_CT_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
|
| 421 |
|
|
TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
|
| 422 |
|
|
TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
|
| 423 |
|
|
TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
|
| 424 |
|
|
TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
|
| 425 |
10 |
zero_gravi |
TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
|
| 426 |
2 |
zero_gravi |
|
| 427 |
|
|
TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
|
| 428 |
|
|
TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
|
| 429 |
|
|
};
|
| 430 |
|
|
|
| 431 |
|
|
/** WTD receive/transmit data register bits */
|
| 432 |
|
|
enum NEORV32_TWI_DATA_enum {
|
| 433 |
|
|
TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
|
| 434 |
|
|
TWI_DATA_MSB = 7 /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
|
| 435 |
|
|
};
|
| 436 |
|
|
/**@}*/
|
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
/**********************************************************************//**
|
| 440 |
|
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
| 441 |
|
|
**************************************************************************/
|
| 442 |
|
|
/**@{*/
|
| 443 |
|
|
/** PWM control register (r/w) */
|
| 444 |
6 |
zero_gravi |
#define PWM_CT (*(IO_REG32 0xFFFFFFB8UL)) // r/w: control register
|
| 445 |
2 |
zero_gravi |
/** PWM duty cycle register (4-channels) (r/w) */
|
| 446 |
6 |
zero_gravi |
#define PWM_DUTY (*(IO_REG32 0xFFFFFFBCUL)) // r/w: duty cycle channel 1 and 0
|
| 447 |
2 |
zero_gravi |
|
| 448 |
|
|
/** PWM control register bits */
|
| 449 |
|
|
enum NEORV32_PWM_CT_enum {
|
| 450 |
|
|
PWM_CT_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
|
| 451 |
|
|
PWM_CT_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
|
| 452 |
|
|
PWM_CT_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
|
| 453 |
|
|
PWM_CT_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
|
| 454 |
|
|
};
|
| 455 |
|
|
|
| 456 |
|
|
/**PWM duty cycle register bits */
|
| 457 |
|
|
enum NEORV32_PWM_DUTY_enum {
|
| 458 |
|
|
PWM_DUTY_CH0_LSB = 0, /**< PWM duty cycle register(0) (r/w): Channel 0 duty cycle (8-bit) LSB */
|
| 459 |
|
|
PWM_DUTY_CH0_MSB = 7, /**< PWM duty cycle register(7) (r/w): Channel 0 duty cycle (8-bit) MSB */
|
| 460 |
|
|
PWM_DUTY_CH1_LSB = 8, /**< PWM duty cycle register(8) (r/w): Channel 1 duty cycle (8-bit) LSB */
|
| 461 |
|
|
PWM_DUTY_CH1_MSB = 15, /**< PWM duty cycle register(15) (r/w): Channel 1 duty cycle (8-bit) MSB */
|
| 462 |
|
|
PWM_DUTY_CH2_LSB = 16, /**< PWM duty cycle register(16) (r/w): Channel 2 duty cycle (8-bit) LSB */
|
| 463 |
|
|
PWM_DUTY_CH2_MSB = 23, /**< PWM duty cycle register(23) (r/w): Channel 2 duty cycle (8-bit) MSB */
|
| 464 |
|
|
PWM_DUTY_CH3_LSB = 24, /**< PWM duty cycle register(24) (r/w): Channel 3 duty cycle (8-bit) LSB */
|
| 465 |
|
|
PWM_DUTY_CH3_MSB = 31 /**< PWM duty cycle register(31) (r/w): Channel 3 duty cycle (8-bit) MSB */
|
| 466 |
|
|
};
|
| 467 |
|
|
/**@}*/
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
/**********************************************************************//**
|
| 471 |
23 |
zero_gravi |
* @name IO Device: Custom Functions Unit (CFU)
|
| 472 |
|
|
**************************************************************************/
|
| 473 |
|
|
/**@{*/
|
| 474 |
|
|
/** CFU register 0 ((r)/(w)) */
|
| 475 |
|
|
#define CFU_REG_0 (*(IO_REG32 0xFFFFFFD0UL)) // (r)/(w): CFU register 0, user-defined
|
| 476 |
|
|
/** CFU register 1 ((r)/(w)) */
|
| 477 |
|
|
#define CFU_REG_1 (*(IO_REG32 0xFFFFFFD4UL)) // (r)/(w): CFU register 1, user-defined
|
| 478 |
|
|
/** CFU register 2 ((r)/(w)) */
|
| 479 |
|
|
#define CFU_REG_2 (*(IO_REG32 0xFFFFFFD8UL)) // (r)/(w): CFU register 2, user-defined
|
| 480 |
|
|
/** CFU register 3 ((r)/(w)) */
|
| 481 |
|
|
#define CFU_REG_3 (*(IO_REG32 0xFFFFFFDCUL)) // (r)/(w): CFU register 3, user-defined
|
| 482 |
2 |
zero_gravi |
/**@}*/
|
| 483 |
|
|
|
| 484 |
|
|
|
| 485 |
3 |
zero_gravi |
/**********************************************************************//**
|
| 486 |
12 |
zero_gravi |
* @name IO Device: System Configuration Info Memory (SYSINFO)
|
| 487 |
|
|
**************************************************************************/
|
| 488 |
|
|
/**@{*/
|
| 489 |
|
|
/** SYSINFO(0): Clock speed */
|
| 490 |
|
|
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
|
| 491 |
|
|
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
|
| 492 |
|
|
#define SYSINFO_USER_CODE (*(IO_ROM32 0xFFFFFFE4UL))
|
| 493 |
|
|
/** SYSINFO(2): Clock speed */
|
| 494 |
|
|
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL))
|
| 495 |
|
|
/** SYSINFO(3): reserved */
|
| 496 |
23 |
zero_gravi |
#define SYSINFO_reserved (*(IO_ROM32 0xFFFFFFECUL))
|
| 497 |
12 |
zero_gravi |
/** SYSINFO(4): Instruction memory address space base */
|
| 498 |
|
|
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL))
|
| 499 |
|
|
/** SYSINFO(5): Data memory address space base */
|
| 500 |
|
|
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 0xFFFFFFF4UL))
|
| 501 |
23 |
zero_gravi |
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
|
| 502 |
|
|
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 0xFFFFFFF8UL))
|
| 503 |
|
|
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
|
| 504 |
|
|
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 0xFFFFFFFCUL))
|
| 505 |
12 |
zero_gravi |
/**@}*/
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
/**********************************************************************//**
|
| 509 |
|
|
* SYSINFO_FEATURES (r/-): Implemented processor devices/features
|
| 510 |
|
|
**************************************************************************/
|
| 511 |
|
|
enum NEORV32_SYSINFO_FEATURES_enum {
|
| 512 |
|
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via BOOTLOADER_USE generic) */
|
| 513 |
|
|
SYSINFO_FEATURES_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_USE generic) */
|
| 514 |
|
|
SYSINFO_FEATURES_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_USE generic) */
|
| 515 |
|
|
SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */
|
| 516 |
|
|
SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */
|
| 517 |
|
|
|
| 518 |
|
|
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */
|
| 519 |
|
|
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */
|
| 520 |
|
|
SYSINFO_FEATURES_IO_UART = 18, /**< SYSINFO_FEATURES (18) (r/-): Universal asynchronous receiver/transmitter implemented when 1 (via IO_UART_USE generic) */
|
| 521 |
|
|
SYSINFO_FEATURES_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_USE generic) */
|
| 522 |
|
|
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_USE generic) */
|
| 523 |
|
|
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */
|
| 524 |
|
|
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */
|
| 525 |
23 |
zero_gravi |
SYSINFO_FEATURES_IO_CFU = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit implemented when 1 (via IO_CFU_USE generic) */
|
| 526 |
30 |
zero_gravi |
SYSINFO_FEATURES_IO_TRNG = 24 /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */
|
| 527 |
12 |
zero_gravi |
};
|
| 528 |
|
|
|
| 529 |
|
|
|
| 530 |
2 |
zero_gravi |
// ----------------------------------------------------------------------------
|
| 531 |
|
|
// Include all IO driver headers
|
| 532 |
|
|
// ----------------------------------------------------------------------------
|
| 533 |
|
|
// cpu core
|
| 534 |
|
|
#include "neorv32_cpu.h"
|
| 535 |
|
|
|
| 536 |
|
|
// neorv32 runtime environment
|
| 537 |
|
|
#include "neorv32_rte.h"
|
| 538 |
|
|
|
| 539 |
|
|
// io/peripheral devices
|
| 540 |
26 |
zero_gravi |
#include "neorv32_cfu.h"
|
| 541 |
2 |
zero_gravi |
#include "neorv32_gpio.h"
|
| 542 |
|
|
#include "neorv32_mtime.h"
|
| 543 |
|
|
#include "neorv32_pwm.h"
|
| 544 |
|
|
#include "neorv32_spi.h"
|
| 545 |
|
|
#include "neorv32_trng.h"
|
| 546 |
|
|
#include "neorv32_twi.h"
|
| 547 |
|
|
#include "neorv32_uart.h"
|
| 548 |
|
|
#include "neorv32_wdt.h"
|
| 549 |
|
|
|
| 550 |
|
|
#endif // neorv32_h
|
