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1 2 zero_gravi 
// #################################################################################################
2 
// # << NEORV32: neorv32.h - Main Core Library File >>                                             #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License                                                                          #
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// #                                                                                               #
6 42 zero_gravi 
// # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
// #                                                                                               #
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// # Redistribution and use in source and binary forms, with or without modification, are          #
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// # permitted provided that the following conditions are met:                                     #
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// #                                                                                               #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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// #    conditions and the following disclaimer.                                                   #
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// #                                                                                               #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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// #    conditions and the following disclaimer in the documentation and/or other materials        #
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// #    provided with the distribution.                                                            #
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// #                                                                                               #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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// #    endorse or promote products derived from this software without specific prior written      #
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// #    permission.                                                                                #
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// #                                                                                               #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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// #################################################################################################
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35 
 
36 
/**********************************************************************//**
37 
 * @file neorv32.h
38 
 * @author Stephan Nolting
39 
 *
40 20 zero_gravi 
 * @brief Main NEORV32 core library include file.
41 2 zero_gravi 
 **************************************************************************/
42 
 
43 
#ifndef neorv32_h
44 
#define neorv32_h
45 
 
46 61 zero_gravi 
#ifdef __cplusplus
47 
extern "C" {
48 
#endif
49 
 
50 
 
51 2 zero_gravi 
// Standard libraries
52 
#include <stdint.h>
53 
#include <inttypes.h>
54 
#include <limits.h>
55 
 
56 
 
57 
/**********************************************************************//**
58 
 * Available CPU Control and Status Registers (CSRs)
59 
 **************************************************************************/
60 42 zero_gravi 
enum NEORV32_CSR_enum {
61 61 zero_gravi 
  CSR_FFLAGS         = 0x001, /**< 0x001 - fflags (r/w): Floating-point accrued exception flags */
62 
  CSR_FRM            = 0x002, /**< 0x002 - frm    (r/w): Floating-point dynamic rounding mode */
63 
  CSR_FCSR           = 0x003, /**< 0x003 - fcsr   (r/w): Floating-point control/staturs register (frm + fflags) */
64 54 zero_gravi 
 
65 42 zero_gravi 
  CSR_MSTATUS        = 0x300, /**< 0x300 - mstatus    (r/w): Machine status register */
66 
  CSR_MISA           = 0x301, /**< 0x301 - misa       (r/-): CPU ISA and extensions (read-only in NEORV32) */
67 
  CSR_MIE            = 0x304, /**< 0x304 - mie        (r/w): Machine interrupt-enable register */
68 
  CSR_MTVEC          = 0x305, /**< 0x305 - mtvec      (r/w): Machine trap-handler base address (for ALL traps) */
69 
  CSR_MCOUNTEREN     = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
70 2 zero_gravi 
 
71 42 zero_gravi 
  CSR_MCOUNTINHIBIT  = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
72 2 zero_gravi 
 
73 42 zero_gravi 
  CSR_MHPMEVENT3     = 0x323, /**< 0x323 - mhpmevent3  (r/w): Machine hardware performance monitor event selector 3  */
74 
  CSR_MHPMEVENT4     = 0x324, /**< 0x324 - mhpmevent4  (r/w): Machine hardware performance monitor event selector 4  */
75 
  CSR_MHPMEVENT5     = 0x325, /**< 0x325 - mhpmevent5  (r/w): Machine hardware performance monitor event selector 5  */
76 
  CSR_MHPMEVENT6     = 0x326, /**< 0x326 - mhpmevent6  (r/w): Machine hardware performance monitor event selector 6  */
77 
  CSR_MHPMEVENT7     = 0x327, /**< 0x327 - mhpmevent7  (r/w): Machine hardware performance monitor event selector 7  */
78 
  CSR_MHPMEVENT8     = 0x328, /**< 0x328 - mhpmevent8  (r/w): Machine hardware performance monitor event selector 8  */
79 
  CSR_MHPMEVENT9     = 0x329, /**< 0x329 - mhpmevent9  (r/w): Machine hardware performance monitor event selector 9  */
80 
  CSR_MHPMEVENT10    = 0x32a, /**< 0x32a - mhpmevent10 (r/w): Machine hardware performance monitor event selector 10 */
81 
  CSR_MHPMEVENT11    = 0x32b, /**< 0x32b - mhpmevent11 (r/w): Machine hardware performance monitor event selector 11 */
82 
  CSR_MHPMEVENT12    = 0x32c, /**< 0x32c - mhpmevent12 (r/w): Machine hardware performance monitor event selector 12 */
83 
  CSR_MHPMEVENT13    = 0x32d, /**< 0x32d - mhpmevent13 (r/w): Machine hardware performance monitor event selector 13 */
84 
  CSR_MHPMEVENT14    = 0x32e, /**< 0x32e - mhpmevent14 (r/w): Machine hardware performance monitor event selector 14 */
85 
  CSR_MHPMEVENT15    = 0x32f, /**< 0x32f - mhpmevent15 (r/w): Machine hardware performance monitor event selector 15 */
86 
  CSR_MHPMEVENT16    = 0x330, /**< 0x330 - mhpmevent16 (r/w): Machine hardware performance monitor event selector 16 */
87 
  CSR_MHPMEVENT17    = 0x331, /**< 0x331 - mhpmevent17 (r/w): Machine hardware performance monitor event selector 17 */
88 
  CSR_MHPMEVENT18    = 0x332, /**< 0x332 - mhpmevent18 (r/w): Machine hardware performance monitor event selector 18 */
89 
  CSR_MHPMEVENT19    = 0x333, /**< 0x333 - mhpmevent19 (r/w): Machine hardware performance monitor event selector 19 */
90 
  CSR_MHPMEVENT20    = 0x334, /**< 0x334 - mhpmevent20 (r/w): Machine hardware performance monitor event selector 20 */
91 
  CSR_MHPMEVENT21    = 0x335, /**< 0x335 - mhpmevent21 (r/w): Machine hardware performance monitor event selector 21 */
92 
  CSR_MHPMEVENT22    = 0x336, /**< 0x336 - mhpmevent22 (r/w): Machine hardware performance monitor event selector 22 */
93 
  CSR_MHPMEVENT23    = 0x337, /**< 0x337 - mhpmevent23 (r/w): Machine hardware performance monitor event selector 23 */
94 
  CSR_MHPMEVENT24    = 0x338, /**< 0x338 - mhpmevent24 (r/w): Machine hardware performance monitor event selector 24 */
95 
  CSR_MHPMEVENT25    = 0x339, /**< 0x339 - mhpmevent25 (r/w): Machine hardware performance monitor event selector 25 */
96 
  CSR_MHPMEVENT26    = 0x33a, /**< 0x33a - mhpmevent26 (r/w): Machine hardware performance monitor event selector 26 */
97 
  CSR_MHPMEVENT27    = 0x33b, /**< 0x33b - mhpmevent27 (r/w): Machine hardware performance monitor event selector 27 */
98 
  CSR_MHPMEVENT28    = 0x33c, /**< 0x33c - mhpmevent28 (r/w): Machine hardware performance monitor event selector 28 */
99 
  CSR_MHPMEVENT29    = 0x33d, /**< 0x33d - mhpmevent29 (r/w): Machine hardware performance monitor event selector 29 */
100 
  CSR_MHPMEVENT30    = 0x33e, /**< 0x33e - mhpmevent30 (r/w): Machine hardware performance monitor event selector 30 */
101 
  CSR_MHPMEVENT31    = 0x33f, /**< 0x33f - mhpmevent31 (r/w): Machine hardware performance monitor event selector 31 */
102 15 zero_gravi 
 
103 42 zero_gravi 
  CSR_MSCRATCH       = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
104 
  CSR_MEPC           = 0x341, /**< 0x341 - mepc     (r/w): Machine exception program counter */
105 
  CSR_MCAUSE         = 0x342, /**< 0x342 - mcause   (r/w): Machine trap cause */
106 60 zero_gravi 
  CSR_MTVAL          = 0x343, /**< 0x343 - mtval    (r/-): Machine bad address or instruction */
107 58 zero_gravi 
  CSR_MIP            = 0x344, /**< 0x344 - mip      (r/-): Machine interrupt pending register */
108 15 zero_gravi 
 
109 42 zero_gravi 
  CSR_PMPCFG0        = 0x3a0, /**< 0x3a0 - pmpcfg0  (r/w): Physical memory protection configuration register 0  */
110 
  CSR_PMPCFG1        = 0x3a1, /**< 0x3a1 - pmpcfg1  (r/w): Physical memory protection configuration register 1  */
111 
  CSR_PMPCFG2        = 0x3a2, /**< 0x3a2 - pmpcfg2  (r/w): Physical memory protection configuration register 2  */
112 
  CSR_PMPCFG3        = 0x3a3, /**< 0x3a3 - pmpcfg3  (r/w): Physical memory protection configuration register 3  */
113 
  CSR_PMPCFG4        = 0x3a4, /**< 0x3a4 - pmpcfg4  (r/w): Physical memory protection configuration register 4  */
114 
  CSR_PMPCFG5        = 0x3a5, /**< 0x3a5 - pmpcfg5  (r/w): Physical memory protection configuration register 5  */
115 
  CSR_PMPCFG6        = 0x3a6, /**< 0x3a6 - pmpcfg6  (r/w): Physical memory protection configuration register 6  */
116 
  CSR_PMPCFG7        = 0x3a7, /**< 0x3a7 - pmpcfg7  (r/w): Physical memory protection configuration register 7  */
117 
  CSR_PMPCFG8        = 0x3a8, /**< 0x3a8 - pmpcfg8  (r/w): Physical memory protection configuration register 8  */
118 
  CSR_PMPCFG9        = 0x3a9, /**< 0x3a9 - pmpcfg9  (r/w): Physical memory protection configuration register 9  */
119 
  CSR_PMPCFG10       = 0x3aa, /**< 0x3aa - pmpcfg10 (r/w): Physical memory protection configuration register 10 */
120 
  CSR_PMPCFG11       = 0x3ab, /**< 0x3ab - pmpcfg11 (r/w): Physical memory protection configuration register 11 */
121 
  CSR_PMPCFG12       = 0x3ac, /**< 0x3ac - pmpcfg12 (r/w): Physical memory protection configuration register 12 */
122 
  CSR_PMPCFG13       = 0x3ad, /**< 0x3ad - pmpcfg13 (r/w): Physical memory protection configuration register 13 */
123 
  CSR_PMPCFG14       = 0x3ae, /**< 0x3ae - pmpcfg14 (r/w): Physical memory protection configuration register 14 */
124 
  CSR_PMPCFG15       = 0x3af, /**< 0x3af - pmpcfg15 (r/w): Physical memory protection configuration register 15 */
125 18 zero_gravi 
 
126 42 zero_gravi 
  CSR_PMPADDR0       = 0x3b0, /**< 0x3b0 - pmpaddr0  (r/w): Physical memory protection address register 0  */
127 
  CSR_PMPADDR1       = 0x3b1, /**< 0x3b1 - pmpaddr1  (r/w): Physical memory protection address register 1  */
128 
  CSR_PMPADDR2       = 0x3b2, /**< 0x3b2 - pmpaddr2  (r/w): Physical memory protection address register 2  */
129 
  CSR_PMPADDR3       = 0x3b3, /**< 0x3b3 - pmpaddr3  (r/w): Physical memory protection address register 3  */
130 
  CSR_PMPADDR4       = 0x3b4, /**< 0x3b4 - pmpaddr4  (r/w): Physical memory protection address register 4  */
131 
  CSR_PMPADDR5       = 0x3b5, /**< 0x3b5 - pmpaddr5  (r/w): Physical memory protection address register 5  */
132 
  CSR_PMPADDR6       = 0x3b6, /**< 0x3b6 - pmpaddr6  (r/w): Physical memory protection address register 6  */
133 
  CSR_PMPADDR7       = 0x3b7, /**< 0x3b7 - pmpaddr7  (r/w): Physical memory protection address register 7  */
134 
  CSR_PMPADDR8       = 0x3b8, /**< 0x3b8 - pmpaddr8  (r/w): Physical memory protection address register 8  */
135 
  CSR_PMPADDR9       = 0x3b9, /**< 0x3b9 - pmpaddr9  (r/w): Physical memory protection address register 9  */
136 
  CSR_PMPADDR10      = 0x3ba, /**< 0x3ba - pmpaddr10 (r/w): Physical memory protection address register 10 */
137 
  CSR_PMPADDR11      = 0x3bb, /**< 0x3bb - pmpaddr11 (r/w): Physical memory protection address register 11 */
138 
  CSR_PMPADDR12      = 0x3bc, /**< 0x3bc - pmpaddr12 (r/w): Physical memory protection address register 12 */
139 
  CSR_PMPADDR13      = 0x3bd, /**< 0x3bd - pmpaddr13 (r/w): Physical memory protection address register 13 */
140 
  CSR_PMPADDR14      = 0x3be, /**< 0x3be - pmpaddr14 (r/w): Physical memory protection address register 14 */
141 
  CSR_PMPADDR15      = 0x3bf, /**< 0x3bf - pmpaddr15 (r/w): Physical memory protection address register 15 */
142 
  CSR_PMPADDR16      = 0x3c0, /**< 0x3c0 - pmpaddr16 (r/w): Physical memory protection address register 16 */
143 
  CSR_PMPADDR17      = 0x3c1, /**< 0x3c1 - pmpaddr17 (r/w): Physical memory protection address register 17 */
144 
  CSR_PMPADDR18      = 0x3c2, /**< 0x3c2 - pmpaddr18 (r/w): Physical memory protection address register 18 */
145 
  CSR_PMPADDR19      = 0x3c3, /**< 0x3c3 - pmpaddr19 (r/w): Physical memory protection address register 19 */
146 
  CSR_PMPADDR20      = 0x3c4, /**< 0x3c4 - pmpaddr20 (r/w): Physical memory protection address register 20 */
147 
  CSR_PMPADDR21      = 0x3c5, /**< 0x3c5 - pmpaddr21 (r/w): Physical memory protection address register 21 */
148 
  CSR_PMPADDR22      = 0x3c6, /**< 0x3c6 - pmpaddr22 (r/w): Physical memory protection address register 22 */
149 
  CSR_PMPADDR23      = 0x3c7, /**< 0x3c7 - pmpaddr23 (r/w): Physical memory protection address register 23 */
150 
  CSR_PMPADDR24      = 0x3c8, /**< 0x3c8 - pmpaddr24 (r/w): Physical memory protection address register 24 */
151 
  CSR_PMPADDR25      = 0x3c9, /**< 0x3c9 - pmpaddr25 (r/w): Physical memory protection address register 25 */
152 
  CSR_PMPADDR26      = 0x3ca, /**< 0x3ca - pmpaddr26 (r/w): Physical memory protection address register 26 */
153 
  CSR_PMPADDR27      = 0x3cb, /**< 0x3cb - pmpaddr27 (r/w): Physical memory protection address register 27 */
154 
  CSR_PMPADDR28      = 0x3cc, /**< 0x3cc - pmpaddr28 (r/w): Physical memory protection address register 28 */
155 
  CSR_PMPADDR29      = 0x3cd, /**< 0x3cd - pmpaddr29 (r/w): Physical memory protection address register 29 */
156 
  CSR_PMPADDR30      = 0x3ce, /**< 0x3ce - pmpaddr30 (r/w): Physical memory protection address register 30 */
157 
  CSR_PMPADDR31      = 0x3cf, /**< 0x3cf - pmpaddr31 (r/w): Physical memory protection address register 31 */
158 
  CSR_PMPADDR32      = 0x3d0, /**< 0x3d0 - pmpaddr32 (r/w): Physical memory protection address register 32 */
159 
  CSR_PMPADDR33      = 0x3d1, /**< 0x3d1 - pmpaddr33 (r/w): Physical memory protection address register 33 */
160 
  CSR_PMPADDR34      = 0x3d2, /**< 0x3d2 - pmpaddr34 (r/w): Physical memory protection address register 34 */
161 
  CSR_PMPADDR35      = 0x3d3, /**< 0x3d3 - pmpaddr35 (r/w): Physical memory protection address register 35 */
162 
  CSR_PMPADDR36      = 0x3d4, /**< 0x3d4 - pmpaddr36 (r/w): Physical memory protection address register 36 */
163 
  CSR_PMPADDR37      = 0x3d5, /**< 0x3d5 - pmpaddr37 (r/w): Physical memory protection address register 37 */
164 
  CSR_PMPADDR38      = 0x3d6, /**< 0x3d6 - pmpaddr38 (r/w): Physical memory protection address register 38 */
165 
  CSR_PMPADDR39      = 0x3d7, /**< 0x3d7 - pmpaddr39 (r/w): Physical memory protection address register 39 */
166 
  CSR_PMPADDR40      = 0x3d8, /**< 0x3d8 - pmpaddr40 (r/w): Physical memory protection address register 40 */
167 
  CSR_PMPADDR41      = 0x3d9, /**< 0x3d9 - pmpaddr41 (r/w): Physical memory protection address register 41 */
168 
  CSR_PMPADDR42      = 0x3da, /**< 0x3da - pmpaddr42 (r/w): Physical memory protection address register 42 */
169 
  CSR_PMPADDR43      = 0x3db, /**< 0x3db - pmpaddr43 (r/w): Physical memory protection address register 43 */
170 
  CSR_PMPADDR44      = 0x3dc, /**< 0x3dc - pmpaddr44 (r/w): Physical memory protection address register 44 */
171 
  CSR_PMPADDR45      = 0x3dd, /**< 0x3dd - pmpaddr45 (r/w): Physical memory protection address register 45 */
172 
  CSR_PMPADDR46      = 0x3de, /**< 0x3de - pmpaddr46 (r/w): Physical memory protection address register 46 */
173 
  CSR_PMPADDR47      = 0x3df, /**< 0x3df - pmpaddr47 (r/w): Physical memory protection address register 47 */
174 
  CSR_PMPADDR48      = 0x3e0, /**< 0x3e0 - pmpaddr48 (r/w): Physical memory protection address register 48 */
175 
  CSR_PMPADDR49      = 0x3e1, /**< 0x3e1 - pmpaddr49 (r/w): Physical memory protection address register 49 */
176 
  CSR_PMPADDR50      = 0x3e2, /**< 0x3e2 - pmpaddr50 (r/w): Physical memory protection address register 50 */
177 
  CSR_PMPADDR51      = 0x3e3, /**< 0x3e3 - pmpaddr51 (r/w): Physical memory protection address register 51 */
178 
  CSR_PMPADDR52      = 0x3e4, /**< 0x3e4 - pmpaddr52 (r/w): Physical memory protection address register 52 */
179 
  CSR_PMPADDR53      = 0x3e5, /**< 0x3e5 - pmpaddr53 (r/w): Physical memory protection address register 53 */
180 
  CSR_PMPADDR54      = 0x3e6, /**< 0x3e6 - pmpaddr54 (r/w): Physical memory protection address register 54 */
181 
  CSR_PMPADDR55      = 0x3e7, /**< 0x3e7 - pmpaddr55 (r/w): Physical memory protection address register 55 */
182 
  CSR_PMPADDR56      = 0x3e8, /**< 0x3e8 - pmpaddr56 (r/w): Physical memory protection address register 56 */
183 
  CSR_PMPADDR57      = 0x3e9, /**< 0x3e9 - pmpaddr57 (r/w): Physical memory protection address register 57 */
184 
  CSR_PMPADDR58      = 0x3ea, /**< 0x3ea - pmpaddr58 (r/w): Physical memory protection address register 58 */
185 
  CSR_PMPADDR59      = 0x3eb, /**< 0x3eb - pmpaddr59 (r/w): Physical memory protection address register 59 */
186 
  CSR_PMPADDR60      = 0x3ec, /**< 0x3ec - pmpaddr60 (r/w): Physical memory protection address register 60 */
187 
  CSR_PMPADDR61      = 0x3ed, /**< 0x3ed - pmpaddr61 (r/w): Physical memory protection address register 61 */
188 
  CSR_PMPADDR62      = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */
189 
  CSR_PMPADDR63      = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */
190 2 zero_gravi 
 
191 61 zero_gravi 
  CSR_MCYCLE         = 0xb00, /**< 0xb00 - mcycle   (r/w): Machine cycle counter low word */
192 
  CSR_MINSTRET       = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
193 2 zero_gravi 
 
194 42 zero_gravi 
  CSR_MHPMCOUNTER3   = 0xb03, /**< 0xb03 - mhpmcounter3  (r/w): Machine hardware performance monitor 3  counter low word */
195 
  CSR_MHPMCOUNTER4   = 0xb04, /**< 0xb04 - mhpmcounter4  (r/w): Machine hardware performance monitor 4  counter low word */
196 
  CSR_MHPMCOUNTER5   = 0xb05, /**< 0xb05 - mhpmcounter5  (r/w): Machine hardware performance monitor 5  counter low word */
197 
  CSR_MHPMCOUNTER6   = 0xb06, /**< 0xb06 - mhpmcounter6  (r/w): Machine hardware performance monitor 6  counter low word */
198 
  CSR_MHPMCOUNTER7   = 0xb07, /**< 0xb07 - mhpmcounter7  (r/w): Machine hardware performance monitor 7  counter low word */
199 
  CSR_MHPMCOUNTER8   = 0xb08, /**< 0xb08 - mhpmcounter8  (r/w): Machine hardware performance monitor 8  counter low word */
200 
  CSR_MHPMCOUNTER9   = 0xb09, /**< 0xb09 - mhpmcounter9  (r/w): Machine hardware performance monitor 9  counter low word */
201 
  CSR_MHPMCOUNTER10  = 0xb0a, /**< 0xb0a - mhpmcounter10 (r/w): Machine hardware performance monitor 10 counter low word */
202 
  CSR_MHPMCOUNTER11  = 0xb0b, /**< 0xb0b - mhpmcounter11 (r/w): Machine hardware performance monitor 11 counter low word */
203 
  CSR_MHPMCOUNTER12  = 0xb0c, /**< 0xb0c - mhpmcounter12 (r/w): Machine hardware performance monitor 12 counter low word */
204 
  CSR_MHPMCOUNTER13  = 0xb0d, /**< 0xb0d - mhpmcounter13 (r/w): Machine hardware performance monitor 13 counter low word */
205 
  CSR_MHPMCOUNTER14  = 0xb0e, /**< 0xb0e - mhpmcounter14 (r/w): Machine hardware performance monitor 14 counter low word */
206 
  CSR_MHPMCOUNTER15  = 0xb0f, /**< 0xb0f - mhpmcounter15 (r/w): Machine hardware performance monitor 15 counter low word */
207 
  CSR_MHPMCOUNTER16  = 0xb10, /**< 0xb10 - mhpmcounter16 (r/w): Machine hardware performance monitor 16 counter low word */
208 
  CSR_MHPMCOUNTER17  = 0xb11, /**< 0xb11 - mhpmcounter17 (r/w): Machine hardware performance monitor 17 counter low word */
209 
  CSR_MHPMCOUNTER18  = 0xb12, /**< 0xb12 - mhpmcounter18 (r/w): Machine hardware performance monitor 18 counter low word */
210 
  CSR_MHPMCOUNTER19  = 0xb13, /**< 0xb13 - mhpmcounter19 (r/w): Machine hardware performance monitor 19 counter low word */
211 
  CSR_MHPMCOUNTER20  = 0xb14, /**< 0xb14 - mhpmcounter20 (r/w): Machine hardware performance monitor 20 counter low word */
212 
  CSR_MHPMCOUNTER21  = 0xb15, /**< 0xb15 - mhpmcounter21 (r/w): Machine hardware performance monitor 21 counter low word */
213 
  CSR_MHPMCOUNTER22  = 0xb16, /**< 0xb16 - mhpmcounter22 (r/w): Machine hardware performance monitor 22 counter low word */
214 
  CSR_MHPMCOUNTER23  = 0xb17, /**< 0xb17 - mhpmcounter23 (r/w): Machine hardware performance monitor 23 counter low word */
215 
  CSR_MHPMCOUNTER24  = 0xb18, /**< 0xb18 - mhpmcounter24 (r/w): Machine hardware performance monitor 24 counter low word */
216 
  CSR_MHPMCOUNTER25  = 0xb19, /**< 0xb19 - mhpmcounter25 (r/w): Machine hardware performance monitor 25 counter low word */
217 
  CSR_MHPMCOUNTER26  = 0xb1a, /**< 0xb1a - mhpmcounter26 (r/w): Machine hardware performance monitor 26 counter low word */
218 
  CSR_MHPMCOUNTER27  = 0xb1b, /**< 0xb1b - mhpmcounter27 (r/w): Machine hardware performance monitor 27 counter low word */
219 
  CSR_MHPMCOUNTER28  = 0xb1c, /**< 0xb1c - mhpmcounter28 (r/w): Machine hardware performance monitor 28 counter low word */
220 
  CSR_MHPMCOUNTER29  = 0xb1d, /**< 0xb1d - mhpmcounter29 (r/w): Machine hardware performance monitor 29 counter low word */
221 
  CSR_MHPMCOUNTER30  = 0xb1e, /**< 0xb1e - mhpmcounter30 (r/w): Machine hardware performance monitor 30 counter low word */
222 
  CSR_MHPMCOUNTER31  = 0xb1f, /**< 0xb1f - mhpmcounter31 (r/w): Machine hardware performance monitor 31 counter low word */
223 2 zero_gravi 
 
224 61 zero_gravi 
  CSR_MCYCLEH        = 0xb80, /**< 0xb80 - mcycleh   (r/w): Machine cycle counter high word */
225 
  CSR_MINSTRETH      = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
226 22 zero_gravi 
 
227 42 zero_gravi 
  CSR_MHPMCOUNTER3H  = 0xb83, /**< 0xb83 - mhpmcounter3h  (r/w): Machine hardware performance monitor 3  counter high word */
228 
  CSR_MHPMCOUNTER4H  = 0xb84, /**< 0xb84 - mhpmcounter4h  (r/w): Machine hardware performance monitor 4  counter high word */
229 
  CSR_MHPMCOUNTER5H  = 0xb85, /**< 0xb85 - mhpmcounter5h  (r/w): Machine hardware performance monitor 5  counter high word */
230 
  CSR_MHPMCOUNTER6H  = 0xb86, /**< 0xb86 - mhpmcounter6h  (r/w): Machine hardware performance monitor 6  counter high word */
231 
  CSR_MHPMCOUNTER7H  = 0xb87, /**< 0xb87 - mhpmcounter7h  (r/w): Machine hardware performance monitor 7  counter high word */
232 
  CSR_MHPMCOUNTER8H  = 0xb88, /**< 0xb88 - mhpmcounter8h  (r/w): Machine hardware performance monitor 8  counter high word */
233 
  CSR_MHPMCOUNTER9H  = 0xb89, /**< 0xb89 - mhpmcounter9h  (r/w): Machine hardware performance monitor 9  counter high word */
234 
  CSR_MHPMCOUNTER10H = 0xb8a, /**< 0xb8a - mhpmcounter10h (r/w): Machine hardware performance monitor 10 counter high word */
235 
  CSR_MHPMCOUNTER11H = 0xb8b, /**< 0xb8b - mhpmcounter11h (r/w): Machine hardware performance monitor 11 counter high word */
236 
  CSR_MHPMCOUNTER12H = 0xb8c, /**< 0xb8c - mhpmcounter12h (r/w): Machine hardware performance monitor 12 counter high word */
237 
  CSR_MHPMCOUNTER13H = 0xb8d, /**< 0xb8d - mhpmcounter13h (r/w): Machine hardware performance monitor 13 counter high word */
238 
  CSR_MHPMCOUNTER14H = 0xb8e, /**< 0xb8e - mhpmcounter14h (r/w): Machine hardware performance monitor 14 counter high word */
239 
  CSR_MHPMCOUNTER15H = 0xb8f, /**< 0xb8f - mhpmcounter15h (r/w): Machine hardware performance monitor 15 counter high word */
240 
  CSR_MHPMCOUNTER16H = 0xb90, /**< 0xb90 - mhpmcounter16h (r/w): Machine hardware performance monitor 16 counter high word */
241 
  CSR_MHPMCOUNTER17H = 0xb91, /**< 0xb91 - mhpmcounter17h (r/w): Machine hardware performance monitor 17 counter high word */
242 
  CSR_MHPMCOUNTER18H = 0xb92, /**< 0xb92 - mhpmcounter18h (r/w): Machine hardware performance monitor 18 counter high word */
243 
  CSR_MHPMCOUNTER19H = 0xb93, /**< 0xb93 - mhpmcounter19h (r/w): Machine hardware performance monitor 19 counter high word */
244 
  CSR_MHPMCOUNTER20H = 0xb94, /**< 0xb94 - mhpmcounter20h (r/w): Machine hardware performance monitor 20 counter high word */
245 
  CSR_MHPMCOUNTER21H = 0xb95, /**< 0xb95 - mhpmcounter21h (r/w): Machine hardware performance monitor 21 counter high word */
246 
  CSR_MHPMCOUNTER22H = 0xb96, /**< 0xb96 - mhpmcounter22h (r/w): Machine hardware performance monitor 22 counter high word */
247 
  CSR_MHPMCOUNTER23H = 0xb97, /**< 0xb97 - mhpmcounter23h (r/w): Machine hardware performance monitor 23 counter high word */
248 
  CSR_MHPMCOUNTER24H = 0xb98, /**< 0xb98 - mhpmcounter24h (r/w): Machine hardware performance monitor 24 counter high word */
249 
  CSR_MHPMCOUNTER25H = 0xb99, /**< 0xb99 - mhpmcounter25h (r/w): Machine hardware performance monitor 25 counter high word */
250 
  CSR_MHPMCOUNTER26H = 0xb9a, /**< 0xb9a - mhpmcounter26h (r/w): Machine hardware performance monitor 26 counter high word */
251 
  CSR_MHPMCOUNTER27H = 0xb9b, /**< 0xb9b - mhpmcounter27h (r/w): Machine hardware performance monitor 27 counter high word */
252 
  CSR_MHPMCOUNTER28H = 0xb9c, /**< 0xb9c - mhpmcounter28h (r/w): Machine hardware performance monitor 28 counter high word */
253 
  CSR_MHPMCOUNTER29H = 0xb9d, /**< 0xb9d - mhpmcounter29h (r/w): Machine hardware performance monitor 29 counter high word */
254 
  CSR_MHPMCOUNTER30H = 0xb9e, /**< 0xb9e - mhpmcounter30h (r/w): Machine hardware performance monitor 30 counter high word */
255 
  CSR_MHPMCOUNTER31H = 0xb9f, /**< 0xb9f - mhpmcounter31h (r/w): Machine hardware performance monitor 31 counter high word */
256 41 zero_gravi 
 
257 61 zero_gravi 
  CSR_CYCLE          = 0xc00, /**< 0xc00 - cycle   (r/-): Cycle counter low word (from MCYCLE) */
258 
  CSR_TIME           = 0xc01, /**< 0xc01 - time    (r/-): Timer low word (from MTIME.TIME_LO) */
259 
  CSR_INSTRET        = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
260 42 zero_gravi 
 
261 61 zero_gravi 
  CSR_CYCLEH         = 0xc80, /**< 0xc80 - cycleh   (r/-): Cycle counter high word (from MCYCLEH) */
262 
  CSR_TIMEH          = 0xc81, /**< 0xc81 - timeh    (r/-): Timer high word (from MTIME.TIME_HI) */
263 
  CSR_INSTRETH       = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
264 42 zero_gravi 
 
265 
  CSR_MVENDORID      = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
266 
  CSR_MARCHID        = 0xf12, /**< 0xf12 - marchid   (r/-): Architecture ID */
267 
  CSR_MIMPID         = 0xf13, /**< 0xf13 - mimpid    (r/-): Implementation ID/version */
268 
  CSR_MHARTID        = 0xf14, /**< 0xf14 - mhartid   (r/-): Hardware thread ID (always 0) */
269 
 
270 
  CSR_MZEXT          = 0xfc0  /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
271 2 zero_gravi 
};
272 
 
273 
 
274 
/**********************************************************************//**
275 
 * CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
276 
 **************************************************************************/
277 42 zero_gravi 
enum NEORV32_CSR_MSTATUS_enum {
278 44 zero_gravi 
  CSR_MSTATUS_MIE   =  3, /**< CPU mstatus CSR  (3): MIE - Machine interrupt enable bit (r/w) */
279 
  CSR_MSTATUS_MPIE  =  7, /**< CPU mstatus CSR  (7): MPIE - Machine previous interrupt enable bit (r/w) */
280 42 zero_gravi 
  CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
281 
  CSR_MSTATUS_MPP_H = 12  /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
282 2 zero_gravi 
};
283 
 
284 
 
285 
/**********************************************************************//**
286 41 zero_gravi 
 * CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
287 
 **************************************************************************/
288 42 zero_gravi 
enum NEORV32_CSR_MCOUNTEREN_enum {
289 61 zero_gravi 
  CSR_MCOUNTEREN_CY    = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h]   CSRs from U-mode when set (r/w) */
290 
  CSR_MCOUNTEREN_TM    = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h]    CSRs from U-mode when set (r/w) */
291 
  CSR_MCOUNTEREN_IR    = 2  /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
292 41 zero_gravi 
};
293 
 
294 
 
295 
/**********************************************************************//**
296 
 * CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.)
297 
 **************************************************************************/
298 42 zero_gravi 
enum NEORV32_CSR_MCOUNTINHIBIT_enum {
299 56 zero_gravi 
  CSR_MCOUNTINHIBIT_CY    = 0,  /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h]   CSR when set (r/w) */
300 
  CSR_MCOUNTINHIBIT_IR    = 2,  /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */
301 
 
302 
  CSR_MCOUNTINHIBIT_HPM3  = 3,  /**< CPU mcountinhibit CSR (3):  HPM3  - Enable auto-increment of hpmcnt3[h]  when set (r/w) */
303 
  CSR_MCOUNTINHIBIT_HPM4  = 4,  /**< CPU mcountinhibit CSR (4):  HPM4  - Enable auto-increment of hpmcnt4[h]  when set (r/w) */
304 
  CSR_MCOUNTINHIBIT_HPM5  = 5,  /**< CPU mcountinhibit CSR (5):  HPM5  - Enable auto-increment of hpmcnt5[h]  when set (r/w) */
305 
  CSR_MCOUNTINHIBIT_HPM6  = 6,  /**< CPU mcountinhibit CSR (6):  HPM6  - Enable auto-increment of hpmcnt6[h]  when set (r/w) */
306 
  CSR_MCOUNTINHIBIT_HPM7  = 7,  /**< CPU mcountinhibit CSR (7):  HPM7  - Enable auto-increment of hpmcnt7[h]  when set (r/w) */
307 
  CSR_MCOUNTINHIBIT_HPM8  = 8,  /**< CPU mcountinhibit CSR (8):  HPM8  - Enable auto-increment of hpmcnt8[h]  when set (r/w) */
308 
  CSR_MCOUNTINHIBIT_HPM9  = 9,  /**< CPU mcountinhibit CSR (9):  HPM9  - Enable auto-increment of hpmcnt9[h]  when set (r/w) */
309 
  CSR_MCOUNTINHIBIT_HPM10 = 10, /**< CPU mcountinhibit CSR (10): HPM10 - Enable auto-increment of hpmcnt10[h] when set (r/w) */
310 
  CSR_MCOUNTINHIBIT_HPM11 = 11, /**< CPU mcountinhibit CSR (11): HPM11 - Enable auto-increment of hpmcnt11[h] when set (r/w) */
311 
  CSR_MCOUNTINHIBIT_HPM12 = 12, /**< CPU mcountinhibit CSR (12): HPM12 - Enable auto-increment of hpmcnt12[h] when set (r/w) */
312 
  CSR_MCOUNTINHIBIT_HPM13 = 13, /**< CPU mcountinhibit CSR (13): HPM13 - Enable auto-increment of hpmcnt13[h] when set (r/w) */
313 
  CSR_MCOUNTINHIBIT_HPM14 = 14, /**< CPU mcountinhibit CSR (14): HPM14 - Enable auto-increment of hpmcnt14[h] when set (r/w) */
314 
  CSR_MCOUNTINHIBIT_HPM15 = 15, /**< CPU mcountinhibit CSR (15): HPM15 - Enable auto-increment of hpmcnt15[h] when set (r/w) */
315 
  CSR_MCOUNTINHIBIT_HPM16 = 16, /**< CPU mcountinhibit CSR (16): HPM16 - Enable auto-increment of hpmcnt16[h] when set (r/w) */
316 
  CSR_MCOUNTINHIBIT_HPM17 = 17, /**< CPU mcountinhibit CSR (17): HPM17 - Enable auto-increment of hpmcnt17[h] when set (r/w) */
317 
  CSR_MCOUNTINHIBIT_HPM18 = 18, /**< CPU mcountinhibit CSR (18): HPM18 - Enable auto-increment of hpmcnt18[h] when set (r/w) */
318 
  CSR_MCOUNTINHIBIT_HPM19 = 19, /**< CPU mcountinhibit CSR (19): HPM19 - Enable auto-increment of hpmcnt19[h] when set (r/w) */
319 
  CSR_MCOUNTINHIBIT_HPM20 = 20, /**< CPU mcountinhibit CSR (20): HPM20 - Enable auto-increment of hpmcnt20[h] when set (r/w) */
320 
  CSR_MCOUNTINHIBIT_HPM21 = 21, /**< CPU mcountinhibit CSR (21): HPM21 - Enable auto-increment of hpmcnt21[h] when set (r/w) */
321 
  CSR_MCOUNTINHIBIT_HPM22 = 22, /**< CPU mcountinhibit CSR (22): HPM22 - Enable auto-increment of hpmcnt22[h] when set (r/w) */
322 
  CSR_MCOUNTINHIBIT_HPM23 = 23, /**< CPU mcountinhibit CSR (23): HPM23 - Enable auto-increment of hpmcnt23[h] when set (r/w) */
323 
  CSR_MCOUNTINHIBIT_HPM24 = 24, /**< CPU mcountinhibit CSR (24): HPM24 - Enable auto-increment of hpmcnt24[h] when set (r/w) */
324 
  CSR_MCOUNTINHIBIT_HPM25 = 25, /**< CPU mcountinhibit CSR (25): HPM25 - Enable auto-increment of hpmcnt25[h] when set (r/w) */
325 
  CSR_MCOUNTINHIBIT_HPM26 = 26, /**< CPU mcountinhibit CSR (26): HPM26 - Enable auto-increment of hpmcnt26[h] when set (r/w) */
326 
  CSR_MCOUNTINHIBIT_HPM27 = 27, /**< CPU mcountinhibit CSR (27): HPM27 - Enable auto-increment of hpmcnt27[h] when set (r/w) */
327 
  CSR_MCOUNTINHIBIT_HPM28 = 28, /**< CPU mcountinhibit CSR (28): HPM28 - Enable auto-increment of hpmcnt28[h] when set (r/w) */
328 
  CSR_MCOUNTINHIBIT_HPM29 = 29, /**< CPU mcountinhibit CSR (29): HPM29 - Enable auto-increment of hpmcnt29[h] when set (r/w) */
329 
  CSR_MCOUNTINHIBIT_HPM30 = 30, /**< CPU mcountinhibit CSR (30): HPM30 - Enable auto-increment of hpmcnt30[h] when set (r/w) */
330 
  CSR_MCOUNTINHIBIT_HPM31 = 31  /**< CPU mcountinhibit CSR (31): HPM31 - Enable auto-increment of hpmcnt31[h] when set (r/w) */
331 41 zero_gravi 
};
332 
 
333 
 
334 
/**********************************************************************//**
335 2 zero_gravi 
 * CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
336 
 **************************************************************************/
337 42 zero_gravi 
enum NEORV32_CSR_MIE_enum {
338 48 zero_gravi 
  CSR_MIE_MSIE    =  3, /**< CPU mie CSR  (3): MSIE - Machine software interrupt enable (r/w) */
339 
  CSR_MIE_MTIE    =  7, /**< CPU mie CSR  (7): MTIE - Machine timer interrupt enable bit (r/w) */
340 
  CSR_MIE_MEIE    = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */
341 
 
342 
  CSR_MIE_FIRQ0E  = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */
343 
  CSR_MIE_FIRQ1E  = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */
344 
  CSR_MIE_FIRQ2E  = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */
345 
  CSR_MIE_FIRQ3E  = 19, /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */
346 
  CSR_MIE_FIRQ4E  = 20, /**< CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) */
347 
  CSR_MIE_FIRQ5E  = 21, /**< CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) */
348 
  CSR_MIE_FIRQ6E  = 22, /**< CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) */
349 
  CSR_MIE_FIRQ7E  = 23, /**< CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) */
350 
  CSR_MIE_FIRQ8E  = 24, /**< CPU mie CSR (24): FIRQ8E - Fast interrupt channel 8 enable bit (r/w) */
351 
  CSR_MIE_FIRQ9E  = 25, /**< CPU mie CSR (25): FIRQ9E - Fast interrupt channel 9 enable bit (r/w) */
352 
  CSR_MIE_FIRQ10E = 26, /**< CPU mie CSR (26): FIRQ10E - Fast interrupt channel 10 enable bit (r/w) */
353 
  CSR_MIE_FIRQ11E = 27, /**< CPU mie CSR (27): FIRQ11E - Fast interrupt channel 11 enable bit (r/w) */
354 
  CSR_MIE_FIRQ12E = 28, /**< CPU mie CSR (28): FIRQ12E - Fast interrupt channel 12 enable bit (r/w) */
355 
  CSR_MIE_FIRQ13E = 29, /**< CPU mie CSR (29): FIRQ13E - Fast interrupt channel 13 enable bit (r/w) */
356 
  CSR_MIE_FIRQ14E = 30, /**< CPU mie CSR (30): FIRQ14E - Fast interrupt channel 14 enable bit (r/w) */
357 
  CSR_MIE_FIRQ15E = 31  /**< CPU mie CSR (31): FIRQ15E - Fast interrupt channel 15 enable bit (r/w) */
358 2 zero_gravi 
};
359 
 
360 
 
361 
/**********************************************************************//**
362 12 zero_gravi 
 * CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.)
363 2 zero_gravi 
 **************************************************************************/
364 42 zero_gravi 
enum NEORV32_CSR_MIP_enum {
365 48 zero_gravi 
  CSR_MIP_MSIP    =  3, /**< CPU mip CSR  (3): MSIP - Machine software interrupt pending (r/-) */
366 
  CSR_MIP_MTIP    =  7, /**< CPU mip CSR  (7): MTIP - Machine timer interrupt pending (r/-) */
367 
  CSR_MIP_MEIP    = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */
368 14 zero_gravi 
 
369 48 zero_gravi 
  CSR_MIP_FIRQ0P  = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */
370 
  CSR_MIP_FIRQ1P  = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */
371 
  CSR_MIP_FIRQ2P  = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */
372 
  CSR_MIP_FIRQ3P  = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */
373 
  CSR_MIP_FIRQ4P  = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */
374 
  CSR_MIP_FIRQ5P  = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */
375 
  CSR_MIP_FIRQ6P  = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */
376 
  CSR_MIP_FIRQ7P  = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */
377 
  CSR_MIP_FIRQ8P  = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) */
378 
  CSR_MIP_FIRQ9P  = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) */
379 
  CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) */
380 
  CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) */
381 
  CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) */
382 
  CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/-) */
383 
  CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/-) */
384 
  CSR_MIP_FIRQ15P = 31  /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/-) */
385 2 zero_gravi 
};
386 
 
387 
 
388 
/**********************************************************************//**
389 16 zero_gravi 
 * CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
390 6 zero_gravi 
 **************************************************************************/
391 42 zero_gravi 
enum NEORV32_CSR_MISA_enum {
392 61 zero_gravi 
  CSR_MISA_A      =  0, /**< CPU misa CSR  (0): A: Atomic instructions CPU extension available (r/-)*/
393 
  CSR_MISA_B      =  1, /**< CPU misa CSR  (1): B: Bit manipulation CPU extension available (r/-)*/
394 
  CSR_MISA_C      =  2, /**< CPU misa CSR  (2): C: Compressed instructions CPU extension available (r/-)*/
395 
  CSR_MISA_D      =  3, /**< CPU misa CSR  (3): D: Double-precision floating-point extension available (r/-)*/
396 
  CSR_MISA_E      =  4, /**< CPU misa CSR  (4): E: Embedded CPU extension available (r/-) */
397 
  CSR_MISA_F      =  5, /**< CPU misa CSR  (5): F: Single-precision floating-point extension available (r/-)*/
398 
  CSR_MISA_I      =  8, /**< CPU misa CSR  (8): I: Base integer ISA CPU extension available (r/-) */
399 
  CSR_MISA_M      = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
400 
  CSR_MISA_U      = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
401 
  CSR_MISA_X      = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
402 
  CSR_MISA_MXL_LO = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
403 
  CSR_MISA_MXL_HI = 31  /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
404 6 zero_gravi 
};
405 
 
406 
 
407 
/**********************************************************************//**
408 33 zero_gravi 
 * CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
409 
 **************************************************************************/
410 42 zero_gravi 
enum NEORV32_CSR_MZEXT_enum {
411 59 zero_gravi 
  CSR_MZEXT_ZICSR     =  0, /**< CPU mzext CSR (0): Zicsr extension (I sub-extension) available when set (r/-) */
412 
  CSR_MZEXT_ZIFENCEI  =  1, /**< CPU mzext CSR (1): Zifencei extension (I sub-extension) available when set (r/-) */
413 61 zero_gravi 
  CSR_MZEXT_ZMMUL     =  2, /**< CPU mzext CSR (2): Zmmul extension (M sub-extension) available when set (r/-) */
414 
 
415 59 zero_gravi 
  CSR_MZEXT_ZFINX     =  5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
416 
  CSR_MZEXT_ZXSCNT    =  6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
417 
  CSR_MZEXT_ZXNOCNT   =  7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
418 
  CSR_MZEXT_PMP       =  8, /**< CPU mzext CSR (8): PMP (physical memory protection) extension available when set (r/-) */
419 
  CSR_MZEXT_HPM       =  9, /**< CPU mzext CSR (9): HPM (hardware performance monitors) extension available when set (r/-) */
420 
  CSR_MZEXT_DEBUGMODE = 10  /**< CPU mzext CSR (10): RISC-V CPU debug mode available when set (r/-) */
421 33 zero_gravi 
};
422 
 
423 
 
424 
/**********************************************************************//**
425 42 zero_gravi 
 * CPU <b>mhpmevent</b> hardware performance monitor events
426 
 **************************************************************************/
427 
enum NEORV32_HPMCNT_EVENT_enum {
428 
  HPMCNT_EVENT_CY      = 0,  /**< CPU mhpmevent CSR (0):  Active cycle */
429 
  HPMCNT_EVENT_IR      = 2,  /**< CPU mhpmevent CSR (2):  Retired instruction */
430 
 
431 
  HPMCNT_EVENT_CIR     = 3,  /**< CPU mhpmevent CSR (3):  Retired compressed instruction */
432 
  HPMCNT_EVENT_WAIT_IF = 4,  /**< CPU mhpmevent CSR (4):  Instruction fetch memory wait cycle */
433 
  HPMCNT_EVENT_WAIT_II = 5,  /**< CPU mhpmevent CSR (5):  Instruction issue wait cycle */
434 45 zero_gravi 
  HPMCNT_EVENT_WAIT_MC = 6,  /**< CPU mhpmevent CSR (6):  Multi-cycle ALU-operation wait cycle */
435 
  HPMCNT_EVENT_LOAD    = 7,  /**< CPU mhpmevent CSR (7):  Load operation */
436 
  HPMCNT_EVENT_STORE   = 8,  /**< CPU mhpmevent CSR (8):  Store operation */
437 
  HPMCNT_EVENT_WAIT_LS = 9,  /**< CPU mhpmevent CSR (9):  Load/store memory wait cycle */
438 42 zero_gravi 
 
439 45 zero_gravi 
  HPMCNT_EVENT_JUMP    = 10, /**< CPU mhpmevent CSR (10): Unconditional jump */
440 
  HPMCNT_EVENT_BRANCH  = 11, /**< CPU mhpmevent CSR (11): Conditional branch (taken or not taken) */
441 
  HPMCNT_EVENT_TBRANCH = 12, /**< CPU mhpmevent CSR (12): Conditional taken branch */
442 42 zero_gravi 
 
443 45 zero_gravi 
  HPMCNT_EVENT_TRAP    = 13, /**< CPU mhpmevent CSR (13): Entered trap */
444 
  HPMCNT_EVENT_ILLEGAL = 14  /**< CPU mhpmevent CSR (14): Illegal instruction exception */
445 42 zero_gravi 
};
446 
 
447 
 
448 
/**********************************************************************//**
449 14 zero_gravi 
 * Trap codes from mcause CSR.
450 2 zero_gravi 
 **************************************************************************/
451 12 zero_gravi 
enum NEORV32_EXCEPTION_CODES_enum {
452 31 zero_gravi 
  TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0:  Instruction address misaligned */
453 
  TRAP_CODE_I_ACCESS     = 0x00000001, /**< 0.1:  Instruction (bus) access fault */
454 
  TRAP_CODE_I_ILLEGAL    = 0x00000002, /**< 0.2:  Illegal instruction */
455 
  TRAP_CODE_BREAKPOINT   = 0x00000003, /**< 0.3:  Breakpoint (EBREAK instruction) */
456 
  TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4:  Load address misaligned */
457 
  TRAP_CODE_L_ACCESS     = 0x00000005, /**< 0.5:  Load (bus) access fault */
458 
  TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6:  Store address misaligned */
459 
  TRAP_CODE_S_ACCESS     = 0x00000007, /**< 0.7:  Store (bus) access fault */
460 40 zero_gravi 
  TRAP_CODE_UENV_CALL    = 0x00000008, /**< 0.8:  Environment call from user mode (ECALL instruction) */
461 14 zero_gravi 
  TRAP_CODE_MENV_CALL    = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
462 58 zero_gravi 
  TRAP_CODE_NMI          = 0x80000000, /**< 1.0:  Non-maskable interrupt */
463 31 zero_gravi 
  TRAP_CODE_MSI          = 0x80000003, /**< 1.3:  Machine software interrupt */
464 
  TRAP_CODE_MTI          = 0x80000007, /**< 1.7:  Machine timer interrupt */
465 14 zero_gravi 
  TRAP_CODE_MEI          = 0x8000000b, /**< 1.11: Machine external interrupt */
466 
  TRAP_CODE_FIRQ_0       = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
467 
  TRAP_CODE_FIRQ_1       = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
468 
  TRAP_CODE_FIRQ_2       = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
469 47 zero_gravi 
  TRAP_CODE_FIRQ_3       = 0x80000013, /**< 1.19: Fast interrupt channel 3 */
470 
  TRAP_CODE_FIRQ_4       = 0x80000014, /**< 1.20: Fast interrupt channel 4 */
471 
  TRAP_CODE_FIRQ_5       = 0x80000015, /**< 1.21: Fast interrupt channel 5 */
472 
  TRAP_CODE_FIRQ_6       = 0x80000016, /**< 1.22: Fast interrupt channel 6 */
473 48 zero_gravi 
  TRAP_CODE_FIRQ_7       = 0x80000017, /**< 1.23: Fast interrupt channel 7 */
474 
  TRAP_CODE_FIRQ_8       = 0x80000018, /**< 1.24: Fast interrupt channel 8 */
475 
  TRAP_CODE_FIRQ_9       = 0x80000019, /**< 1.25: Fast interrupt channel 9 */
476 
  TRAP_CODE_FIRQ_10      = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */
477 
  TRAP_CODE_FIRQ_11      = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */
478 
  TRAP_CODE_FIRQ_12      = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */
479 
  TRAP_CODE_FIRQ_13      = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */
480 
  TRAP_CODE_FIRQ_14      = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */
481 
  TRAP_CODE_FIRQ_15      = 0x8000001f  /**< 1.31: Fast interrupt channel 15 */
482 12 zero_gravi 
};
483 
 
484 
 
485 
/**********************************************************************//**
486 52 zero_gravi 
 * Processor clock prescalers select
487 2 zero_gravi 
 **************************************************************************/
488 
enum NEORV32_CLOCK_PRSC_enum {
489 47 zero_gravi 
  CLK_PRSC_2    = 0, /**< CPU_CLK (from clk_i top signal) / 2 */
490 
  CLK_PRSC_4    = 1, /**< CPU_CLK (from clk_i top signal) / 4 */
491 
  CLK_PRSC_8    = 2, /**< CPU_CLK (from clk_i top signal) / 8 */
492 
  CLK_PRSC_64   = 3, /**< CPU_CLK (from clk_i top signal) / 64 */
493 
  CLK_PRSC_128  = 4, /**< CPU_CLK (from clk_i top signal) / 128 */
494 
  CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */
495 
  CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */
496 
  CLK_PRSC_4096 = 7  /**< CPU_CLK (from clk_i top signal) / 4096 */
497 2 zero_gravi 
};
498 
 
499 
 
500 
/**********************************************************************//**
501 34 zero_gravi 
 * Official NEORV32 >RISC-V open-source architecture ID<
502 
 * https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
503 32 zero_gravi 
 **************************************************************************/
504 
#define NEORV32_ARCHID 19
505 
 
506 
 
507 
/**********************************************************************//**
508 2 zero_gravi 
 * @name Helper macros for easy memory-mapped register access
509 
 **************************************************************************/
510 
/**@{*/
511 
/** memory-mapped byte (8-bit) read/write register */
512 
#define IO_REG8  (volatile uint8_t*)
513 
/** memory-mapped half-word (16-bit) read/write register */
514 
#define IO_REG16 (volatile uint16_t*)
515 
/** memory-mapped word (32-bit) read/write register */
516 
#define IO_REG32 (volatile uint32_t*)
517 
/** memory-mapped double-word (64-bit) read/write register */
518 
#define IO_REG64 (volatile uint64_t*)
519 
/** memory-mapped byte (8-bit) read-only register */
520 
#define IO_ROM8  (const volatile uint8_t*)
521 
/** memory-mapped half-word (16-bit) read-only register */
522 
#define IO_ROM16 (const volatile uint16_t*)
523 
/** memory-mapped word (32-bit) read-only register */
524 
#define IO_ROM32 (const volatile uint32_t*)
525 
/** memory-mapped double-word (64-bit) read-only register */
526 
#define IO_ROM64 (const volatile uint64_t*)
527 
/**@}*/
528 
 
529 
 
530 
/**********************************************************************//**
531 
 * @name Address space sections
532 
 **************************************************************************/
533 
/**@{*/
534 
/** instruction memory base address (r/w/x) */
535 23 zero_gravi 
// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
536 2 zero_gravi 
/** data memory base address (r/w/x) */
537 23 zero_gravi 
// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
538 2 zero_gravi 
/** bootloader memory base address (r/-/x) */
539 6 zero_gravi 
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL)
540 2 zero_gravi 
/** peripheral/IO devices memory base address (r/w/x) */
541 60 zero_gravi 
#define IO_BASE_ADDRESS         (0xFFFFFE00UL)
542 2 zero_gravi 
/**@}*/
543 
 
544 
 
545 60 zero_gravi 
// ############################################################################################################################
546 
// Peripheral/IO Devices - IO Address Space
547 
// ############################################################################################################################
548 
 
549 
 
550 2 zero_gravi 
/**********************************************************************//**
551 47 zero_gravi 
 * @name IO Device: Custom Functions Subsystem (CFS)
552 
 **************************************************************************/
553 
/**@{*/
554 60 zero_gravi 
/** CFS base address */
555 
#define CFS_BASE (0xFFFFFE00UL) // /**< CFS base address */
556 
/** CFS address space size in bytes */
557 
#define CFS_SIZE (64*4) // /**< CFS address space size in bytes */
558 
 
559 47 zero_gravi 
/** custom CFS register 0 */
560 60 zero_gravi 
#define CFS_REG_0  (*(IO_REG32 (CFS_BASE + 0))) // /**< (r)/(w): CFS register 0, user-defined */
561 47 zero_gravi 
/** custom CFS register 1 */
562 60 zero_gravi 
#define CFS_REG_1  (*(IO_REG32 (CFS_BASE + 4))) // /**< (r)/(w): CFS register 1, user-defined */
563 47 zero_gravi 
/** custom CFS register 2 */
564 60 zero_gravi 
#define CFS_REG_2  (*(IO_REG32 (CFS_BASE + 8))) // /**< (r)/(w): CFS register 2, user-defined */
565 47 zero_gravi 
/** custom CFS register 3 */
566 60 zero_gravi 
#define CFS_REG_3  (*(IO_REG32 (CFS_BASE + 12))) // /**< (r)/(w): CFS register 3, user-defined */
567 47 zero_gravi 
/** custom CFS register 4 */
568 60 zero_gravi 
#define CFS_REG_4  (*(IO_REG32 (CFS_BASE + 16))) // /**< (r)/(w): CFS register 4, user-defined */
569 47 zero_gravi 
/** custom CFS register 5 */
570 60 zero_gravi 
#define CFS_REG_5  (*(IO_REG32 (CFS_BASE + 20))) // /**< (r)/(w): CFS register 5, user-defined */
571 47 zero_gravi 
/** custom CFS register 6 */
572 60 zero_gravi 
#define CFS_REG_6  (*(IO_REG32 (CFS_BASE + 24))) // /**< (r)/(w): CFS register 6, user-defined */
573 47 zero_gravi 
/** custom CFS register 7 */
574 60 zero_gravi 
#define CFS_REG_7  (*(IO_REG32 (CFS_BASE + 28))) // /**< (r)/(w): CFS register 7, user-defined */
575 47 zero_gravi 
/** custom CFS register 8 */
576 60 zero_gravi 
#define CFS_REG_8  (*(IO_REG32 (CFS_BASE + 32))) // /**< (r)/(w): CFS register 8, user-defined */
577 47 zero_gravi 
/** custom CFS register 9 */
578 60 zero_gravi 
#define CFS_REG_9  (*(IO_REG32 (CFS_BASE + 36))) // /**< (r)/(w): CFS register 9, user-defined */
579 47 zero_gravi 
/** custom CFS register 10 */
580 60 zero_gravi 
#define CFS_REG_10 (*(IO_REG32 (CFS_BASE + 40))) // /**< (r)/(w): CFS register 10, user-defined */
581 47 zero_gravi 
/** custom CFS register 11 */
582 60 zero_gravi 
#define CFS_REG_11 (*(IO_REG32 (CFS_BASE + 44))) // /**< (r)/(w): CFS register 11, user-defined */
583 47 zero_gravi 
/** custom CFS register 12 */
584 60 zero_gravi 
#define CFS_REG_12 (*(IO_REG32 (CFS_BASE + 48))) // /**< (r)/(w): CFS register 12, user-defined */
585 47 zero_gravi 
/** custom CFS register 13 */
586 60 zero_gravi 
#define CFS_REG_13 (*(IO_REG32 (CFS_BASE + 52))) // /**< (r)/(w): CFS register 13, user-defined */
587 47 zero_gravi 
/** custom CFS register 14 */
588 60 zero_gravi 
#define CFS_REG_14 (*(IO_REG32 (CFS_BASE + 56))) // /**< (r)/(w): CFS register 14, user-defined */
589 47 zero_gravi 
/** custom CFS register 15 */
590 60 zero_gravi 
#define CFS_REG_15 (*(IO_REG32 (CFS_BASE + 60))) // /**< (r)/(w): CFS register 15, user-defined */
591 47 zero_gravi 
/** custom CFS register 16 */
592 60 zero_gravi 
#define CFS_REG_16 (*(IO_REG32 (CFS_BASE + 64))) // /**< (r)/(w): CFS register 16, user-defined */
593 47 zero_gravi 
/** custom CFS register 17 */
594 60 zero_gravi 
#define CFS_REG_17 (*(IO_REG32 (CFS_BASE + 68))) // /**< (r)/(w): CFS register 17, user-defined */
595 47 zero_gravi 
/** custom CFS register 18 */
596 60 zero_gravi 
#define CFS_REG_18 (*(IO_REG32 (CFS_BASE + 72))) // /**< (r)/(w): CFS register 18, user-defined */
597 47 zero_gravi 
/** custom CFS register 19 */
598 60 zero_gravi 
#define CFS_REG_19 (*(IO_REG32 (CFS_BASE + 76))) // /**< (r)/(w): CFS register 19, user-defined */
599 47 zero_gravi 
/** custom CFS register 20 */
600 60 zero_gravi 
#define CFS_REG_20 (*(IO_REG32 (CFS_BASE + 80))) // /**< (r)/(w): CFS register 20, user-defined */
601 47 zero_gravi 
/** custom CFS register 21 */
602 60 zero_gravi 
#define CFS_REG_21 (*(IO_REG32 (CFS_BASE + 84))) // /**< (r)/(w): CFS register 21, user-defined */
603 47 zero_gravi 
/** custom CFS register 22 */
604 60 zero_gravi 
#define CFS_REG_22 (*(IO_REG32 (CFS_BASE + 88))) // /**< (r)/(w): CFS register 22, user-defined */
605 47 zero_gravi 
/** custom CFS register 23 */
606 60 zero_gravi 
#define CFS_REG_23 (*(IO_REG32 (CFS_BASE + 92))) // /**< (r)/(w): CFS register 23, user-defined */
607 47 zero_gravi 
/** custom CFS register 24 */
608 60 zero_gravi 
#define CFS_REG_24 (*(IO_REG32 (CFS_BASE + 96))) // /**< (r)/(w): CFS register 24, user-defined */
609 47 zero_gravi 
/** custom CFS register 25 */
610 60 zero_gravi 
#define CFS_REG_25 (*(IO_REG32 (CFS_BASE + 100))) // /**< (r)/(w): CFS register 25, user-defined */
611 47 zero_gravi 
/** custom CFS register 26 */
612 60 zero_gravi 
#define CFS_REG_26 (*(IO_REG32 (CFS_BASE + 104))) // /**< (r)/(w): CFS register 26, user-defined */
613 47 zero_gravi 
/** custom CFS register 27 */
614 60 zero_gravi 
#define CFS_REG_27 (*(IO_REG32 (CFS_BASE + 108))) // /**< (r)/(w): CFS register 27, user-defined */
615 47 zero_gravi 
/** custom CFS register 28 */
616 60 zero_gravi 
#define CFS_REG_28 (*(IO_REG32 (CFS_BASE + 112))) // /**< (r)/(w): CFS register 28, user-defined */
617 47 zero_gravi 
/** custom CFS register 29 */
618 60 zero_gravi 
#define CFS_REG_29 (*(IO_REG32 (CFS_BASE + 116))) // /**< (r)/(w): CFS register 29, user-defined */
619 47 zero_gravi 
/** custom CFS register 30 */
620 60 zero_gravi 
#define CFS_REG_30 (*(IO_REG32 (CFS_BASE + 120))) // /**< (r)/(w): CFS register 30, user-defined */
621 47 zero_gravi 
/** custom CFS register 31 */
622 60 zero_gravi 
#define CFS_REG_31 (*(IO_REG32 (CFS_BASE + 124))) // /**< (r)/(w): CFS register 31, user-defined */
623 47 zero_gravi 
/**@}*/
624 
 
625 
 
626 
/**********************************************************************//**
627 60 zero_gravi 
 * @name IO Device: Pulse Width Modulation Controller (PWM)
628 
 **************************************************************************/
629 
/**@{*/
630 
/** PWM base address */
631 61 zero_gravi 
#define PWM_BASE (0xFFFFFE80UL) // /**< PWM base address */
632 60 zero_gravi 
/** PWM address space size in bytes */
633 
#define PWM_SIZE (16*4) // /**< PWM address space size in bytes */
634 
 
635 
/** PWM control register (r/w) */
636 
#define PWM_CT     (*(IO_REG32 (PWM_BASE + 0))) // r/w: control register
637 
/** PWM duty cycle register 0 (r/w) */
638 
#define PWM_DUTY0  (*(IO_REG32 (PWM_BASE + 4))) // r/w: duty cycle channel 3:0
639 
/** PWM duty cycle register 1 (r/w) */
640 
#define PWM_DUTY1  (*(IO_REG32 (PWM_BASE + 8))) // r/w: duty cycle channel 7:4
641 
/** PWM duty cycle register 2 (r/w) */
642 
#define PWM_DUTY2  (*(IO_REG32 (PWM_BASE + 12))) // r/w: duty cycle channel 11:8
643 
/** PWM duty cycle register 3 (r/w) */
644 
#define PWM_DUTY3  (*(IO_REG32 (PWM_BASE + 16))) // r/w: duty cycle channel 15:12
645 
/** PWM duty cycle register 4 (r/w) */
646 
#define PWM_DUTY4  (*(IO_REG32 (PWM_BASE + 20))) // r/w: duty cycle channel 19:16
647 
/** PWM duty cycle register 5 (r/w) */
648 
#define PWM_DUTY5  (*(IO_REG32 (PWM_BASE + 24))) // r/w: duty cycle channel 23:20
649 
/** PWM duty cycle register 6 (r/w) */
650 
#define PWM_DUTY6  (*(IO_REG32 (PWM_BASE + 28))) // r/w: duty cycle channel 27:24
651 
/** PWM duty cycle register 7 (r/w) */
652 
#define PWM_DUTY7  (*(IO_REG32 (PWM_BASE + 32))) // r/w: duty cycle channel 31:28
653 
/** PWM duty cycle register 8 (r/w) */
654 
#define PWM_DUTY8  (*(IO_REG32 (PWM_BASE + 36))) // r/w: duty cycle channel 35:32
655 
/** PWM duty cycle register 9 (r/w) */
656 
#define PWM_DUTY9  (*(IO_REG32 (PWM_BASE + 40))) // r/w: duty cycle channel 39:36
657 
/** PWM duty cycle register 10 (r/w) */
658 
#define PWM_DUTY10 (*(IO_REG32 (PWM_BASE + 44))) // r/w: duty cycle channel 43:40
659 
/** PWM duty cycle register 11 (r/w) */
660 
#define PWM_DUTY11 (*(IO_REG32 (PWM_BASE + 48))) // r/w: duty cycle channel 47:44
661 
/** PWM duty cycle register 12 (r/w) */
662 
#define PWM_DUTY12 (*(IO_REG32 (PWM_BASE + 52))) // r/w: duty cycle channel 51:48
663 
/** PWM duty cycle register 13 (r/w) */
664 
#define PWM_DUTY13 (*(IO_REG32 (PWM_BASE + 56))) // r/w: duty cycle channel 55:52
665 
/** PWM duty cycle register 14 (r/w) */
666 
#define PWM_DUTY14 (*(IO_REG32 (PWM_BASE + 60))) // r/w: duty cycle channel 59:56
667 
 
668 
/** PWM control register bits */
669 
enum NEORV32_PWM_CT_enum {
670 
  PWM_CT_EN    =  0, /**< PWM control register(0) (r/w): PWM controller enable */
671 
  PWM_CT_PRSC0 =  1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
672 
  PWM_CT_PRSC1 =  2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
673 
  PWM_CT_PRSC2 =  3  /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
674 
};
675 
/**@}*/
676 
 
677 
 
678 
/**********************************************************************//**
679 61 zero_gravi 
 * @name IO Device: Stream link interface (SLINK)
680 2 zero_gravi 
 **************************************************************************/
681 
/**@{*/
682 61 zero_gravi 
/** SLINK base address */
683 
#define SLINK_BASE (0xFFFFFEC0UL) // /**< SLINK base address */
684 
/** SLINK address space size in bytes */
685 
#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */
686 60 zero_gravi 
 
687 61 zero_gravi 
/** SLINK control register (r/w) */
688 
#define SLINK_CT  (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register
689 
/** stream link 0 (r/w) */
690 
#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0
691 
/** stream link 1 (r/w) */
692 
#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1
693 
/** stream link 2 (r/w) */
694 
#define SLINK_CH2 (*(IO_REG32 (SLINK_BASE + 32 + 8))) // r/w: link 2
695 
/** stream link 3 (r/w) */
696 
#define SLINK_CH3 (*(IO_REG32 (SLINK_BASE + 32 + 12))) // r/w: link 3
697 
/** stream link 4 (r/w) */
698 
#define SLINK_CH4 (*(IO_REG32 (SLINK_BASE + 32 + 16))) // r/w: link 4
699 
/** stream link 5 (r/w) */
700 
#define SLINK_CH5 (*(IO_REG32 (SLINK_BASE + 32 + 20))) // r/w: link 5
701 
/** stream link 6 (r/w) */
702 
#define SLINK_CH6 (*(IO_REG32 (SLINK_BASE + 32 + 24))) // r/w: link 6
703 
/** stream link 7 (r/w) */
704 
#define SLINK_CH7 (*(IO_REG32 (SLINK_BASE + 32 + 28))) // r/w: link 7
705 2 zero_gravi 
 
706 61 zero_gravi 
/** SLINK control register bits */
707 
enum NEORV32_SLINK_CT_enum {
708 
  SLINK_CT_RX0_AVAIL  =  0, /**< SLINK control register(0) (r/-): RX link 0 data available */
709 
  SLINK_CT_RX1_AVAIL  =  1, /**< SLINK control register(1) (r/-): RX link 1 data available */
710 
  SLINK_CT_RX2_AVAIL  =  2, /**< SLINK control register(2) (r/-): RX link 2 data available */
711 
  SLINK_CT_RX3_AVAIL  =  3, /**< SLINK control register(3) (r/-): RX link 3 data available */
712 
  SLINK_CT_RX4_AVAIL  =  4, /**< SLINK control register(4) (r/-): RX link 4 data available */
713 
  SLINK_CT_RX5_AVAIL  =  5, /**< SLINK control register(5) (r/-): RX link 5 data available */
714 
  SLINK_CT_RX6_AVAIL  =  6, /**< SLINK control register(6) (r/-): RX link 6 data available */
715 
  SLINK_CT_RX7_AVAIL  =  7, /**< SLINK control register(7) (r/-): RX link 7 data available */
716 2 zero_gravi 
 
717 61 zero_gravi 
  SLINK_CT_TX0_FREE   =  8, /**< SLINK control register(8)  (r/-): RT link 0 ready to send */
718 
  SLINK_CT_TX1_FREE   =  9, /**< SLINK control register(9)  (r/-): RT link 1 ready to send */
719 
  SLINK_CT_TX2_FREE   = 10, /**< SLINK control register(10) (r/-): RT link 2 ready to send */
720 
  SLINK_CT_TX3_FREE   = 11, /**< SLINK control register(11) (r/-): RT link 3 ready to send */
721 
  SLINK_CT_TX4_FREE   = 12, /**< SLINK control register(12) (r/-): RT link 4 ready to send */
722 
  SLINK_CT_TX5_FREE   = 13, /**< SLINK control register(13) (r/-): RT link 5 ready to send */
723 
  SLINK_CT_TX6_FREE   = 14, /**< SLINK control register(14) (r/-): RT link 6 ready to send */
724 
  SLINK_CT_TX7_FREE   = 15, /**< SLINK control register(15) (r/-): RT link 7 ready to send */
725 60 zero_gravi 
 
726 61 zero_gravi 
  SLINK_CT_RX_NUM0    = 16, /**< SLINK control register(16) (r/-): number of implemented RX links -1 bit 0 */
727 
  SLINK_CT_RX_NUM1    = 17, /**< SLINK control register(17) (r/-): number of implemented RX links -1 bit 1 */
728 
  SLINK_CT_RX_NUM2    = 18, /**< SLINK control register(18) (r/-): number of implemented RX links -1 bit 2 */
729 30 zero_gravi 
 
730 61 zero_gravi 
  SLINK_CT_TX_NUM0    = 19, /**< SLINK control register(19) (r/-): number of implemented TX links -1bit 0 */
731 
  SLINK_CT_TX_NUM1    = 20, /**< SLINK control register(20) (r/-): number of implemented TX links -1bit 1 */
732 
  SLINK_CT_TX_NUM2    = 21, /**< SLINK control register(21) (r/-): number of implemented TX links -1bit 2 */
733 47 zero_gravi 
 
734 61 zero_gravi 
  SLINK_CT_RX_FIFO_S0 = 22, /**< SLINK control register(22) (r/-): log2(RX FIFO size) bit 0 */
735 
  SLINK_CT_RX_FIFO_S1 = 23, /**< SLINK control register(23) (r/-): log2(RX FIFO size) bit 1 */
736 
  SLINK_CT_RX_FIFO_S2 = 24, /**< SLINK control register(24) (r/-): log2(RX FIFO size) bit 2 */
737 
  SLINK_CT_RX_FIFO_S3 = 25, /**< SLINK control register(25) (r/-): log2(RX FIFO size) bit 3 */
738 
 
739 
  SLINK_CT_TX_FIFO_S0 = 26, /**< SLINK control register(26) (r/-): log2(TX FIFO size) bit 0 */
740 
  SLINK_CT_TX_FIFO_S1 = 27, /**< SLINK control register(27) (r/-): log2(TX FIFO size) bit 1 */
741 
  SLINK_CT_TX_FIFO_S2 = 28, /**< SLINK control register(28) (r/-): log2(TX FIFO size) bit 2 */
742 
  SLINK_CT_TX_FIFO_S3 = 29, /**< SLINK control register(29) (r/-): log2(TX FIFO size) bit 3 */
743 
 
744 
  SLINK_CT_EN         = 31  /**< SLINK control register(31) (r/w): SLINK controller enable */
745 30 zero_gravi 
};
746 18 zero_gravi 
/**@}*/
747 
 
748 
 
749 
/**********************************************************************//**
750 61 zero_gravi 
 * @name IO Device: External Interrupt Controller (XIRQ)
751 2 zero_gravi 
 **************************************************************************/
752 
/**@{*/
753 61 zero_gravi 
/** XIRQ base address */
754 
#define XIRQ_BASE (0xFFFFFF80UL) // /**< XIRQ base address */
755 
/** XIRQ address space size in bytes */
756 
#define XIRQ_SIZE (4*4) // /**< XIRQ address space size in bytes */
757 60 zero_gravi 
 
758 61 zero_gravi 
/** XIRQ IRQ input enable register (r/w) */
759 
#define XIRQ_IER (*(IO_REG32 (XIRQ_BASE + 0)))
760 
/** XIRQ pending IRQ register /ack/clear (r/w) */
761 
#define XIRQ_IPR (*(IO_REG32 (XIRQ_BASE + 4)))
762 
/** EXTIRW  (time compare register) low word (r/w) */
763 
#define XIRQ_SCR (*(IO_REG32 (XIRQ_BASE + 8)))
764 
// reserved
765 
//#define XIRQ_reserved (*(IO_REG32 (XIRQ_BASE + 12)))
766 2 zero_gravi 
/**@}*/
767 
 
768 
 
769 
/**********************************************************************//**
770 
 * @name IO Device: Machine System Timer (MTIME)
771 
 **************************************************************************/
772 
/**@{*/
773 60 zero_gravi 
/** MTIME base address */
774 
#define MTIME_BASE (0xFFFFFF90UL) // /**< MTIME base address */
775 
/** MTIME address space size in bytes */
776 
#define MTIME_SIZE (4*4) // /**< MTIME address space size in bytes */
777 
 
778 11 zero_gravi 
/** MTIME (time register) low word (r/w) */
779 60 zero_gravi 
#define MTIME_LO     (*(IO_REG32 (MTIME_BASE + 0)))
780 11 zero_gravi 
/** MTIME (time register) high word (r/w) */
781 60 zero_gravi 
#define MTIME_HI     (*(IO_REG32 (MTIME_BASE + 4)))
782 2 zero_gravi 
/** MTIMECMP (time compare register) low word (r/w) */
783 60 zero_gravi 
#define MTIMECMP_LO  (*(IO_REG32 (MTIME_BASE + 8)))
784 2 zero_gravi 
/** MTIMECMP (time register) high word (r/w) */
785 60 zero_gravi 
#define MTIMECMP_HI  (*(IO_REG32 (MTIME_BASE + 12)))
786 2 zero_gravi 
 
787 11 zero_gravi 
/** MTIME (time register) 64-bit access (r/w) */
788 
#define MTIME        (*(IO_REG64 (&MTIME_LO)))
789 2 zero_gravi 
/** MTIMECMP (time compare register) low word (r/w) */
790 
#define MTIMECMP     (*(IO_REG64 (&MTIMECMP_LO)))
791 
/**@}*/
792 
 
793 
 
794 
/**********************************************************************//**
795 50 zero_gravi 
 * @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
796 2 zero_gravi 
 **************************************************************************/
797 
/**@{*/
798 60 zero_gravi 
/** UART0 base address */
799 
#define UART0_BASE (0xFFFFFFA0UL) // /**< UART0 base address */
800 
/** UART0 address space size in bytes */
801 
#define UART0_SIZE (2*4) // /**< UART0 address space size in bytes */
802 
 
803 50 zero_gravi 
/** UART0 control register (r/w) */
804 60 zero_gravi 
#define UART0_CT   (*(IO_REG32 (UART0_BASE + 0)))
805 50 zero_gravi 
/** UART0 receive/transmit data register (r/w) */
806 60 zero_gravi 
#define UART0_DATA (*(IO_REG32 (UART0_BASE + 4)))
807 2 zero_gravi 
 
808 60 zero_gravi 
 
809 
/** UART1 base address */
810 
#define UART1_BASE (0xFFFFFFD0UL) // /**< UART1 base address */
811 
/** UART1 address space size in bytes */
812 
#define UART1_SIZE (2*4) // /**< UART1 address space size in bytes */
813 
 
814 50 zero_gravi 
/** UART1 control register (r/w) */
815 60 zero_gravi 
#define UART1_CT   (*(IO_REG32 (UART1_BASE + 0)))
816 50 zero_gravi 
/** UART1 receive/transmit data register (r/w) */
817 60 zero_gravi 
#define UART1_DATA (*(IO_REG32 (UART1_BASE + 4)))
818 50 zero_gravi 
 
819 
/** UART0/UART1 control register bits */
820 2 zero_gravi 
enum NEORV32_UART_CT_enum {
821 50 zero_gravi 
  UART_CT_BAUD00   =  0, /**< UART control register(0)  (r/w): BAUD rate config value lsb (12-bit, bit 0) */
822 
  UART_CT_BAUD01   =  1, /**< UART control register(1)  (r/w): BAUD rate config value (12-bit, bit 1) */
823 
  UART_CT_BAUD02   =  2, /**< UART control register(2)  (r/w): BAUD rate config value (12-bit, bit 2) */
824 
  UART_CT_BAUD03   =  3, /**< UART control register(3)  (r/w): BAUD rate config value (12-bit, bit 3) */
825 
  UART_CT_BAUD04   =  4, /**< UART control register(4)  (r/w): BAUD rate config value (12-bit, bit 4) */
826 
  UART_CT_BAUD05   =  5, /**< UART control register(5)  (r/w): BAUD rate config value (12-bit, bit 4) */
827 
  UART_CT_BAUD06   =  6, /**< UART control register(6)  (r/w): BAUD rate config value (12-bit, bit 5) */
828 
  UART_CT_BAUD07   =  7, /**< UART control register(7)  (r/w): BAUD rate config value (12-bit, bit 6) */
829 
  UART_CT_BAUD08   =  8, /**< UART control register(8)  (r/w): BAUD rate config value (12-bit, bit 7) */
830 
  UART_CT_BAUD09   =  9, /**< UART control register(9)  (r/w): BAUD rate config value (12-bit, bit 8) */
831 
  UART_CT_BAUD10   = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */
832 
  UART_CT_BAUD11   = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */
833 30 zero_gravi 
  UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
834 
 
835 51 zero_gravi 
  UART_CT_RTS_EN   = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */
836 
  UART_CT_CTS_EN   = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */
837 42 zero_gravi 
  UART_CT_PMODE0   = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */
838 
  UART_CT_PMODE1   = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */
839 30 zero_gravi 
  UART_CT_PRSC0    = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
840 
  UART_CT_PRSC1    = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
841 
  UART_CT_PRSC2    = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
842 51 zero_gravi 
  UART_CT_CTS      = 27, /**< UART control register(27) (r/-): current state of CTS input */
843 
  UART_CT_EN       = 28, /**< UART control register(28) (r/w): UART global enable */
844 42 zero_gravi 
 
845 30 zero_gravi 
  UART_CT_TX_BUSY  = 31  /**< UART control register(31) (r/-): Transmitter is busy when set */
846 2 zero_gravi 
};
847 
 
848 51 zero_gravi 
/** UART0/UART1 parity configuration */
849 
enum NEORV32_UART_PARITY_enum {
850 
  PARITY_NONE = 0b00, /**< 0b00: No parity bit at all */
851 
  PARITY_EVEN = 0b10, /**< 0b10: Even parity */
852 
  PARITY_ODD  = 0b11  /**< 0b11: Odd parity */
853 
};
854 
 
855 
/** UART0/UART1 hardware flow control configuration */
856 
enum NEORV32_UART_FLOW_CONTROL_enum {
857 
  FLOW_CONTROL_NONE   = 0b00, /**< 0b00: No hardware flow control */
858 
  FLOW_CONTROL_RTS    = 0b01, /**< 0b01: Assert RTS output if UART.RX is ready to receive */
859 
  FLOW_CONTROL_CTS    = 0b10, /**< 0b10: UART.TX starts sending only if CTS input is asserted */
860 
  FLOW_CONTROL_RTSCTS = 0b11  /**< 0b11: Assert RTS output if UART.RX is ready to receive & UART.TX starts sending only if CTS input is asserted */
861 
};
862 
 
863 50 zero_gravi 
/** UART0/UART1 receive/transmit data register bits */
864 2 zero_gravi 
enum NEORV32_UART_DATA_enum {
865 
  UART_DATA_LSB   =  0, /**< UART receive/transmit data register(0)  (r/w): Receive/transmit data LSB (bit 0) */
866 
  UART_DATA_MSB   =  7, /**< UART receive/transmit data register(7)  (r/w): Receive/transmit data MSB (bit 7) */
867 47 zero_gravi 
 
868 42 zero_gravi 
  UART_DATA_PERR  = 28, /**< UART receive/transmit data register(18) (r/-): RX parity error detected when set */
869 
  UART_DATA_FERR  = 29, /**< UART receive/transmit data register(29) (r/-): RX frame error (not valid stop bit) wdetected when set */
870 
  UART_DATA_OVERR = 30, /**< UART receive/transmit data register(30) (r/-): RX data overrun when set */
871 
  UART_DATA_AVAIL = 31  /**< UART receive/transmit data register(31) (r/-): RX data available when set  */
872 2 zero_gravi 
};
873 
/**@}*/
874 
 
875 
 
876 
/**********************************************************************//**
877 10 zero_gravi 
 * @name IO Device: Serial Peripheral Interface Controller (SPI)
878 2 zero_gravi 
 **************************************************************************/
879 
/**@{*/
880 60 zero_gravi 
/** SPI base address */
881 
#define SPI_BASE (0xFFFFFFA8UL) // /**< SPI base address */
882 
/** SPI address space size in bytes */
883 
#define SPI_SIZE (2*4) // /**< SPI address space size in bytes */
884 
 
885 2 zero_gravi 
/** SPI control register (r/w) */
886 60 zero_gravi 
#define SPI_CT  (*(IO_REG32 (SPI_BASE + 0)))
887 2 zero_gravi 
/** SPI receive/transmit data register (r/w) */
888 60 zero_gravi 
#define SPI_DATA (*(IO_REG32 (SPI_BASE + 4)))
889 2 zero_gravi 
 
890 
/** SPI control register bits */
891 
enum NEORV32_SPI_CT_enum {
892 51 zero_gravi 
  SPI_CT_CS0    =  0, /**< UART control register(0)  (r/w): Direct chip select line 0 (output is low when set) */
893 
  SPI_CT_CS1    =  1, /**< UART control register(1)  (r/w): Direct chip select line 1 (output is low when set) */
894 
  SPI_CT_CS2    =  2, /**< UART control register(2)  (r/w): Direct chip select line 2 (output is low when set) */
895 
  SPI_CT_CS3    =  3, /**< UART control register(3)  (r/w): Direct chip select line 3 (output is low when set) */
896 
  SPI_CT_CS4    =  4, /**< UART control register(4)  (r/w): Direct chip select line 4 (output is low when set) */
897 
  SPI_CT_CS5    =  5, /**< UART control register(5)  (r/w): Direct chip select line 5 (output is low when set) */
898 
  SPI_CT_CS6    =  6, /**< UART control register(6)  (r/w): Direct chip select line 6 (output is low when set) */
899 
  SPI_CT_CS7    =  7, /**< UART control register(7)  (r/w): Direct chip select line 7 (output is low when set) */
900 
  SPI_CT_EN     =  8, /**< UART control register(8)  (r/w): SPI unit enable */
901 
  SPI_CT_CPHA   =  9, /**< UART control register(9)  (r/w): Clock polarity (idle polarity) */
902 2 zero_gravi 
  SPI_CT_PRSC0  = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */
903 
  SPI_CT_PRSC1  = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */
904 
  SPI_CT_PRSC2  = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */
905 36 zero_gravi 
  SPI_CT_SIZE0  = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
906 
  SPI_CT_SIZE1  = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
907 2 zero_gravi 
 
908 
  SPI_CT_BUSY   = 31  /**< UART control register(31) (r/-): SPI busy flag */
909 
};
910 
/**@}*/
911 
 
912 
 
913 
/**********************************************************************//**
914 10 zero_gravi 
 * @name IO Device: Two-Wire Interface Controller (TWI)
915 2 zero_gravi 
 **************************************************************************/
916 
/**@{*/
917 60 zero_gravi 
/** TWI base address */
918 
#define TWI_BASE (0xFFFFFFB0UL) // /**< TWI base address */
919 
/** TWI address space size in bytes */
920 
#define TWI_SIZE (2*4) // /**< TWI address space size in bytes */
921 
 
922 2 zero_gravi 
/** TWI control register (r/w) */
923 60 zero_gravi 
#define TWI_CT   (*(IO_REG32 (TWI_BASE + 0)))
924 2 zero_gravi 
/** TWI receive/transmit data register (r/w) */
925 60 zero_gravi 
#define TWI_DATA (*(IO_REG32 (TWI_BASE + 4)))
926 2 zero_gravi 
 
927 
/** TWI control register bits */
928 
enum NEORV32_TWI_CT_enum {
929 
  TWI_CT_EN     =  0, /**< TWI control register(0) (r/w): TWI enable */
930 
  TWI_CT_START  =  1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
931 
  TWI_CT_STOP   =  2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
932 48 zero_gravi 
  TWI_CT_PRSC0  =  3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */
933 
  TWI_CT_PRSC1  =  4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */
934 
  TWI_CT_PRSC2  =  5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */
935 
  TWI_CT_MACK   =  6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */
936 
  TWI_CT_CKSTEN =  7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */
937 2 zero_gravi 
 
938 
  TWI_CT_ACK    = 30, /**< TWI control register(30) (r/-): ACK received when set */
939 
  TWI_CT_BUSY   = 31  /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
940 
};
941 
 
942 
/** WTD receive/transmit data register bits */
943 
enum NEORV32_TWI_DATA_enum {
944 
  TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
945 
  TWI_DATA_MSB = 7  /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
946 
};
947 
/**@}*/
948 
 
949 
 
950 
/**********************************************************************//**
951 61 zero_gravi 
 * @name IO Device: True Random Number Generator (TRNG)
952 2 zero_gravi 
 **************************************************************************/
953 
/**@{*/
954 61 zero_gravi 
/** TRNG base address */
955 
#define TRNG_BASE (0xFFFFFFB8UL) // /**< TRNG base address */
956 
/** TRNG address space size in bytes */
957 
#define TRNG_SIZE (1*4) // /**< TRNG address space size in bytes */
958 2 zero_gravi 
 
959 61 zero_gravi 
/** TRNG control/data register (r/w) */
960 
#define TRNG_CT (*(IO_REG32 (TRNG_BASE + 0)))
961 49 zero_gravi 
 
962 61 zero_gravi 
/** TRNG control/data register bits */
963 
enum NEORV32_TRNG_CT_enum {
964 
  TRNG_CT_DATA_LSB =  0, /**< TRNG data/control register(0)  (r/-): Random data byte LSB */
965 
  TRNG_CT_DATA_MSB =  7, /**< TRNG data/control register(7)  (r/-): Random data byte MSB */
966 
 
967 
  TRNG_CT_EN       = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
968 
  TRNG_CT_VALID    = 31  /**< TRNG data/control register(31) (r/-): Random data output valid */
969 49 zero_gravi 
};
970 61 zero_gravi 
/**@}*/
971 49 zero_gravi 
 
972 61 zero_gravi 
 
973 
/**********************************************************************//**
974 
 * @name IO Device: Watchdog Timer (WDT)
975 
 **************************************************************************/
976 
/**@{*/
977 
/** WDT base address */
978 
#define WDT_BASE (0xFFFFFFBCUL) // /**< WDT base address */
979 
/** WDT address space size in bytes */
980 
#define WDT_SIZE (1*4) // /**< WDT address space size in bytes */
981 
 
982 
/** Watchdog control register (r/w) */
983 
#define WDT_CT (*(IO_REG32 (WDT_BASE + 0)))
984 
 
985 
/** WTD control register bits */
986 
enum NEORV32_WDT_CT_enum {
987 
  WDT_CT_EN       = 0, /**< WDT control register(0) (r/w): Watchdog enable */
988 
  WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */
989 
  WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */
990 
  WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */
991 
  WDT_CT_MODE     = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */
992 
  WDT_CT_RCAUSE   = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
993 
  WDT_CT_RESET    = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */
994 
  WDT_CT_FORCE    = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */
995 
  WDT_CT_LOCK     = 8  /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */
996 
};
997 49 zero_gravi 
/**@}*/
998 
 
999 
 
1000 
/**********************************************************************//**
1001 61 zero_gravi 
 * @name IO Device: General Purpose Input/Output Port Unit (GPIO)
1002 
 **************************************************************************/
1003 
/**@{*/
1004 
/** GPIO base address */
1005 
#define GPIO_BASE (0xFFFFFFC0UL) // /**< GPIO base address */
1006 
/** GPIO address space size in bytes */
1007 
#define GPIO_SIZE (4*4) // /**< GPIO address space size in bytes */
1008 
 
1009 
/** GPIO parallel input port lower 32-bit (r/-) */
1010 
#define GPIO_INPUT_LO  (*(IO_REG32 (GPIO_BASE +  0)))
1011 
/** GPIO parallel input port upper 32-bit (r/-) */
1012 
#define GPIO_INPUT_HI  (*(IO_REG32 (GPIO_BASE +  4)))
1013 
/** GPIO parallel output port lower 32-bit (r/w) */
1014 
#define GPIO_OUTPUT_LO (*(IO_REG32 (GPIO_BASE +  8)))
1015 
/** GPIO parallel output port upper 32-bit (r/w) */
1016 
#define GPIO_OUTPUT_HI (*(IO_REG32 (GPIO_BASE + 12)))
1017 
 
1018 
/** GPIO parallel input 64-bit access (r/-) */
1019 
#define GPIO_INPUT   (*(IO_REG64 (&GPIO_INPUT_LO)))
1020 
/** GPIO parallel output 64-bit access (r/w) */
1021 
#define GPIO_OUTPUT (*(IO_REG64 (&GPIO_OUTPUT_LO)))
1022 
/**@}*/
1023 
 
1024 
 
1025 
/**********************************************************************//**
1026 52 zero_gravi 
 * @name IO Device: Smart LED Hardware Interface (NEOLED)
1027 
 **************************************************************************/
1028 
/**@{*/
1029 60 zero_gravi 
/** NEOLED base address */
1030 
#define NEOLED_BASE (0xFFFFFFD8UL) // /**< NEOLED base address */
1031 
/** NEOLED address space size in bytes */
1032 
#define NEOLED_SIZE (2*4) // /**< NEOLED address space size in bytes */
1033 
 
1034 52 zero_gravi 
/** NEOLED control register (r/w) */
1035 60 zero_gravi 
#define NEOLED_CT   (*(IO_REG32 (NEOLED_BASE + 0))) // r/w: control register
1036 52 zero_gravi 
/** NEOLED TX data register (-/w) */
1037 60 zero_gravi 
#define NEOLED_DATA (*(IO_REG32 (NEOLED_BASE + 4))) // -/w: TX data register
1038 52 zero_gravi 
 
1039 
/** NEOLED control register bits */
1040 
enum NEORV32_NEOLED_CT_enum {
1041 
  NEOLED_CT_EN         =  0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
1042 
  NEOLED_CT_MODE       =  1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
1043 
  NEOLED_CT_BSCON      =  2, /**< NEOLED control register(2) (r/w): buffer status configuration -> busy_flag/IRQ config (0=at least one free entry, 1=whole buffer empty) */
1044 
  NEOLED_CT_PRSC0      =  3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
1045 
  NEOLED_CT_PRSC1      =  4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
1046 
  NEOLED_CT_PRSC2      =  5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
1047 
  //
1048 
  NEOLED_CT_BUFS_0     =  6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
1049 
  NEOLED_CT_BUFS_1     =  7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */
1050 
  NEOLED_CT_BUFS_2     =  8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */
1051 
  NEOLED_CT_BUFS_3     =  9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */
1052 
  //
1053 
  NEOLED_CT_T_TOT_0    = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */
1054 
  NEOLED_CT_T_TOT_1    = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */
1055 
  NEOLED_CT_T_TOT_2    = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */
1056 
  NEOLED_CT_T_TOT_3    = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */
1057 
  NEOLED_CT_T_TOT_4    = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */
1058 
  //
1059 
  NEOLED_CT_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */
1060 
  NEOLED_CT_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */
1061 
  NEOLED_CT_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */
1062 
  NEOLED_CT_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */
1063 
  NEOLED_CT_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */
1064 
  //
1065 
  NEOLED_CT_T_ONE_H_0  = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */
1066 
  NEOLED_CT_T_ONE_H_1  = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
1067 
  NEOLED_CT_T_ONE_H_2  = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
1068 
  NEOLED_CT_T_ONE_H_3  = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
1069 
  NEOLED_CT_T_ONE_H_4  = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
1070 
  //
1071 
  NEOLED_CT_TX_STATUS  = 30, /**< NEOLED control register(30) (r/-): serial transmit engine still busy when set */
1072 
  NEOLED_CT_BUSY       = 31  /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */
1073 
};
1074 
/**@}*/
1075 
 
1076 
 
1077 
/**********************************************************************//**
1078 12 zero_gravi 
 * @name IO Device: System Configuration Info Memory (SYSINFO)
1079 
 **************************************************************************/
1080 
/**@{*/
1081 60 zero_gravi 
/** NEOLED base address */
1082 
#define SYSINFO_BASE (0xFFFFFFE0UL) // /**< SYSINFO base address */
1083 
/** NEOLED address space size in bytes */
1084 
#define SYSINFO_SIZE (8*4) // /**< SYSINFO address space size in bytes */
1085 
 
1086 12 zero_gravi 
/** SYSINFO(0): Clock speed */
1087 60 zero_gravi 
#define SYSINFO_CLK         (*(IO_ROM32 (SYSINFO_BASE + 0)))
1088 12 zero_gravi 
/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
1089 60 zero_gravi 
#define SYSINFO_USER_CODE   (*(IO_ROM32 (SYSINFO_BASE + 4)))
1090 12 zero_gravi 
/** SYSINFO(2): Clock speed */
1091 60 zero_gravi 
#define SYSINFO_FEATURES    (*(IO_ROM32 (SYSINFO_BASE + 8)))
1092 41 zero_gravi 
/** SYSINFO(3): Cache configuration */
1093 60 zero_gravi 
#define SYSINFO_CACHE       (*(IO_ROM32 (SYSINFO_BASE + 12)))
1094 12 zero_gravi 
/** SYSINFO(4): Instruction memory address space base */
1095 60 zero_gravi 
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 16)))
1096 12 zero_gravi 
/** SYSINFO(5): Data memory address space base */
1097 60 zero_gravi 
#define SYSINFO_DSPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 20)))
1098 23 zero_gravi 
/** SYSINFO(6): Internal instruction memory (IMEM) size in bytes */
1099 60 zero_gravi 
#define SYSINFO_IMEM_SIZE   (*(IO_ROM32 (SYSINFO_BASE + 24)))
1100 23 zero_gravi 
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
1101 60 zero_gravi 
#define SYSINFO_DMEM_SIZE   (*(IO_ROM32 (SYSINFO_BASE + 28)))
1102 12 zero_gravi 
/**@}*/
1103 
 
1104 
/**********************************************************************//**
1105 
 * SYSINFO_FEATURES (r/-): Implemented processor devices/features
1106 
 **************************************************************************/
1107 
 enum NEORV32_SYSINFO_FEATURES_enum {
1108 61 zero_gravi 
  SYSINFO_FEATURES_BOOTLOADER       =  0, /**< SYSINFO_FEATURES  (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
1109 44 zero_gravi 
  SYSINFO_FEATURES_MEM_EXT          =  1, /**< SYSINFO_FEATURES  (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
1110 
  SYSINFO_FEATURES_MEM_INT_IMEM     =  2, /**< SYSINFO_FEATURES  (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
1111 61 zero_gravi 
  SYSINFO_FEATURES_MEM_INT_DMEM     =  3, /**< SYSINFO_FEATURES  (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
1112 
  SYSINFO_FEATURES_MEM_EXT_ENDIAN   =  4, /**< SYSINFO_FEATURES  (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */
1113 
  SYSINFO_FEATURES_ICACHE           =  5, /**< SYSINFO_FEATURES  (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
1114 12 zero_gravi 
 
1115 59 zero_gravi 
  SYSINFO_FEATURES_OCD              = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
1116 57 zero_gravi 
  SYSINFO_FEATURES_HW_RESET         = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
1117 
 
1118 44 zero_gravi 
  SYSINFO_FEATURES_IO_GPIO          = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
1119 
  SYSINFO_FEATURES_IO_MTIME         = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
1120 50 zero_gravi 
  SYSINFO_FEATURES_IO_UART0         = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
1121 44 zero_gravi 
  SYSINFO_FEATURES_IO_SPI           = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
1122 
  SYSINFO_FEATURES_IO_TWI           = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
1123 
  SYSINFO_FEATURES_IO_PWM           = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
1124 
  SYSINFO_FEATURES_IO_WDT           = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
1125 47 zero_gravi 
  SYSINFO_FEATURES_IO_CFS           = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
1126 49 zero_gravi 
  SYSINFO_FEATURES_IO_TRNG          = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
1127 61 zero_gravi 
  SYSINFO_FEATURES_IO_SLINK         = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */
1128 52 zero_gravi 
  SYSINFO_FEATURES_IO_UART1         = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
1129 61 zero_gravi 
  SYSINFO_FEATURES_IO_NEOLED        = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
1130 
  SYSINFO_FEATURES_IO_XIRQ          = 28  /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
1131 12 zero_gravi 
};
1132 
 
1133 41 zero_gravi 
/**********************************************************************//**
1134 
 * SYSINFO_CACHE (r/-): Cache configuration
1135 
 **************************************************************************/
1136 
 enum NEORV32_SYSINFO_CACHE_enum {
1137 
  SYSINFO_CACHE_IC_BLOCK_SIZE_0    =  0, /**< SYSINFO_CACHE  (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
1138 
  SYSINFO_CACHE_IC_BLOCK_SIZE_1    =  1, /**< SYSINFO_CACHE  (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */
1139 
  SYSINFO_CACHE_IC_BLOCK_SIZE_2    =  2, /**< SYSINFO_CACHE  (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */
1140 
  SYSINFO_CACHE_IC_BLOCK_SIZE_3    =  3, /**< SYSINFO_CACHE  (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */
1141 12 zero_gravi 
 
1142 41 zero_gravi 
  SYSINFO_CACHE_IC_NUM_BLOCKS_0    =  4, /**< SYSINFO_CACHE  (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */
1143 
  SYSINFO_CACHE_IC_NUM_BLOCKS_1    =  5, /**< SYSINFO_CACHE  (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */
1144 
  SYSINFO_CACHE_IC_NUM_BLOCKS_2    =  6, /**< SYSINFO_CACHE  (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */
1145 
  SYSINFO_CACHE_IC_NUM_BLOCKS_3    =  7, /**< SYSINFO_CACHE  (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */
1146 
 
1147 45 zero_gravi 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_0 =  8, /**< SYSINFO_CACHE  (8) (r/-): i-cache: log2(associativity), bit 0 (via ICACHE_ASSOCIATIVITY generic) */
1148 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_1 =  9, /**< SYSINFO_CACHE  (9) (r/-): i-cache: log2(associativity), bit 1 (via ICACHE_ASSOCIATIVITY generic) */
1149 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 2 (via ICACHE_ASSOCIATIVITY generic) */
1150 
  SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 3 (via ICACHE_ASSOCIATIVITY generic) */
1151 
 
1152 
  SYSINFO_CACHE_IC_REPLACEMENT_0   = 12, /**< SYSINFO_CACHE (12) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 0 */
1153 
  SYSINFO_CACHE_IC_REPLACEMENT_1   = 13, /**< SYSINFO_CACHE (13) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 1 */
1154 
  SYSINFO_CACHE_IC_REPLACEMENT_2   = 14, /**< SYSINFO_CACHE (14) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 2 */
1155 
  SYSINFO_CACHE_IC_REPLACEMENT_3   = 15, /**< SYSINFO_CACHE (15) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 3 */
1156 41 zero_gravi 
};
1157 
 
1158 
 
1159 2 zero_gravi 
// ----------------------------------------------------------------------------
1160 
// Include all IO driver headers
1161 
// ----------------------------------------------------------------------------
1162 
// cpu core
1163 
#include "neorv32_cpu.h"
1164 
 
1165 54 zero_gravi 
// intrinsics
1166 
#include "neorv32_intrinsics.h"
1167 
 
1168 2 zero_gravi 
// neorv32 runtime environment
1169 
#include "neorv32_rte.h"
1170 
 
1171 
// io/peripheral devices
1172 47 zero_gravi 
#include "neorv32_cfs.h"
1173 2 zero_gravi 
#include "neorv32_gpio.h"
1174 
#include "neorv32_mtime.h"
1175 52 zero_gravi 
#include "neorv32_neoled.h"
1176 2 zero_gravi 
#include "neorv32_pwm.h"
1177 61 zero_gravi 
#include "neorv32_slink.h"
1178 2 zero_gravi 
#include "neorv32_spi.h"
1179 
#include "neorv32_trng.h"
1180 
#include "neorv32_twi.h"
1181 
#include "neorv32_uart.h"
1182 
#include "neorv32_wdt.h"
1183 61 zero_gravi 
#include "neorv32_xirq.h"
1184 2 zero_gravi 
 
1185 61 zero_gravi 
 
1186 
#ifdef __cplusplus
1187 
}
1188 
#endif
1189 
 
1190 2 zero_gravi 
#endif // neorv32_h

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