| 1 |
2 |
zero_gravi |
// #################################################################################################
|
| 2 |
|
|
// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
|
| 3 |
|
|
// # ********************************************************************************************* #
|
| 4 |
|
|
// # BSD 3-Clause License #
|
| 5 |
|
|
// # #
|
| 6 |
|
|
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
| 7 |
|
|
// # #
|
| 8 |
|
|
// # Redistribution and use in source and binary forms, with or without modification, are #
|
| 9 |
|
|
// # permitted provided that the following conditions are met: #
|
| 10 |
|
|
// # #
|
| 11 |
|
|
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| 12 |
|
|
// # conditions and the following disclaimer. #
|
| 13 |
|
|
// # #
|
| 14 |
|
|
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
| 15 |
|
|
// # conditions and the following disclaimer in the documentation and/or other materials #
|
| 16 |
|
|
// # provided with the distribution. #
|
| 17 |
|
|
// # #
|
| 18 |
|
|
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
| 19 |
|
|
// # endorse or promote products derived from this software without specific prior written #
|
| 20 |
|
|
// # permission. #
|
| 21 |
|
|
// # #
|
| 22 |
|
|
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
| 23 |
|
|
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
| 24 |
|
|
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
| 25 |
|
|
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
| 26 |
|
|
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
| 27 |
|
|
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
| 28 |
|
|
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
| 29 |
|
|
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
| 30 |
|
|
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
| 31 |
|
|
// # ********************************************************************************************* #
|
| 32 |
|
|
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
| 33 |
|
|
// #################################################################################################
|
| 34 |
|
|
|
| 35 |
|
|
|
| 36 |
|
|
/**********************************************************************//**
|
| 37 |
|
|
* @file neorv32_cpu.c
|
| 38 |
|
|
* @author Stephan Nolting
|
| 39 |
|
|
* @brief CPU Core Functions HW driver source file.
|
| 40 |
|
|
**************************************************************************/
|
| 41 |
|
|
|
| 42 |
|
|
#include "neorv32.h"
|
| 43 |
|
|
#include "neorv32_cpu.h"
|
| 44 |
|
|
|
| 45 |
|
|
|
| 46 |
|
|
/**********************************************************************//**
|
| 47 |
|
|
* Enable specific CPU interrupt.
|
| 48 |
|
|
*
|
| 49 |
|
|
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
|
| 50 |
|
|
*
|
| 51 |
|
|
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
|
| 52 |
|
|
* return 0 if success, 1 if error (invalid irq_sel).
|
| 53 |
|
|
**************************************************************************/
|
| 54 |
|
|
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
|
| 55 |
|
|
|
| 56 |
|
|
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
|
| 57 |
|
|
return 1;
|
| 58 |
|
|
}
|
| 59 |
|
|
|
| 60 |
|
|
register uint32_t mask = (uint32_t)(1 << irq_sel);
|
| 61 |
|
|
asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
|
| 62 |
|
|
return 0;
|
| 63 |
|
|
}
|
| 64 |
|
|
|
| 65 |
|
|
|
| 66 |
|
|
/**********************************************************************//**
|
| 67 |
|
|
* Disable specific CPU interrupt.
|
| 68 |
|
|
*
|
| 69 |
|
|
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
|
| 70 |
|
|
* return 0 if success, 1 if error (invalid irq_sel).
|
| 71 |
|
|
**************************************************************************/
|
| 72 |
|
|
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
|
| 73 |
|
|
|
| 74 |
|
|
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
|
| 75 |
|
|
return 1;
|
| 76 |
|
|
}
|
| 77 |
|
|
|
| 78 |
|
|
register uint32_t mask = (uint32_t)(1 << irq_sel);
|
| 79 |
|
|
asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
|
| 80 |
|
|
return 0;
|
| 81 |
|
|
}
|
| 82 |
|
|
|
| 83 |
|
|
|
| 84 |
|
|
/**********************************************************************//**
|
| 85 |
|
|
* Simple delay function (not very precise) using busy wait.
|
| 86 |
|
|
*
|
| 87 |
|
|
* @param[in] time_ms Time in ms to wait.
|
| 88 |
|
|
**************************************************************************/
|
| 89 |
|
|
void neorv32_cpu_delay_ms(uint32_t time_ms) {
|
| 90 |
|
|
|
| 91 |
|
|
uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
|
| 92 |
|
|
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
|
| 93 |
|
|
uint32_t cnt = clock_speed * time_ms;
|
| 94 |
|
|
|
| 95 |
|
|
// one iteration = ~30 cycles
|
| 96 |
|
|
while (cnt) {
|
| 97 |
|
|
asm volatile("nop");
|
| 98 |
|
|
asm volatile("nop");
|
| 99 |
|
|
asm volatile("nop");
|
| 100 |
|
|
asm volatile("nop");
|
| 101 |
|
|
cnt--;
|
| 102 |
|
|
}
|
| 103 |
|
|
}
|
| 104 |
|
|
|
