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// #################################################################################################
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// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_cpu.c
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* @author Stephan Nolting
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* @brief CPU Core Functions HW driver source file.
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_cpu.h"
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/**********************************************************************//**
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* >Private< helper functions.
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**************************************************************************/
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static int __neorv32_cpu_irq_id_check(uint8_t irq_sel);
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static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
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static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
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/**********************************************************************//**
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* Private function: Check IRQ id.
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {
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if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
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((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) {
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return 0;
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}
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else {
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return 1;
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}
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}
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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// check IRQ id
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if (__neorv32_cpu_irq_id_check(irq_sel)) {
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return 1;
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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return 0;
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}
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/**********************************************************************//**
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* Disable specific CPU interrupt.
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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// check IRQ id
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if (__neorv32_cpu_irq_id_check(irq_sel)) {
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return 1;
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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return 0;
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}
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/**********************************************************************//**
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* Get cycle count from cycle[h].
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*
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* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
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*
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* @return Current cycle counter (64 bit).
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**************************************************************************/
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uint64_t neorv32_cpu_get_cycle(void) {
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
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tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
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tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
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tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
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if (tmp1 == tmp3) {
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break;
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}
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}
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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return cycles.uint64;
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}
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/**********************************************************************//**
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* Set mcycle[h] counter.
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*
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* @param[in] value New value for mcycle[h] CSR (64-bit).
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**************************************************************************/
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void neorv32_cpu_set_mcycle(uint64_t value) {
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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cycles.uint64 = value;
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neorv32_cpu_csr_write(CSR_MCYCLE, 0);
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neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
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neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);
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}
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/**********************************************************************//**
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* Get retired instructions counter from instret[h].
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*
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* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
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*
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* @return Current instructions counter (64 bit).
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**************************************************************************/
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uint64_t neorv32_cpu_get_instret(void) {
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
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tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
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tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
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tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
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if (tmp1 == tmp3) {
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break;
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}
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}
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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return cycles.uint64;
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}
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/**********************************************************************//**
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* Set retired instructions counter minstret[h].
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*
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* @param[in] value New value for mcycle[h] CSR (64-bit).
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**************************************************************************/
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void neorv32_cpu_set_minstret(uint64_t value) {
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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cycles.uint64 = value;
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neorv32_cpu_csr_write(CSR_MINSTRET, 0);
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neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
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neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);
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}
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/**********************************************************************//**
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* Get current system time from time[h] CSR.
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*
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* @note This function requires the MTIME system timer to be implemented.
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*
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* @return Current system time (64 bit).
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**************************************************************************/
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uint64_t neorv32_cpu_get_systime(void) {
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
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tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
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tmp2 = neorv32_cpu_csr_read(CSR_TIME);
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tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
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if (tmp1 == tmp3) {
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break;
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}
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}
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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return cycles.uint64;
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}
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/**********************************************************************//**
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zero_gravi |
* Simple delay function using busy wait.
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zero_gravi |
*
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zero_gravi |
* @warning This function requires the cycle CSR(s). Hence, the Zicsr extension is mandatory.
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*
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* @param[in] time_ms Time in ms to wait.
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**************************************************************************/
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void neorv32_cpu_delay_ms(uint32_t time_ms) {
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zero_gravi |
uint64_t time_resume = neorv32_cpu_get_cycle();
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zero_gravi |
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zero_gravi |
uint32_t clock = SYSINFO_CLK; // clock ticks per second
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clock = clock / 1000; // clock ticks per ms
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uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
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time_resume += wait_cycles;
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while(1) {
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if (neorv32_cpu_get_cycle() >= time_resume) {
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break;
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}
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}
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| 268 |
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}
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zero_gravi |
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/**********************************************************************//**
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* Switch from privilege mode MACHINE to privilege mode USER.
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*
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* @warning This function requires the U extension to be implemented.
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zero_gravi |
**************************************************************************/
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
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35 |
zero_gravi |
// make sure to use NO registers in here! -> naked
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| 279 |
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asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
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"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
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"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
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"mret \n\t" // return and switch to user mode
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42 |
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: : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
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| 285 |
15 |
zero_gravi |
}
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| 286 |
39 |
zero_gravi |
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/**********************************************************************//**
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* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes).
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| 290 |
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*
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| 291 |
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* @warning This function requires the A (atomic) CPU extension.
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| 292 |
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*
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| 293 |
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* @param[in] addr Address of memory location.
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| 294 |
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* @param[in] expected Expected value (for comparison).
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| 295 |
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* @param[in] desired Desired value (new value).
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| 296 |
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* @return Returns 0 on success, 1 on failure.
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| 297 |
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**************************************************************************/
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| 298 |
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int __attribute__ ((noinline)) neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired) {
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| 299 |
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#ifdef __riscv_atomic
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| 300 |
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| 301 |
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register uint32_t addr_reg = addr;
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register uint32_t des_reg = desired;
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| 303 |
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register uint32_t tmp_reg;
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| 304 |
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// load original value + reservation (lock)
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| 306 |
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asm volatile ("lr.w %[result], (%[input])" : [result] "=r" (tmp_reg) : [input] "r" (addr_reg));
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| 307 |
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| 308 |
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if (tmp_reg != expected) {
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| 309 |
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asm volatile ("lw x0, 0(%[input])" : : [input] "r" (addr_reg)); // clear reservation lock
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| 310 |
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return 1;
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| 311 |
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}
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| 312 |
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| 313 |
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// store-conditional
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| 314 |
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asm volatile ("sc.w %[result], %[input_i], (%[input_j])" : [result] "=r" (tmp_reg) : [input_i] "r" (des_reg), [input_j] "r" (addr_reg));
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| 315 |
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| 316 |
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if (tmp_reg) {
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| 317 |
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return 1;
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| 318 |
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}
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| 319 |
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| 320 |
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return 0;
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| 321 |
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#else
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| 322 |
45 |
zero_gravi |
return 1; // A extension not implemented - function always fails
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| 323 |
39 |
zero_gravi |
#endif
|
| 324 |
|
|
}
|
| 325 |
40 |
zero_gravi |
|
| 326 |
|
|
|
| 327 |
|
|
/**********************************************************************//**
|
| 328 |
42 |
zero_gravi |
* Physical memory protection (PMP): Get number of available regions.
|
| 329 |
|
|
*
|
| 330 |
|
|
* @warning This function overrides all available PMPCFG* CSRs.
|
| 331 |
|
|
* @warning This function requires the PMP CPU extension.
|
| 332 |
|
|
*
|
| 333 |
|
|
* @return Returns number of available PMP regions.
|
| 334 |
|
|
**************************************************************************/
|
| 335 |
|
|
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
|
| 336 |
|
|
|
| 337 |
45 |
zero_gravi |
uint32_t i = 0;
|
| 338 |
|
|
|
| 339 |
42 |
zero_gravi |
// try setting R bit in all PMPCFG CSRs
|
| 340 |
45 |
zero_gravi |
const uint32_t tmp = 0x01010101;
|
| 341 |
|
|
for (i=0; i<16; i++) {
|
| 342 |
|
|
__neorv32_cpu_pmp_cfg_write(i, tmp);
|
| 343 |
|
|
}
|
| 344 |
42 |
zero_gravi |
|
| 345 |
|
|
// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
|
| 346 |
|
|
union {
|
| 347 |
|
|
uint32_t uint32;
|
| 348 |
|
|
uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];
|
| 349 |
|
|
} cnt;
|
| 350 |
|
|
|
| 351 |
|
|
cnt.uint32 = 0;
|
| 352 |
45 |
zero_gravi |
for (i=0; i<16; i++) {
|
| 353 |
|
|
cnt.uint32 += __neorv32_cpu_pmp_cfg_read(i);
|
| 354 |
|
|
}
|
| 355 |
42 |
zero_gravi |
|
| 356 |
|
|
// sum up bytes
|
| 357 |
|
|
uint32_t num_regions = 0;
|
| 358 |
|
|
num_regions += (uint32_t)cnt.uint8[0];
|
| 359 |
|
|
num_regions += (uint32_t)cnt.uint8[1];
|
| 360 |
|
|
num_regions += (uint32_t)cnt.uint8[2];
|
| 361 |
|
|
num_regions += (uint32_t)cnt.uint8[3];
|
| 362 |
|
|
|
| 363 |
|
|
return num_regions;
|
| 364 |
|
|
}
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
/**********************************************************************//**
|
| 368 |
40 |
zero_gravi |
* Physical memory protection (PMP): Get minimal region size (granularity).
|
| 369 |
|
|
*
|
| 370 |
|
|
* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
|
| 371 |
|
|
* @warning This function requires the PMP CPU extension.
|
| 372 |
|
|
*
|
| 373 |
42 |
zero_gravi |
* @return Returns minimal region size in bytes.
|
| 374 |
40 |
zero_gravi |
**************************************************************************/
|
| 375 |
|
|
uint32_t neorv32_cpu_pmp_get_granularity(void) {
|
| 376 |
|
|
|
| 377 |
|
|
// check min granulartiy
|
| 378 |
|
|
uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
|
| 379 |
|
|
tmp &= 0xffffff00; // disable entry 0
|
| 380 |
|
|
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
|
| 381 |
|
|
neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
|
| 382 |
|
|
uint32_t tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
|
| 383 |
|
|
|
| 384 |
|
|
uint32_t i;
|
| 385 |
|
|
|
| 386 |
|
|
// find least-significat set bit
|
| 387 |
|
|
for (i=31; i!=0; i--) {
|
| 388 |
|
|
if (((tmp_a >> i) & 1) == 0) {
|
| 389 |
|
|
break;
|
| 390 |
|
|
}
|
| 391 |
|
|
}
|
| 392 |
|
|
|
| 393 |
|
|
return (uint32_t)(1 << (i+1+2));
|
| 394 |
|
|
}
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
/**********************************************************************//**
|
| 398 |
|
|
* Physical memory protection (PMP): Configure region.
|
| 399 |
|
|
*
|
| 400 |
|
|
* @note Using NAPOT mode - page base address has to be naturally aligned.
|
| 401 |
|
|
*
|
| 402 |
|
|
* @warning This function requires the PMP CPU extension.
|
| 403 |
42 |
zero_gravi |
* @warning Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).
|
| 404 |
40 |
zero_gravi |
*
|
| 405 |
42 |
zero_gravi |
* @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).
|
| 406 |
40 |
zero_gravi |
* @param[in] base Region base address (has to be naturally aligned!).
|
| 407 |
|
|
* @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
|
| 408 |
|
|
* @param[in] config Region configuration (attributes) byte (for PMPCFGx).
|
| 409 |
|
|
* @return Returns 0 on success, 1 on failure.
|
| 410 |
|
|
**************************************************************************/
|
| 411 |
|
|
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
|
| 412 |
|
|
|
| 413 |
|
|
if (size < 8) {
|
| 414 |
|
|
return 1; // minimal region size is 8 bytes
|
| 415 |
|
|
}
|
| 416 |
|
|
|
| 417 |
|
|
if ((size & (size - 1)) != 0) {
|
| 418 |
|
|
return 1; // region size is not a power of two
|
| 419 |
|
|
}
|
| 420 |
|
|
|
| 421 |
45 |
zero_gravi |
// pmpcfg register index
|
| 422 |
|
|
uint32_t pmpcfg_index = index >> 4; // 4 entries per pmpcfg csr
|
| 423 |
|
|
|
| 424 |
40 |
zero_gravi |
// setup configuration
|
| 425 |
|
|
uint32_t tmp;
|
| 426 |
|
|
uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
|
| 427 |
|
|
uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
|
| 428 |
|
|
config_mask = ~config_mask;
|
| 429 |
|
|
|
| 430 |
|
|
// clear old configuration
|
| 431 |
45 |
zero_gravi |
__neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) & config_mask);
|
| 432 |
40 |
zero_gravi |
|
| 433 |
45 |
zero_gravi |
|
| 434 |
40 |
zero_gravi |
// set base address and region size
|
| 435 |
|
|
uint32_t addr_mask = ~((size - 1) >> 2);
|
| 436 |
|
|
uint32_t size_mask = (size - 1) >> 3;
|
| 437 |
|
|
|
| 438 |
|
|
tmp = base & addr_mask;
|
| 439 |
|
|
tmp = tmp | size_mask;
|
| 440 |
|
|
|
| 441 |
42 |
zero_gravi |
switch(index & 63) {
|
| 442 |
|
|
case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
|
| 443 |
|
|
case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
|
| 444 |
|
|
case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
|
| 445 |
|
|
case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
|
| 446 |
|
|
case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
|
| 447 |
|
|
case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
|
| 448 |
|
|
case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
|
| 449 |
|
|
case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
|
| 450 |
|
|
case 8: neorv32_cpu_csr_write(CSR_PMPADDR8, tmp); break;
|
| 451 |
|
|
case 9: neorv32_cpu_csr_write(CSR_PMPADDR9, tmp); break;
|
| 452 |
|
|
case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, tmp); break;
|
| 453 |
|
|
case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, tmp); break;
|
| 454 |
|
|
case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, tmp); break;
|
| 455 |
|
|
case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, tmp); break;
|
| 456 |
|
|
case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, tmp); break;
|
| 457 |
|
|
case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, tmp); break;
|
| 458 |
|
|
case 16: neorv32_cpu_csr_write(CSR_PMPADDR16, tmp); break;
|
| 459 |
|
|
case 17: neorv32_cpu_csr_write(CSR_PMPADDR17, tmp); break;
|
| 460 |
|
|
case 18: neorv32_cpu_csr_write(CSR_PMPADDR18, tmp); break;
|
| 461 |
|
|
case 19: neorv32_cpu_csr_write(CSR_PMPADDR19, tmp); break;
|
| 462 |
|
|
case 20: neorv32_cpu_csr_write(CSR_PMPADDR20, tmp); break;
|
| 463 |
|
|
case 21: neorv32_cpu_csr_write(CSR_PMPADDR21, tmp); break;
|
| 464 |
|
|
case 22: neorv32_cpu_csr_write(CSR_PMPADDR22, tmp); break;
|
| 465 |
|
|
case 23: neorv32_cpu_csr_write(CSR_PMPADDR23, tmp); break;
|
| 466 |
|
|
case 24: neorv32_cpu_csr_write(CSR_PMPADDR24, tmp); break;
|
| 467 |
|
|
case 25: neorv32_cpu_csr_write(CSR_PMPADDR25, tmp); break;
|
| 468 |
|
|
case 26: neorv32_cpu_csr_write(CSR_PMPADDR26, tmp); break;
|
| 469 |
|
|
case 27: neorv32_cpu_csr_write(CSR_PMPADDR27, tmp); break;
|
| 470 |
|
|
case 28: neorv32_cpu_csr_write(CSR_PMPADDR28, tmp); break;
|
| 471 |
|
|
case 29: neorv32_cpu_csr_write(CSR_PMPADDR29, tmp); break;
|
| 472 |
|
|
case 30: neorv32_cpu_csr_write(CSR_PMPADDR30, tmp); break;
|
| 473 |
|
|
case 31: neorv32_cpu_csr_write(CSR_PMPADDR31, tmp); break;
|
| 474 |
|
|
case 32: neorv32_cpu_csr_write(CSR_PMPADDR32, tmp); break;
|
| 475 |
|
|
case 33: neorv32_cpu_csr_write(CSR_PMPADDR33, tmp); break;
|
| 476 |
|
|
case 34: neorv32_cpu_csr_write(CSR_PMPADDR34, tmp); break;
|
| 477 |
|
|
case 35: neorv32_cpu_csr_write(CSR_PMPADDR35, tmp); break;
|
| 478 |
|
|
case 36: neorv32_cpu_csr_write(CSR_PMPADDR36, tmp); break;
|
| 479 |
|
|
case 37: neorv32_cpu_csr_write(CSR_PMPADDR37, tmp); break;
|
| 480 |
|
|
case 38: neorv32_cpu_csr_write(CSR_PMPADDR38, tmp); break;
|
| 481 |
|
|
case 39: neorv32_cpu_csr_write(CSR_PMPADDR39, tmp); break;
|
| 482 |
|
|
case 40: neorv32_cpu_csr_write(CSR_PMPADDR40, tmp); break;
|
| 483 |
|
|
case 41: neorv32_cpu_csr_write(CSR_PMPADDR41, tmp); break;
|
| 484 |
|
|
case 42: neorv32_cpu_csr_write(CSR_PMPADDR42, tmp); break;
|
| 485 |
|
|
case 43: neorv32_cpu_csr_write(CSR_PMPADDR43, tmp); break;
|
| 486 |
|
|
case 44: neorv32_cpu_csr_write(CSR_PMPADDR44, tmp); break;
|
| 487 |
|
|
case 45: neorv32_cpu_csr_write(CSR_PMPADDR45, tmp); break;
|
| 488 |
|
|
case 46: neorv32_cpu_csr_write(CSR_PMPADDR46, tmp); break;
|
| 489 |
|
|
case 47: neorv32_cpu_csr_write(CSR_PMPADDR47, tmp); break;
|
| 490 |
|
|
case 48: neorv32_cpu_csr_write(CSR_PMPADDR48, tmp); break;
|
| 491 |
|
|
case 49: neorv32_cpu_csr_write(CSR_PMPADDR49, tmp); break;
|
| 492 |
|
|
case 50: neorv32_cpu_csr_write(CSR_PMPADDR50, tmp); break;
|
| 493 |
|
|
case 51: neorv32_cpu_csr_write(CSR_PMPADDR51, tmp); break;
|
| 494 |
|
|
case 52: neorv32_cpu_csr_write(CSR_PMPADDR52, tmp); break;
|
| 495 |
|
|
case 53: neorv32_cpu_csr_write(CSR_PMPADDR53, tmp); break;
|
| 496 |
|
|
case 54: neorv32_cpu_csr_write(CSR_PMPADDR54, tmp); break;
|
| 497 |
|
|
case 55: neorv32_cpu_csr_write(CSR_PMPADDR55, tmp); break;
|
| 498 |
|
|
case 56: neorv32_cpu_csr_write(CSR_PMPADDR56, tmp); break;
|
| 499 |
|
|
case 57: neorv32_cpu_csr_write(CSR_PMPADDR57, tmp); break;
|
| 500 |
|
|
case 58: neorv32_cpu_csr_write(CSR_PMPADDR58, tmp); break;
|
| 501 |
|
|
case 59: neorv32_cpu_csr_write(CSR_PMPADDR59, tmp); break;
|
| 502 |
|
|
case 60: neorv32_cpu_csr_write(CSR_PMPADDR60, tmp); break;
|
| 503 |
|
|
case 61: neorv32_cpu_csr_write(CSR_PMPADDR61, tmp); break;
|
| 504 |
|
|
case 62: neorv32_cpu_csr_write(CSR_PMPADDR62, tmp); break;
|
| 505 |
|
|
case 63: neorv32_cpu_csr_write(CSR_PMPADDR63, tmp); break;
|
| 506 |
40 |
zero_gravi |
default: break;
|
| 507 |
|
|
}
|
| 508 |
|
|
|
| 509 |
42 |
zero_gravi |
// wait for HW to compute PMP-internal stuff (address masks)
|
| 510 |
40 |
zero_gravi |
for (tmp=0; tmp<16; tmp++) {
|
| 511 |
|
|
asm volatile ("nop");
|
| 512 |
|
|
}
|
| 513 |
|
|
|
| 514 |
|
|
// set new configuration
|
| 515 |
45 |
zero_gravi |
__neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) | config_int);
|
| 516 |
|
|
|
| 517 |
|
|
return 0;
|
| 518 |
|
|
}
|
| 519 |
|
|
|
| 520 |
|
|
|
| 521 |
|
|
/**********************************************************************//**
|
| 522 |
|
|
* Internal helper function: Read PMP configuration register 0..15
|
| 523 |
|
|
*
|
| 524 |
|
|
* @warning This function requires the PMP CPU extension.
|
| 525 |
|
|
*
|
| 526 |
|
|
* @param[in] index PMP CFG configuration register ID (0..15).
|
| 527 |
|
|
* @return PMP CFG read data.
|
| 528 |
|
|
**************************************************************************/
|
| 529 |
|
|
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index) {
|
| 530 |
|
|
|
| 531 |
|
|
uint32_t tmp = 0;
|
| 532 |
42 |
zero_gravi |
switch(index & 15) {
|
| 533 |
45 |
zero_gravi |
case 0: tmp = neorv32_cpu_csr_read(CSR_PMPCFG0); break;
|
| 534 |
|
|
case 1: tmp = neorv32_cpu_csr_read(CSR_PMPCFG1); break;
|
| 535 |
|
|
case 2: tmp = neorv32_cpu_csr_read(CSR_PMPCFG2); break;
|
| 536 |
|
|
case 3: tmp = neorv32_cpu_csr_read(CSR_PMPCFG3); break;
|
| 537 |
|
|
case 4: tmp = neorv32_cpu_csr_read(CSR_PMPCFG4); break;
|
| 538 |
|
|
case 5: tmp = neorv32_cpu_csr_read(CSR_PMPCFG5); break;
|
| 539 |
|
|
case 6: tmp = neorv32_cpu_csr_read(CSR_PMPCFG6); break;
|
| 540 |
|
|
case 7: tmp = neorv32_cpu_csr_read(CSR_PMPCFG7); break;
|
| 541 |
|
|
case 8: tmp = neorv32_cpu_csr_read(CSR_PMPCFG8); break;
|
| 542 |
|
|
case 9: tmp = neorv32_cpu_csr_read(CSR_PMPCFG9); break;
|
| 543 |
|
|
case 10: tmp = neorv32_cpu_csr_read(CSR_PMPCFG10); break;
|
| 544 |
|
|
case 11: tmp = neorv32_cpu_csr_read(CSR_PMPCFG11); break;
|
| 545 |
|
|
case 12: tmp = neorv32_cpu_csr_read(CSR_PMPCFG12); break;
|
| 546 |
|
|
case 13: tmp = neorv32_cpu_csr_read(CSR_PMPCFG13); break;
|
| 547 |
|
|
case 14: tmp = neorv32_cpu_csr_read(CSR_PMPCFG14); break;
|
| 548 |
|
|
case 15: tmp = neorv32_cpu_csr_read(CSR_PMPCFG15); break;
|
| 549 |
42 |
zero_gravi |
default: break;
|
| 550 |
40 |
zero_gravi |
}
|
| 551 |
|
|
|
| 552 |
45 |
zero_gravi |
return tmp;
|
| 553 |
40 |
zero_gravi |
}
|
| 554 |
42 |
zero_gravi |
|
| 555 |
|
|
|
| 556 |
|
|
/**********************************************************************//**
|
| 557 |
45 |
zero_gravi |
* Internal helper function: Write PMP configuration register 0..15
|
| 558 |
|
|
*
|
| 559 |
|
|
* @warning This function requires the PMP CPU extension.
|
| 560 |
|
|
*
|
| 561 |
|
|
* @param[in] index PMP CFG configuration register ID (0..15).
|
| 562 |
|
|
* @param[in] data PMP CFG write data.
|
| 563 |
|
|
**************************************************************************/
|
| 564 |
|
|
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data) {
|
| 565 |
|
|
|
| 566 |
|
|
switch(index & 15) {
|
| 567 |
|
|
case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, data); break;
|
| 568 |
|
|
case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, data); break;
|
| 569 |
|
|
case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, data); break;
|
| 570 |
|
|
case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, data); break;
|
| 571 |
|
|
case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, data); break;
|
| 572 |
|
|
case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, data); break;
|
| 573 |
|
|
case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, data); break;
|
| 574 |
|
|
case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, data); break;
|
| 575 |
|
|
case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, data); break;
|
| 576 |
|
|
case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, data); break;
|
| 577 |
|
|
case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, data); break;
|
| 578 |
|
|
case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, data); break;
|
| 579 |
|
|
case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, data); break;
|
| 580 |
|
|
case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, data); break;
|
| 581 |
|
|
case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, data); break;
|
| 582 |
|
|
case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, data); break;
|
| 583 |
|
|
default: break;
|
| 584 |
|
|
}
|
| 585 |
|
|
}
|
| 586 |
|
|
|
| 587 |
|
|
|
| 588 |
|
|
/**********************************************************************//**
|
| 589 |
42 |
zero_gravi |
* Hardware performance monitors (HPM): Get number of available HPM counters.
|
| 590 |
|
|
*
|
| 591 |
|
|
* @warning This function overrides all available mhpmcounter* CSRs.
|
| 592 |
|
|
*
|
| 593 |
|
|
* @return Returns number of available HPM counters (..29).
|
| 594 |
|
|
**************************************************************************/
|
| 595 |
|
|
uint32_t neorv32_cpu_hpm_get_counters(void) {
|
| 596 |
|
|
|
| 597 |
|
|
// try setting all mhpmcounter* CSRs to 1
|
| 598 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 1);
|
| 599 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 1);
|
| 600 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 1);
|
| 601 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 1);
|
| 602 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 1);
|
| 603 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 1);
|
| 604 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 1);
|
| 605 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 1);
|
| 606 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 1);
|
| 607 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 1);
|
| 608 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 1);
|
| 609 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 1);
|
| 610 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER15, 1);
|
| 611 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER16, 1);
|
| 612 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER17, 1);
|
| 613 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER18, 1);
|
| 614 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER19, 1);
|
| 615 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER20, 1);
|
| 616 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER21, 1);
|
| 617 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER22, 1);
|
| 618 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER23, 1);
|
| 619 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER24, 1);
|
| 620 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER25, 1);
|
| 621 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER26, 1);
|
| 622 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER27, 1);
|
| 623 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER28, 1);
|
| 624 |
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER29, 1);
|
| 625 |
|
|
|
| 626 |
|
|
// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
|
| 627 |
|
|
uint32_t num_hpm_cnts = 0;
|
| 628 |
|
|
|
| 629 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
|
| 630 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER4);
|
| 631 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER5);
|
| 632 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER6);
|
| 633 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER7);
|
| 634 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER8);
|
| 635 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER9);
|
| 636 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER10);
|
| 637 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER11);
|
| 638 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER12);
|
| 639 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER13);
|
| 640 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER14);
|
| 641 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER15);
|
| 642 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER16);
|
| 643 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER17);
|
| 644 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER18);
|
| 645 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER19);
|
| 646 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER20);
|
| 647 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER21);
|
| 648 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER22);
|
| 649 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER23);
|
| 650 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER24);
|
| 651 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER25);
|
| 652 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER26);
|
| 653 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER27);
|
| 654 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER28);
|
| 655 |
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER29);
|
| 656 |
|
|
|
| 657 |
|
|
return num_hpm_cnts;
|
| 658 |
|
|
}
|
