URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_rte.c] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


// #################################################################################################
// # << NEORV32: neorv32_rte.c - NEORV32 Runtime Environment >>                                    #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_rte.c
 * @author Stephan Nolting
 * @brief NEORV32 Runtime Environment.
 **************************************************************************/
 
#include "neorv32.h"
#include "neorv32_rte.h"
 
// Privates
static void __neorv32_rte_dummy_exc_handler(void)     __attribute__((unused));
static void __neorv32_rte_debug_exc_handler(void)     __attribute__((unused));
static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
static void __neorv32_rte_print_hw_version(void)      __attribute__((unused));
 
 
/**********************************************************************//**
 * Setup NEORV32 runtime environment in debug mode.
 *
 * @note This function installs a debug handler for ALL exception and interrupt sources, which
 * gives detailed information about the exception/interrupt. Call this function before you
 * install custom handler functions via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)),
 * since this function will override all installed exception handlers.
 *
 * @warning This function should be used for debugging only, since it only shows the uninitialize exception/interrupt, but
 * does not resolve the cause. Hence, it cannot guarantee to resume normal application execution after showing the debug messages.
 **************************************************************************/
void neorv32_rte_enable_debug_mode(void) {
 
  uint8_t id;
 
  // install debug handler for all sources
  for (id=0; id<32; id++) {
    neorv32_rte_exception_install(id, __neorv32_rte_debug_exc_handler);
  }
}
 
 
/**********************************************************************//**
 * Install exception handler function to NEORV32 runtime environment.
 *
 * @note This function automatically activates the according CSR.mie bits when installing handlers for
 * the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has
 * to be set by the user via neorv32_cpu_eint(void).
 *
 * @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum.
 * @param[in] handler The actual handler function for the specified exception (function must be of type "void function(void);").
 * return 0 if success, 1 if error (invalid exc_id or targeted exception not supported).
 **************************************************************************/
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)) {
 
  // id valid?
  if ((exc_id == EXCID_I_MISALIGNED) || (exc_id == EXCID_I_ACCESS)     || (exc_id == EXCID_I_ILLEGAL) ||
      (exc_id == EXCID_BREAKPOINT)   || (exc_id == EXCID_L_MISALIGNED) || (exc_id == EXCID_L_ACCESS)  ||
      (exc_id == EXCID_S_MISALIGNED) || (exc_id == EXCID_S_ACCESS)     || (exc_id == EXCID_MENV_CALL) ||
      (exc_id == EXCID_MSI)          || (exc_id == EXCID_MTI)          || (exc_id == EXCID_MEI)) {
 
    if (exc_id == EXCID_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt
    if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
    if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
 
    uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
    vt_base = vt_base + (((uint32_t)exc_id) << 2);
    (*(IO_REG32 (vt_base))) = (uint32_t)handler;
 
    return 0;
  }
  return 1;
}
 
 
/**********************************************************************//**
 * Uninstall exception handler function from NEORV32 runtime environment, which was
 * previously installed via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)).
 *
 * @note This function automatically clears the according CSR.mie bits when uninstalling handlers for
 * the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has
 * to be cleared by the user via neorv32_cpu_dint(void).
 *
 * @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum.
 * return 0 if success, 1 if error (invalid exc_id or targeted exception not supported).
 **************************************************************************/
int neorv32_rte_exception_uninstall(uint8_t exc_id) {
 
  // id valid?
  if ((exc_id == EXCID_I_MISALIGNED) || (exc_id == EXCID_I_ACCESS)     || (exc_id == EXCID_I_ILLEGAL) ||
      (exc_id == EXCID_BREAKPOINT)   || (exc_id == EXCID_L_MISALIGNED) || (exc_id == EXCID_L_ACCESS)  ||
      (exc_id == EXCID_S_MISALIGNED) || (exc_id == EXCID_S_ACCESS)     || (exc_id == EXCID_MENV_CALL) ||
      (exc_id == EXCID_MSI)          || (exc_id == EXCID_MTI)          || (exc_id == EXCID_MEI)) {
 
    if (exc_id == EXCID_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt
    if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
    if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
 
    uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
    vt_base = vt_base + (((uint32_t)exc_id) << 2);
    (*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered
 
    return 0;
  }
  return 1;
}
 
 
/**********************************************************************//**
 * NEORV32 runtime environment: Dummy exception handler (does nothing).
 * @note This function is used by neorv32_rte_exception_uninstall(uint8_t exc_id) only.
 **************************************************************************/
static void __neorv32_rte_dummy_exc_handler(void) {
 
  asm volatile("nop");
}
 
 
/**********************************************************************//**
 * NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
 * @note This function is used by neorv32_rte_enable_debug_mode(void) only.
 **************************************************************************/
static void __neorv32_rte_debug_exc_handler(void) {
 
  neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");
 
  neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));
 
  register uint32_t exc_cause   = neorv32_cpu_csr_read(CSR_MCAUSE);
  register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC);
  register uint32_t trans_cmd   = neorv32_cpu_csr_read(CSR_MTINST);
 
  if (exc_cause & 0x80000000) {
    neorv32_uart_printf("INTERRUPT");
  }
  else {
    neorv32_uart_printf("EXCEPTION");
    if ((trans_cmd & (1 << 1)) == 0) {
      return_addr -= 4;
    }
    else {
      return_addr -= 2;
    }
  }
  neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr);
 
  neorv32_uart_printf("Cause: ");
  switch (exc_cause) {
    case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break;
    case 0x00000001: neorv32_uart_printf("Instruction access fault"); break;
    case 0x00000002: neorv32_uart_printf("Illegal instruction"); break;
    case 0x00000003: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
    case 0x00000004: neorv32_uart_printf("Load address misaligned"); break;
    case 0x00000005: neorv32_uart_printf("Load access fault"); break;
    case 0x00000006: neorv32_uart_printf("Store address misaligned"); break;
    case 0x00000007: neorv32_uart_printf("Store access fault"); break;
    case 0x0000000B: neorv32_uart_printf("Environment call (ECALL)"); break;
    case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break;
    case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break;
    case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;
    default:         neorv32_uart_printf("Unknown (0x%x)", exc_cause); break;
  }
 
  // fault address
  if (exc_cause == 0x00000002) {
    neorv32_uart_printf("\nFaulting instruction");
  }
  else {
    neorv32_uart_printf("\nFaulting address");
  }
  neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
  neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd);
 
  if ((trans_cmd & (1 << 1)) == 0) {
    neorv32_uart_printf("(decompressed)\n");
  }
 
  neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
 
  neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n");
}
 
 
/**********************************************************************//**
 * NEORV32 runtime environment: Print hardware configuration information via UART
 **************************************************************************/
void neorv32_rte_print_hw_config(void) {
 
  uint32_t tmp;
  int i;
  char c;
 
  neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
 
  // CPU configuration
  neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
  // Hart ID
  neorv32_uart_printf("Hart ID:          0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
 
  // HW version
  neorv32_uart_printf("Hardware version: ");
  __neorv32_rte_print_hw_version();
  neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
 
  // CPU architecture
  neorv32_uart_printf("Architecture:     ");
  tmp = neorv32_cpu_csr_read(CSR_MISA);
  tmp = (tmp >> 30) & 0x03;
  if (tmp == 0) {
    neorv32_uart_printf("unknown");
  }
  if (tmp == 1) {
    neorv32_uart_printf("RV32");
  }
  if (tmp == 2) {
    neorv32_uart_printf("RV64");
  }
  if (tmp == 3) {
    neorv32_uart_printf("RV128");
  }
 
  // CPU extensions
  neorv32_uart_printf("\nCPU extensions:   ");
  tmp = neorv32_cpu_csr_read(CSR_MISA);
  for (i=0; i<26; i++) {
    if (tmp & (1 << i)) {
      c = (char)('A' + i);
      neorv32_uart_putc(c);
      neorv32_uart_putc(' ');
    }
  }
  neorv32_uart_printf("(0x%x)\n", tmp);
 
  // Performance counters
  neorv32_uart_printf("CNT & time CSRs:  ");
  __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));
 
  // Clock speed
  neorv32_uart_printf("Clock speed:      %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));
 
  // Memory configuration
  neorv32_uart_printf("\n-- Memory Configuration --\n");
 
  uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);
  uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);
  neorv32_uart_printf("Instruction memory:   %u bytes @ 0x%x\n", size, base);
  neorv32_uart_printf("Internal IMEM:        ");
  __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));
  neorv32_uart_printf("Internal IMEM as ROM: ");
  __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));
 
  size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);
  base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
  neorv32_uart_printf("Data memory:          %u bytes @ 0x%x\n", size, base);
  neorv32_uart_printf("Internal DMEM:        ");
  __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));
 
  neorv32_uart_printf("Bootloader:           ");
  __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));
 
  neorv32_uart_printf("External interface:   ");
  __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));
 
  // peripherals
  neorv32_uart_printf("\n-- Peripherals --\n");
  tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
 
  neorv32_uart_printf("GPIO:    ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
 
  neorv32_uart_printf("MTIME:   ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
 
  neorv32_uart_printf("UART:    ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
 
  neorv32_uart_printf("SPI:     ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
 
  neorv32_uart_printf("TWI:     ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
 
  neorv32_uart_printf("PWM:     ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
 
  neorv32_uart_printf("WDT:     ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
 
  neorv32_uart_printf("CLIC:    ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
 
  neorv32_uart_printf("TRNG:    ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
 
  neorv32_uart_printf("DEVNULL: ");
  __neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
}
 
 
/**********************************************************************//**
 * NEORV32 runtime environment: Private function to print true or false.
 * @note This function is used by neorv32_rte_print_hw_config(void) only.
 *
 * @param[in] state Print TRUE when !=0, print FALSE when 0
 **************************************************************************/
static void __neorv32_rte_print_true_false(int state) {
 
  if (state) {
    neorv32_uart_printf("True\n");
  }
  else {
    neorv32_uart_printf("False\n");
  }
}
 
 
/**********************************************************************//**
 * NEORV32 runtime environment: Private function to show the processor version in human-readable format.
 * @note This function is used by neorv32_rte_print_hw_config(void) only.
 **************************************************************************/
static void __neorv32_rte_print_hw_version(void) {
 
  uint32_t i;
  char tmp, cnt;
  uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
 
  for (i=0; i<4; i++) {
 
    tmp = (char)(version >> (24 - 8*i));
 
    // serial division
    cnt = 0;
    while (tmp >= 10) {
      tmp = tmp - 10;
      cnt++;
    }
 
    if (cnt) {
      neorv32_uart_putc('0' + cnt);
    }
    neorv32_uart_putc('0' + tmp);
    if (i < 3) {
      neorv32_uart_putc('.');
    }
  }
}

Browse

Tools

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_rte.c] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	zero_gravi	`// #################################################################################################`
2			`// # << NEORV32: neorv32_rte.c - NEORV32 Runtime Environment >> #`
3			`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6			`// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #`
7			`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_rte.c`
38			`* @author Stephan Nolting`
39			`* @brief NEORV32 Runtime Environment.`
40			`**************************************************************************/`
41
42			`#include "neorv32.h"`
43			`#include "neorv32_rte.h"`
44
45			`// Privates`
46	6	zero_gravi	`static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));`
47			`static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));`
48			`static void __neorv32_rte_print_true_false(int state) __attribute__((unused));`
49			`static void __neorv32_rte_print_hw_version(void) __attribute__((unused));`
50	2	zero_gravi
51
52			`/********************************************************************//`
53			`* Setup NEORV32 runtime environment in debug mode.`
54			`*`
55			`* @note This function installs a debug handler for ALL exception and interrupt sources, which`
56			`* gives detailed information about the exception/interrupt. Call this function before you`
57			`* install custom handler functions via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)),`
58			`* since this function will override all installed exception handlers.`
59			`*`
60			`* @warning This function should be used for debugging only, since it only shows the uninitialize exception/interrupt, but`
61			`* does not resolve the cause. Hence, it cannot guarantee to resume normal application execution after showing the debug messages.`
62			`**************************************************************************/`
63			`void neorv32_rte_enable_debug_mode(void) {`
64
65			`uint8_t id;`
66
67			`// install debug handler for all sources`
68			`for (id=0; id<32; id++) {`
69			`neorv32_rte_exception_install(id, __neorv32_rte_debug_exc_handler);`
70			`}`
71			`}`
72
73
74			`/********************************************************************//`
75			`* Install exception handler function to NEORV32 runtime environment.`
76			`*`
77			`* @note This function automatically activates the according CSR.mie bits when installing handlers for`
78			`* the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has`
79			`* to be set by the user via neorv32_cpu_eint(void).`
80			`*`
81			`* @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum.`
82			`* @param[in] handler The actual handler function for the specified exception (function must be of type "void function(void);").`
83			`* return 0 if success, 1 if error (invalid exc_id or targeted exception not supported).`
84			`**************************************************************************/`
85			`int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)) {`
86
87			`// id valid?`
88			`if ((exc_id == EXCID_I_MISALIGNED) \|\| (exc_id == EXCID_I_ACCESS) \|\| (exc_id == EXCID_I_ILLEGAL) \|\|`
89			`(exc_id == EXCID_BREAKPOINT) \|\| (exc_id == EXCID_L_MISALIGNED) \|\| (exc_id == EXCID_L_ACCESS) \|\|`
90			`(exc_id == EXCID_S_MISALIGNED) \|\| (exc_id == EXCID_S_ACCESS) \|\| (exc_id == EXCID_MENV_CALL) \|\|`
91			`(exc_id == EXCID_MSI) \|\| (exc_id == EXCID_MTI) \|\| (exc_id == EXCID_MEI)) {`
92
93			`if (exc_id == EXCID_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt`
94			`if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt`
95			`if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt`
96
97			`uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table`
98			`vt_base = vt_base + (((uint32_t)exc_id) << 2);`
99			`(*(IO_REG32 (vt_base))) = (uint32_t)handler;`
100
101			`return 0;`
102			`}`
103			`return 1;`
104			`}`
105
106
107			`/********************************************************************//`
108			`* Uninstall exception handler function from NEORV32 runtime environment, which was`
109			`* previously installed via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)).`
110			`*`
111			`* @note This function automatically clears the according CSR.mie bits when uninstalling handlers for`
112			`* the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has`
113			`* to be cleared by the user via neorv32_cpu_dint(void).`
114			`*`
115			`* @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum.`
116			`* return 0 if success, 1 if error (invalid exc_id or targeted exception not supported).`
117			`**************************************************************************/`
118			`int neorv32_rte_exception_uninstall(uint8_t exc_id) {`
119
120			`// id valid?`
121			`if ((exc_id == EXCID_I_MISALIGNED) \|\| (exc_id == EXCID_I_ACCESS) \|\| (exc_id == EXCID_I_ILLEGAL) \|\|`
122			`(exc_id == EXCID_BREAKPOINT) \|\| (exc_id == EXCID_L_MISALIGNED) \|\| (exc_id == EXCID_L_ACCESS) \|\|`
123			`(exc_id == EXCID_S_MISALIGNED) \|\| (exc_id == EXCID_S_ACCESS) \|\| (exc_id == EXCID_MENV_CALL) \|\|`
124			`(exc_id == EXCID_MSI) \|\| (exc_id == EXCID_MTI) \|\| (exc_id == EXCID_MEI)) {`
125
126			`if (exc_id == EXCID_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt`
127			`if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt`
128			`if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt`
129
130			`uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table`
131			`vt_base = vt_base + (((uint32_t)exc_id) << 2);`
132			`(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered`
133
134			`return 0;`
135			`}`
136			`return 1;`
137			`}`
138
139
140			`/********************************************************************//`
141			`* NEORV32 runtime environment: Dummy exception handler (does nothing).`
142			`* @note This function is used by neorv32_rte_exception_uninstall(uint8_t exc_id) only.`
143			`**************************************************************************/`
144			`static void __neorv32_rte_dummy_exc_handler(void) {`
145
146			`asm volatile("nop");`
147			`}`
148
149
150			`/********************************************************************//`
151			`* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.`
152			`* @note This function is used by neorv32_rte_enable_debug_mode(void) only.`
153			`**************************************************************************/`
154			`static void __neorv32_rte_debug_exc_handler(void) {`
155
156	6	zero_gravi	`neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");`
157	2	zero_gravi
158			`neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));`
159
160	6	zero_gravi	`register uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE);`
161			`register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC);`
162			`register uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST);`
163	2	zero_gravi
164			`if (exc_cause & 0x80000000) {`
165			`neorv32_uart_printf("INTERRUPT");`
166			`}`
167			`else {`
168			`neorv32_uart_printf("EXCEPTION");`
169	6	zero_gravi	`if ((trans_cmd & (1 << 1)) == 0) {`
170			`return_addr -= 4;`
171			`}`
172			`else {`
173			`return_addr -= 2;`
174			`}`
175	2	zero_gravi	`}`
176	6	zero_gravi	`neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr);`
177	2	zero_gravi
178			`neorv32_uart_printf("Cause: ");`
179			`switch (exc_cause) {`
180			`case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break;`
181			`case 0x00000001: neorv32_uart_printf("Instruction access fault"); break;`
182			`case 0x00000002: neorv32_uart_printf("Illegal instruction"); break;`
183			`case 0x00000003: neorv32_uart_printf("Breakpoint (EBREAK)"); break;`
184			`case 0x00000004: neorv32_uart_printf("Load address misaligned"); break;`
185			`case 0x00000005: neorv32_uart_printf("Load access fault"); break;`
186			`case 0x00000006: neorv32_uart_printf("Store address misaligned"); break;`
187			`case 0x00000007: neorv32_uart_printf("Store access fault"); break;`
188			`case 0x0000000B: neorv32_uart_printf("Environment call (ECALL)"); break;`
189			`case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break;`
190			`case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break;`
191			`case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;`
192			`default: neorv32_uart_printf("Unknown (0x%x)", exc_cause); break;`
193			`}`
194
195			`// fault address`
196			`if (exc_cause == 0x00000002) {`
197			`neorv32_uart_printf("\nFaulting instruction");`
198			`}`
199			`else {`
200			`neorv32_uart_printf("\nFaulting address");`
201			`}`
202			`neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));`
203			`neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd);`
204
205	6	zero_gravi	`if ((trans_cmd & (1 << 1)) == 0) {`
206			`neorv32_uart_printf("(decompressed)\n");`
207	2	zero_gravi	`}`
208	6	zero_gravi
209			`neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));`
210
211			`neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n");`
212			`}`
213
214
215			`/********************************************************************//`
216			`* NEORV32 runtime environment: Print hardware configuration information via UART`
217			`**************************************************************************/`
218			`void neorv32_rte_print_hw_config(void) {`
219
220			`uint32_t tmp;`
221			`int i;`
222			`char c;`
223
224			`neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");`
225
226			`// CPU configuration`
227			`neorv32_uart_printf("\n-- Central Processing Unit --\n");`
228
229			`// Hart ID`
230			`neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));`
231
232			`// HW version`
233			`neorv32_uart_printf("Hardware version: ");`
234			`__neorv32_rte_print_hw_version();`
235			`neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));`
236
237			`// CPU architecture`
238			`neorv32_uart_printf("Architecture: ");`
239			`tmp = neorv32_cpu_csr_read(CSR_MISA);`
240			`tmp = (tmp >> 30) & 0x03;`
241			`if (tmp == 0) {`
242			`neorv32_uart_printf("unknown");`
243			`}`
244			`if (tmp == 1) {`
245			`neorv32_uart_printf("RV32");`
246			`}`
247			`if (tmp == 2) {`
248			`neorv32_uart_printf("RV64");`
249			`}`
250			`if (tmp == 3) {`
251			`neorv32_uart_printf("RV128");`
252			`}`
253
254			`// CPU extensions`
255			`neorv32_uart_printf("\nCPU extensions: ");`
256			`tmp = neorv32_cpu_csr_read(CSR_MISA);`
257			`for (i=0; i<26; i++) {`
258			`if (tmp & (1 << i)) {`
259			`c = (char)('A' + i);`
260			`neorv32_uart_putc(c);`
261			`neorv32_uart_putc(' ');`
262			`}`
263			`}`
264			`neorv32_uart_printf("(0x%x)\n", tmp);`
265
266			`// Performance counters`
267			`neorv32_uart_printf("CNT & time CSRs: ");`
268			`__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));`
269
270			`// Clock speed`
271			`neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));`
272
273			`// Memory configuration`
274			`neorv32_uart_printf("\n-- Memory Configuration --\n");`
275
276			`uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);`
277			`uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);`
278			`neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);`
279			`neorv32_uart_printf("Internal IMEM: ");`
280			`__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));`
281			`neorv32_uart_printf("Internal IMEM as ROM: ");`
282			`__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));`
283
284			`size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);`
285			`base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);`
286			`neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);`
287			`neorv32_uart_printf("Internal DMEM: ");`
288			`__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));`
289
290			`neorv32_uart_printf("Bootloader: ");`
291			`__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));`
292
293			`neorv32_uart_printf("External interface: ");`
294			`__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));`
295
296			`// peripherals`
297			`neorv32_uart_printf("\n-- Peripherals --\n");`
298			`tmp = neorv32_cpu_csr_read(CSR_MFEATURES);`
299
300			`neorv32_uart_printf("GPIO: ");`
301			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));`
302
303			`neorv32_uart_printf("MTIME: ");`
304			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));`
305
306			`neorv32_uart_printf("UART: ");`
307			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));`
308
309			`neorv32_uart_printf("SPI: ");`
310			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));`
311
312			`neorv32_uart_printf("TWI: ");`
313			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));`
314
315			`neorv32_uart_printf("PWM: ");`
316			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));`
317
318			`neorv32_uart_printf("WDT: ");`
319			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));`
320
321			`neorv32_uart_printf("CLIC: ");`
322			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));`
323
324			`neorv32_uart_printf("TRNG: ");`
325			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));`
326
327			`neorv32_uart_printf("DEVNULL: ");`
328			`__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));`
329			`}`
330
331
332			`/********************************************************************//`
333			`* NEORV32 runtime environment: Private function to print true or false.`
334			`* @note This function is used by neorv32_rte_print_hw_config(void) only.`
335			`*`
336			`* @param[in] state Print TRUE when !=0, print FALSE when 0`
337			`**************************************************************************/`
338			`static void __neorv32_rte_print_true_false(int state) {`
339
340			`if (state) {`
341			`neorv32_uart_printf("True\n");`
342			`}`
343	2	zero_gravi	`else {`
344	6	zero_gravi	`neorv32_uart_printf("False\n");`
345	2	zero_gravi	`}`
346	6	zero_gravi	`}`
347	2	zero_gravi
348
349	6	zero_gravi	`/********************************************************************//`
350			`* NEORV32 runtime environment: Private function to show the processor version in human-readable format.`
351			`* @note This function is used by neorv32_rte_print_hw_config(void) only.`
352			`**************************************************************************/`
353			`static void __neorv32_rte_print_hw_version(void) {`
354
355			`uint32_t i;`
356			`char tmp, cnt;`
357			`uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);`
358
359			`for (i=0; i<4; i++) {`
360
361			`tmp = (char)(version >> (24 - 8*i));`
362
363			`// serial division`
364			`cnt = 0;`
365			`while (tmp >= 10) {`
366			`tmp = tmp - 10;`
367			`cnt++;`
368			`}`
369
370			`if (cnt) {`
371			`neorv32_uart_putc('0' + cnt);`
372			`}`
373			`neorv32_uart_putc('0' + tmp);`
374			`if (i < 3) {`
375			`neorv32_uart_putc('.');`
376			`}`
377			`}`
378	2	zero_gravi	`}`