URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [svd/] [neorv32.svd] - Blame information for rev 69

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  stnolting
  neorv32
  RISC-V
  1.6.4
  The NEORV32 RISC-V Processor
 
  
  
    NEORV32
    r2p0
    little
    true
    true
    false
    false
    true
    true
    0
    false
  
 
  
  8
  32
  32
  read-write
  0x00000000
  0x00000000 
 
  
  
 
    
    
      CFS
      Custom functions subsystem
      CFS
      0xFFFFFE00
 
      CFS_FIRQ1
 
      
        0
        0x80
        registers
      
 
      
        REG0Application-defined0x00
        REG1Application-defined0x04
        REG2Application-defined0x08
        REG3Application-defined0x0C
        REG4Application-defined0x10
        REG5Application-defined0x14
        REG6Application-defined0x18
        REG7Application-defined0x1C
        REG8Application-defined0x20
        REG9Application-defined0x24
        REG10Application-defined0x28
        REG11Application-defined0x2C
        REG12Application-defined0x30
        REG13Application-defined0x34
        REG14Application-defined0x38
        REG15Application-defined0x3C
        REG16Application-defined0x40
        REG17Application-defined0x44
        REG18Application-defined0x48
        REG19Application-defined0x4C
        REG20Application-defined0x50
        REG21Application-defined0x54
        REG22Application-defined0x58
        REG23Application-defined0x5C
        REG24Application-defined0x60
        REG25Application-defined0x64
        REG26Application-defined0x68
        REG27Application-defined0x6C
        REG28Application-defined0x70
        REG29Application-defined0x74
        REG30Application-defined0x78
        REG31Application-defined0x7C
      
    
 
    
    
      PWM
      Pulse-width modulation controller
      PWM
      0xFFFFFE80
 
      
        0
        0x40
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              PWM_CTRL_EN
              [0:0]
              PWM controller enable flag
            
            
              PWM_CTRL_PRSCx
              [3:1]
              Clock prescaler select
            
          
        
        
          DUTY0
          Duty cycle register 0
          0x04
        
        
          DUTY1
          Duty cycle register 1
          0x08
        
        
          DUTY2
          Duty cycle register 2
          0x0C
        
        
          DUTY3
          Duty cycle register 3
          0x10
        
        
          DUTY4
          Duty cycle register 4
          0x14
        
        
          DUTY5
          Duty cycle register 5
          0x18
        
        
          DUTY6
          Duty cycle register 6
          0x1C
        
        
          DUTY7
          Duty cycle register 7
          0x20
        
        
          DUTY8
          Duty cycle register 8
          0x24
        
        
          DUTY9
          Duty cycle register 9
          0x28
        
        
          DUTY10
          Duty cycle register 10
          0x2C
        
        
          DUTY11
          Duty cycle register 11
          0x30
        
        
          DUTY12
          Duty cycle register 12
          0x34
        
        
          DUTY13
          Duty cycle register 13
          0x38
        
        
          DUTY14
          Duty cycle register 14
          0x3C
        
      
    
 
    
    
      SLINK
      Stream link interface
      SLINK
      0xFFFFFEC0
 
      SLINK_RX_FIRQ10
      SLINK_TX_FIRQ11
 
      
        0
        0x40
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              SLINK_CTRL_RX_NUMx
              read-only
              [3:0]
              Number of implemented RX links
            
            
              SLINK_CTRL_TX_NUMx
              read-only
              [7:4]
              Number of implemented TX links
            
            
              SLINK_CTRL_RX_FIFO_Sx
              read-only
              [11:8]
              log2(RX FIFO size)
            
            
              SLINK_CTRL_TX_FIFO_Sx
              read-only
              [15:12]
              log2(TX FIFO size)
            
            
              SLINK_CTRL_EN
              read-write
              [31:31]
              SLINK enable flag
            
          
        
        
          IRQ
          Link interrupt configuration register
          0x08
          
            
              SLINK_IRQ_RX_EN
              [7:0]
              RX link interrupt enable
            
            
              SLINK_IRQ_RX_MODE
              [15:8]
              RX link interrupt mode
            
            
              SLINK_IRQ_TX_EN
              [23:16]
              TX link interrupt enable
            
            
              SLINK_IRQ_TX_MODE
              [31:24]
              TX link interrupt mode
            
          
        
        
          STATUS
          Link status register
          0x10
          
            
              SLINK_STATUS_RX_AVAIL
              [7:0]
              RX link n FIFO is NOT empty (data available)
            
            
              SLINK_STATUS_TX_FREE
              [15:8]
              TX link n FIFO is NOT full (ready to send)
            
            
              SLINK_STATUS_RX_HALF
              [23:16]
              RX link n FIFO fill level is >= half-full
            
            
              SLINK_STATUS_TX_HALF
              [31:24]
              TX link 0 FIFO fill level is > half-full
            
          
        
        
          DATA0
          Link 0 RTX data register
          0x20
        
        
          DATA1
          Link 1 RTX data register
          0x24
        
        
          DATA2
          Link 2 RTX data register
          0x28
        
        
          DATA3
          Link 3 RTX data register
          0x2C
        
        
          DATA4
          Link 4 RTX data register
          0x30
        
        
          DATA5
          Link 5 RTX data register
          0x34
        
        
          DATA6
          Link 6 RTX data register
          0x38
        
        
          DATA7
          Link 7 RTX data register
          0x3C
        
      
    
 
    
    
      GPTMR
      General purpose timer
      GPTMR
      0xFFFFFF60
 
      GPTMR_FIRQ12
 
      
        0
        0x10
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              GPTMR_CTRL_EN
              [0:0]
              Timer enable flag
            
            
              GPTMR_CTRL_PRSC
              [3:1]
              Clock prescaler select
            
            
              GPTMR_CTRL_MODE
              [4:4]
              Timer mode: 0=single-shot mode, 1=continuous mode
            
          
        
        
          THRES
          Threshold register
          0x04
        
        
          COUNT
          Counter register
          0x08
        
      
    
 
    
    
      BUSKEEPER
      Bus keeper
      BUSKEEPER
      0xFFFFFF7C
 
      
        0
        0x04
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              BUSKEEPER_ERR_TYPE
              [0:0]
              read-only
              Bus error type: 0=device error, 1=access timeout
            
            
              BUSKEEPER_ERR_FLAG
              [31:31]
              Sticky error flag, clears after read or write access
            
          
        
      
    
 
    
    
      XIRQ
      External interrupts controller
      XIRQ
      0xFFFFFF80
 
      XIRQ_FIRQ8
 
      
        0
        0x10
        registers
      
 
      
        
          IER
          IRQ input enable register
          0x00
        
        
          IPR
          IRQ pending/ack/clear register
          0x04
        
        
          SCR
          IRQ source register
          0x08
        
      
    
 
    
    
      MTIME
      Machine timer
      MTIME
      0xFFFFFF90
 
      
        0
        0x10
        registers
      
 
      
        
          TIME_LO
          System time register - low
          0x00
        
        
          TIME_HI
          System time register - high
          0x04
        
        
          TIMECMP_LO
          Time compare register - low
          0x08
        
        
          TIMECMP_HI
          Time compare register - high
          0x0C
        
      
    
 
    
    
      UART0
      Primary universal asynchronous receiver and transmitter
      UART0
      0xFFFFFFA0
 
      UART0_RX_FIRQ2
      UART0_TX_FIRQ3
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              UART_CTRL_BAUD
              [11:0]
              Baud rate divisor
            
            
              UART_CTRL_SIM_MODE
              [12:12]
              Simulation output override enable, for use in simulation only
            
            
              UART_CTRL_RX_EMPTY
              [13:13]
              read-only
              RX FIFO is empty
            
            
              UART_CTRL_RX_HALF
              [14:14]
              read-only
              RX FIFO is at least half-full
            
            
              UART_CTRL_RX_FULL
              [15:15]
              read-only
              RX FIFO is full
            
            
              UART_CTRL_TX_EMPTY
              [16:16]
              read-only
              TX FIFO is empty
            
            
              UART_CTRL_TX_HALF
              [17:17]
              read-only
              TX FIFO is at least half-full
            
            
              UART_CTRL_TX_FULL
              [18:18]
              read-only
              TX FIFO is full
            
            
              UART_CTRL_RTS_EN
              [20:20]
              Enable hardware flow control: Assert RTS output if UART.RX is ready to receive
            
            
              UART_CTRL_CTS_EN
              [21:21]
              Enable hardware flow control: UART.TX starts sending only if CTS input is asserted
            
            
              UART_CTRL_PMODE0
              [22:22]
              Parity configuration (0=even; 1=odd)
            
            
              UART_CTRL_PMODE1
              [23:23]
              Parity bit enabled when set
            
            
              UART_CTRL_PRSC
              [26:24]
              Clock prescaler select
            
            
              UART_CTRL_CTS
              [27:27]
              read-only
              current state of CTS input
            
            
              UART_CTRL_EN
              [28:28]
              UART enable flag
            
            
              UART_CTRL_RX_IRQ
              [29:29]
              RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty
            
            
              UART_CTRL_TX_IRQ
              [30:30]
              TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full
            
            
              UART_CTRL_TX_BUSY
              [31:31]
              read-only
              Transmitter is busy when set
            
          
        
        
          DATA
          RX/TX data register
          0x04
          
            
              UART_DATA
              [7:0]
              Receive/transmit data
            
            
              UART_DATA_PERR
              [28:28]
              read-only
              RX parity error detected when set
            
            
              UART_DATA_FERR
              [29:29]
              read-only
              RX frame error (no valid stop bit) detected when set
            
            
              UART_DATA_OVERR
              [30:30]
              read-only
              RX parity error detected when set
            
            
              UART_DATA_AVAIL
              [31:31]
              read-only
              RX data available when set
            
          
        
      
    
 
    
    
      UART1
      Secondary universal asynchronous receiver and transmitter
      UART1
      0xFFFFFFD0
 
      UART1_RX_FIRQ4
      UART1_TX_FIRQ5
 
      
        0
        0x08
        registers
      
 
    
 
    
    
      SPI
      Serial peripheral interface controller
      SPI
      0xFFFFFFA8
 
      SPI_FIRQ6
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              SPI_CTRL_CS
              [7:0]
              Direct chip select line
            
            
              SPI_CTRL_EN
              [8:8]
              SPI enable flag
            
            
              SPI_CTRL_CPHA
              [9:9]
              Clock phase
            
            
              SPI_CTRL_PRSC
              [12:10]
              Clock prescaler select
            
            
              SPI_CTRL_SIZE
              [14:13]
              Data transfer size
            
            
              SPI_CTRL_CPOL
              [15:15]
              Clock polarity
            
            
              SPI_CTRL_BUSY
              [31:31]
              read-only
              SPI busy flag
            
          
        
        
          DATA
          RX/TX data register
          0x04
        
      
    
 
    
    
      TWI
      Two-wire interface controller
      SPI
      0xFFFFFFB0
 
      TWI_FIRQ7
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              TWI_CTRL_EN
              [0:0]
              TWI enable flag
            
            
              TWI_CTRL_START
              [1:1]
              Generate START condition, auto-clears
            
            
              TWI_CTRL_STOP
              [2:2]
              Generate STOP condition, auto-clears
            
            
              TWI_CTRL_PRSC
              [5:3]
              Clock prescaler select
            
            
              TWI_CTRL_MACK
              [6:6]
              Generate ACK by controller for each transmission
            
            
              TWI_CTRL_ACK
              [30:30]
              read-only
              ACK received when set
            
            
              TWI_CTRL_BUSY
              [31:31]
              read-only
              Transfer in progress, busy flag
            
          
        
        
          DATA
          RX/TX data register
          0x04
          
            
              TWI_DATA
              [7:0]
              RX/TX data
            
          
        
      
    
 
    
    
      TRNG
      True random number generator
      TRNG
      0xFFFFFFB8
 
      
        0
        0x04
        registers
      
 
      
        
          CTRL
          Control and data register
          0x00
          
            
              TRNG_CTRL_DATA
              [7:0]
              read-only
              Random data
            
            
              TRNG_CTRL_EN
              [30:30]
              TRNG enable flag
            
            
              TRNG_CTRL_VALID
              [31:31]
              read-only
              Random data output valid
            
          
        
      
    
 
    
    
      WDT
      Watchdog timer
      WDT
      0xFFFFFFBC
 
      WDT_FIRQ0
 
      
        0
        0x04
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              WDT_CTRL_EN
              [0:0]
              WDT enable flag
            
            
              WDT_CTRL_CLK_SEL
              [3:1]
              Clock prescaler select
            
            
              WDT_CTRL_MODE
              [4:4]
              Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset
            
            
              WDT_CTRL_RCAUSE
              [5:5]
              read-only
              Cause of last system reset: 0=external reset, 1=watchdog
            
            
              WDT_CTRL_RESET
              [6:6]
              Reset WDT counter when set, auto-clears
            
            
              WDT_CTRL_FORCE
              [7:7]
              Force WDT action, auto-clears
            
            
              WDT_CTRL_LOCK
              [8:8]
              Lock write access to control register, clears on reset (HW or WDT) only
            
            
              WDT_CTRL_DBEN
              [9:9]
              Allow WDT to continue operation even when in debug mode
            
            
              WDT_CTRL_HALF
              [10:10]
              read-only
              Set if at least half of the max. timeout counter value has been reached
            
          
        
      
    
 
    
    
      GPIO
      General purpose input/output port
      GPIO
      0xFFFFFFc0
 
      
        0
        0x10
        registers
      
 
      
        
          INPUT_LO
          Parallel input register - low
          0x00
          read-only
        
        
          INPUT_HI
          Parallel input register - high
          0x04
          read-only
        
        
          OUTPUT_LO
          Parallel output register - low
          0x08
        
        
          OUTPUT_HI
          Parallel output register - high
          0x0C
        
      
    
 
    
    
      NEOLED
      Smart LED hardware interface
      NEOLED
      0xFFFFFFD8
 
      NEOLED_FIRQ9
 
      
        0
        0x08
        registers
      
 
      
        
          CTRL
          Control register
          0x00
          
            
              NEOLED_CTRL_EN
              [0:0]
              NEOLED enable flag
            
            
              NEOLED_CTRL_MODE
              [1:1]
              TX mode (0=24-bit, 1=32-bit)
            
            
              NEOLED_CTRL_STROBE
              [2:2]
              Strobe (0=send normal data, 1=send RESET command on data write)
            
            
              NEOLED_CTRL_PRSC
              [5:3]
              Clock prescaler select
            
            
              NEOLED_CTRL_BUFS
              [9:6]
              read-only
              log2(tx buffer size)
            
            
              NEOLED_CTRL_T_TOT
              [14:10]
              pulse-clock ticks per total period bit
            
            
              NEOLED_CTRL_T_ZERO_H
              [19:15]
              pulse-clock ticks per ZERO high-time
            
            
              NEOLED_CTRL_T_ONE_H
              [24:20]
              pulse-clock ticks per ONE high-time
            
            
              NEOLED_CTRL_IRQ_CONF
              [27:27]
              TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty
            
            
              NEOLED_CTRL_TX_EMPTY
              [28:28]
              read-only
              TX FIFO is empty
            
            
              NEOLED_CTRL_TX_HALF
              [29:29]
              read-only
              TX FIFO is at least half-full
            
            
              NEOLED_CTRL_TX_FULL
              [30:30]
              read-only
              TX FIFO is full
            
            
              NEOLED_CTRL_TX_BUSY
              [31:31]
              read-only
              busy flag
            
          
        
        
          DATA
          Data register
          0x04
        
      
    
 
    
    
      SYSINFO
      System configuration information memory
      SYSINFO
      0xFFFFFFE0
 
      
        0
        0x20
        registers
      
 
      
        
          CLK
          Clock speed in Hz
          0x00
          read-only
        
        
          CPU
          CPU core features
          0x04
          read-only
          
            SYSINFO_CPU_ZICSR[0:0]Zicsr extension (I sub-extension) available when set
            SYSINFO_CPU_ZIFENCEI[1:1]Zifencei extension (I sub-extension) available when set
            SYSINFO_CPU_ZMMUL[2:2]Zmmul extension (M sub-extension) available when set
            SYSINFO_CPU_ZFINX[5:5]Zfinx extension (F sub-/alternative-extension) available when set
            SYSINFO_CPU_ZXSCNT[6:6]Custom extension - Small CPU counters
            SYSINFO_CPU_ZICNTR[7:7]Basic CPU counters available when set
            SYSINFO_CPU_PMP[8:8]PMP (physical memory protection) extension available when set
            SYSINFO_CPU_ZIHPM[9:9]HPM (hardware performance monitors) extension available when set
            SYSINFO_CPU_DEBUGMODE[10:10]RISC-V CPU debug mode available when set
            SYSINFO_CPU_FASTMUL[30:30]fast multiplications (via FAST_MUL_EN generic) available when set
            SYSINFO_CPU_FASTSHIFT[31:31]fast shifts (via FAST_SHIFT_EN generic) available when set
          
        
        
          SOC
          SoC features
          0x08
          read-only
          
            SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented
            SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented
            SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented
            SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented
            SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order
            SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented
            SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated
            SYSINFO_SOC_OCD[14:14]On-chip debugger implemented
            SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented
            SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented
            SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented
            SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented
            SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented
            SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented
            SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented
            SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented
            SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented
            SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented
            SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented
            SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented
            SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented
            SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented
            SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented
          
        
        
          CACHE
          Cache configuration
          0x0C
          read-only
          
            SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes)
            SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines)
            SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity)
            SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)
          
        
        
          ISPACE_BASE
          Instruction memory address space base address
          0x10
          read-only
        
        
          DSPACE_BASE
          Data memory address space base address
          0x14
          read-only
        
        
          IMEM_SIZE
          Internal instruction memory (IMEM) size in bytes
          0x18
          read-only
        
        
          DMEM_SIZE
          Internal data memory (DMEM) size in bytes
          0x1C
          read-only
        
      
    
 
  


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Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [svd/] [neorv32.svd] - Blame information for rev 69

Line No.	Rev	Author	Line
1	69	zero_gravi
2
3
4			`stnolting`
5			`neorv32`
6			`RISC-V`
7			`1.6.4`
8			`The NEORV32 RISC-V Processor`
9
10
11
12			`NEORV32`
13			`r2p0`
14			`little`
15			`true`
16			`true`
17			`false`
18			`false`
19			`true`
20			`true`
21			`0`
22			`false`
23
24
25
26			`8`
27			`32`
28			`32`
29			`read-write`
30			`0x00000000`
31			`0x00000000`
32
33
34
35
36
37
38			`CFS`
39			`Custom functions subsystem`
40			`CFS`
41			`0xFFFFFE00`
42
43			`CFS_FIRQ1`
44
45
46			`0`
47			`0x80`
48			`registers`
49
50
51
52			`REG0Application-defined0x00`
53			`REG1Application-defined0x04`
54			`REG2Application-defined0x08`
55			`REG3Application-defined0x0C`
56			`REG4Application-defined0x10`
57			`REG5Application-defined0x14`
58			`REG6Application-defined0x18`
59			`REG7Application-defined0x1C`
60			`REG8Application-defined0x20`
61			`REG9Application-defined0x24`
62			`REG10Application-defined0x28`
63			`REG11Application-defined0x2C`
64			`REG12Application-defined0x30`
65			`REG13Application-defined0x34`
66			`REG14Application-defined0x38`
67			`REG15Application-defined0x3C`
68			`REG16Application-defined0x40`
69			`REG17Application-defined0x44`
70			`REG18Application-defined0x48`
71			`REG19Application-defined0x4C`
72			`REG20Application-defined0x50`
73			`REG21Application-defined0x54`
74			`REG22Application-defined0x58`
75			`REG23Application-defined0x5C`
76			`REG24Application-defined0x60`
77			`REG25Application-defined0x64`
78			`REG26Application-defined0x68`
79			`REG27Application-defined0x6C`
80			`REG28Application-defined0x70`
81			`REG29Application-defined0x74`
82			`REG30Application-defined0x78`
83			`REG31Application-defined0x7C`
84
85
86
87
88
89			`PWM`
90			`Pulse-width modulation controller`
91			`PWM`
92			`0xFFFFFE80`
93
94
95			`0`
96			`0x40`
97			`registers`
98
99
100
101
102			`CTRL`
103			`Control register`
104			`0x00`
105
106
107			`PWM_CTRL_EN`
108			`[0:0]`
109			`PWM controller enable flag`
110
111
112			`PWM_CTRL_PRSCx`
113			`[3:1]`
114			`Clock prescaler select`
115
116
117
118
119			`DUTY0`
120			`Duty cycle register 0`
121			`0x04`
122
123
124			`DUTY1`
125			`Duty cycle register 1`
126			`0x08`
127
128
129			`DUTY2`
130			`Duty cycle register 2`
131			`0x0C`
132
133
134			`DUTY3`
135			`Duty cycle register 3`
136			`0x10`
137
138
139			`DUTY4`
140			`Duty cycle register 4`
141			`0x14`
142
143
144			`DUTY5`
145			`Duty cycle register 5`
146			`0x18`
147
148
149			`DUTY6`
150			`Duty cycle register 6`
151			`0x1C`
152
153
154			`DUTY7`
155			`Duty cycle register 7`
156			`0x20`
157
158
159			`DUTY8`
160			`Duty cycle register 8`
161			`0x24`
162
163
164			`DUTY9`
165			`Duty cycle register 9`
166			`0x28`
167
168
169			`DUTY10`
170			`Duty cycle register 10`
171			`0x2C`
172
173
174			`DUTY11`
175			`Duty cycle register 11`
176			`0x30`
177
178
179			`DUTY12`
180			`Duty cycle register 12`
181			`0x34`
182
183
184			`DUTY13`
185			`Duty cycle register 13`
186			`0x38`
187
188
189			`DUTY14`
190			`Duty cycle register 14`
191			`0x3C`
192
193
194
195
196
197
198			`SLINK`
199			`Stream link interface`
200			`SLINK`
201			`0xFFFFFEC0`
202
203			`SLINK_RX_FIRQ10`
204			`SLINK_TX_FIRQ11`
205
206
207			`0`
208			`0x40`
209			`registers`
210
211
212
213
214			`CTRL`
215			`Control register`
216			`0x00`
217
218
219			`SLINK_CTRL_RX_NUMx`
220			`read-only`
221			`[3:0]`
222			`Number of implemented RX links`
223
224
225			`SLINK_CTRL_TX_NUMx`
226			`read-only`
227			`[7:4]`
228			`Number of implemented TX links`
229
230
231			`SLINK_CTRL_RX_FIFO_Sx`
232			`read-only`
233			`[11:8]`
234			`log2(RX FIFO size)`
235
236
237			`SLINK_CTRL_TX_FIFO_Sx`
238			`read-only`
239			`[15:12]`
240			`log2(TX FIFO size)`
241
242
243			`SLINK_CTRL_EN`
244			`read-write`
245			`[31:31]`
246			`SLINK enable flag`
247
248
249
250
251			`IRQ`
252			`Link interrupt configuration register`
253			`0x08`
254
255
256			`SLINK_IRQ_RX_EN`
257			`[7:0]`
258			`RX link interrupt enable`
259
260
261			`SLINK_IRQ_RX_MODE`
262			`[15:8]`
263			`RX link interrupt mode`
264
265
266			`SLINK_IRQ_TX_EN`
267			`[23:16]`
268			`TX link interrupt enable`
269
270
271			`SLINK_IRQ_TX_MODE`
272			`[31:24]`
273			`TX link interrupt mode`
274
275
276
277
278			`STATUS`
279			`Link status register`
280			`0x10`
281
282
283			`SLINK_STATUS_RX_AVAIL`
284			`[7:0]`
285			`RX link n FIFO is NOT empty (data available)`
286
287
288			`SLINK_STATUS_TX_FREE`
289			`[15:8]`
290			`TX link n FIFO is NOT full (ready to send)`
291
292
293			`SLINK_STATUS_RX_HALF`
294			`[23:16]`
295			`RX link n FIFO fill level is >= half-full`
296
297
298			`SLINK_STATUS_TX_HALF`
299			`[31:24]`
300			`TX link 0 FIFO fill level is > half-full`
301
302
303
304
305			`DATA0`
306			`Link 0 RTX data register`
307			`0x20`
308
309
310			`DATA1`
311			`Link 1 RTX data register`
312			`0x24`
313
314
315			`DATA2`
316			`Link 2 RTX data register`
317			`0x28`
318
319
320			`DATA3`
321			`Link 3 RTX data register`
322			`0x2C`
323
324
325			`DATA4`
326			`Link 4 RTX data register`
327			`0x30`
328
329
330			`DATA5`
331			`Link 5 RTX data register`
332			`0x34`
333
334
335			`DATA6`
336			`Link 6 RTX data register`
337			`0x38`
338
339
340			`DATA7`
341			`Link 7 RTX data register`
342			`0x3C`
343
344
345
346
347
348
349			`GPTMR`
350			`General purpose timer`
351			`GPTMR`
352			`0xFFFFFF60`
353
354			`GPTMR_FIRQ12`
355
356
357			`0`
358			`0x10`
359			`registers`
360
361
362
363
364			`CTRL`
365			`Control register`
366			`0x00`
367
368
369			`GPTMR_CTRL_EN`
370			`[0:0]`
371			`Timer enable flag`
372
373
374			`GPTMR_CTRL_PRSC`
375			`[3:1]`
376			`Clock prescaler select`
377
378
379			`GPTMR_CTRL_MODE`
380			`[4:4]`
381			`Timer mode: 0=single-shot mode, 1=continuous mode`
382
383
384
385
386			`THRES`
387			`Threshold register`
388			`0x04`
389
390
391			`COUNT`
392			`Counter register`
393			`0x08`
394
395
396
397
398
399
400			`BUSKEEPER`
401			`Bus keeper`
402			`BUSKEEPER`
403			`0xFFFFFF7C`
404
405
406			`0`
407			`0x04`
408			`registers`
409
410
411
412
413			`CTRL`
414			`Control register`
415			`0x00`
416
417
418			`BUSKEEPER_ERR_TYPE`
419			`[0:0]`
420			`read-only`
421			`Bus error type: 0=device error, 1=access timeout`
422
423
424			`BUSKEEPER_ERR_FLAG`
425			`[31:31]`
426			`Sticky error flag, clears after read or write access`
427
428
429
430
431
432
433
434
435			`XIRQ`
436			`External interrupts controller`
437			`XIRQ`
438			`0xFFFFFF80`
439
440			`XIRQ_FIRQ8`
441
442
443			`0`
444			`0x10`
445			`registers`
446
447
448
449
450			`IER`
451			`IRQ input enable register`
452			`0x00`
453
454
455			`IPR`
456			`IRQ pending/ack/clear register`
457			`0x04`
458
459
460			`SCR`
461			`IRQ source register`
462			`0x08`
463
464
465
466
467
468
469			`MTIME`
470			`Machine timer`
471			`MTIME`
472			`0xFFFFFF90`
473
474
475			`0`
476			`0x10`
477			`registers`
478
479
480
481
482			`TIME_LO`
483			`System time register - low`
484			`0x00`
485
486
487			`TIME_HI`
488			`System time register - high`
489			`0x04`
490
491
492			`TIMECMP_LO`
493			`Time compare register - low`
494			`0x08`
495
496
497			`TIMECMP_HI`
498			`Time compare register - high`
499			`0x0C`
500
501
502
503
504
505
506			`UART0`
507			`Primary universal asynchronous receiver and transmitter`
508			`UART0`
509			`0xFFFFFFA0`
510
511			`UART0_RX_FIRQ2`
512			`UART0_TX_FIRQ3`
513
514
515			`0`
516			`0x08`
517			`registers`
518
519
520
521
522			`CTRL`
523			`Control register`
524			`0x00`
525
526
527			`UART_CTRL_BAUD`
528			`[11:0]`
529			`Baud rate divisor`
530
531
532			`UART_CTRL_SIM_MODE`
533			`[12:12]`
534			`Simulation output override enable, for use in simulation only`
535
536
537			`UART_CTRL_RX_EMPTY`
538			`[13:13]`
539			`read-only`
540			`RX FIFO is empty`
541
542
543			`UART_CTRL_RX_HALF`
544			`[14:14]`
545			`read-only`
546			`RX FIFO is at least half-full`
547
548
549			`UART_CTRL_RX_FULL`
550			`[15:15]`
551			`read-only`
552			`RX FIFO is full`
553
554
555			`UART_CTRL_TX_EMPTY`
556			`[16:16]`
557			`read-only`
558			`TX FIFO is empty`
559
560
561			`UART_CTRL_TX_HALF`
562			`[17:17]`
563			`read-only`
564			`TX FIFO is at least half-full`
565
566
567			`UART_CTRL_TX_FULL`
568			`[18:18]`
569			`read-only`
570			`TX FIFO is full`
571
572
573			`UART_CTRL_RTS_EN`
574			`[20:20]`
575			`Enable hardware flow control: Assert RTS output if UART.RX is ready to receive`
576
577
578			`UART_CTRL_CTS_EN`
579			`[21:21]`
580			`Enable hardware flow control: UART.TX starts sending only if CTS input is asserted`
581
582
583			`UART_CTRL_PMODE0`
584			`[22:22]`
585			`Parity configuration (0=even; 1=odd)`
586
587
588			`UART_CTRL_PMODE1`
589			`[23:23]`
590			`Parity bit enabled when set`
591
592
593			`UART_CTRL_PRSC`
594			`[26:24]`
595			`Clock prescaler select`
596
597
598			`UART_CTRL_CTS`
599			`[27:27]`
600			`read-only`
601			`current state of CTS input`
602
603
604			`UART_CTRL_EN`
605			`[28:28]`
606			`UART enable flag`
607
608
609			`UART_CTRL_RX_IRQ`
610			`[29:29]`
611			`RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty`
612
613
614			`UART_CTRL_TX_IRQ`
615			`[30:30]`
616			`TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full`
617
618
619			`UART_CTRL_TX_BUSY`
620			`[31:31]`
621			`read-only`
622			`Transmitter is busy when set`
623
624
625
626
627			`DATA`
628			`RX/TX data register`
629			`0x04`
630
631
632			`UART_DATA`
633			`[7:0]`
634			`Receive/transmit data`
635
636
637			`UART_DATA_PERR`
638			`[28:28]`
639			`read-only`
640			`RX parity error detected when set`
641
642
643			`UART_DATA_FERR`
644			`[29:29]`
645			`read-only`
646			`RX frame error (no valid stop bit) detected when set`
647
648
649			`UART_DATA_OVERR`
650			`[30:30]`
651			`read-only`
652			`RX parity error detected when set`
653
654
655			`UART_DATA_AVAIL`
656			`[31:31]`
657			`read-only`
658			`RX data available when set`
659
660
661
662
663
664
665
666
667			`UART1`
668			`Secondary universal asynchronous receiver and transmitter`
669			`UART1`
670			`0xFFFFFFD0`
671
672			`UART1_RX_FIRQ4`
673			`UART1_TX_FIRQ5`
674
675
676			`0`
677			`0x08`
678			`registers`
679
680
681
682
683
684
685			`SPI`
686			`Serial peripheral interface controller`
687			`SPI`
688			`0xFFFFFFA8`
689
690			`SPI_FIRQ6`
691
692
693			`0`
694			`0x08`
695			`registers`
696
697
698
699
700			`CTRL`
701			`Control register`
702			`0x00`
703
704
705			`SPI_CTRL_CS`
706			`[7:0]`
707			`Direct chip select line`
708
709
710			`SPI_CTRL_EN`
711			`[8:8]`
712			`SPI enable flag`
713
714
715			`SPI_CTRL_CPHA`
716			`[9:9]`
717			`Clock phase`
718
719
720			`SPI_CTRL_PRSC`
721			`[12:10]`
722			`Clock prescaler select`
723
724
725			`SPI_CTRL_SIZE`
726			`[14:13]`
727			`Data transfer size`
728
729
730			`SPI_CTRL_CPOL`
731			`[15:15]`
732			`Clock polarity`
733
734
735			`SPI_CTRL_BUSY`
736			`[31:31]`
737			`read-only`
738			`SPI busy flag`
739
740
741
742
743			`DATA`
744			`RX/TX data register`
745			`0x04`
746
747
748
749
750
751
752			`TWI`
753			`Two-wire interface controller`
754			`SPI`
755			`0xFFFFFFB0`
756
757			`TWI_FIRQ7`
758
759
760			`0`
761			`0x08`
762			`registers`
763
764
765
766
767			`CTRL`
768			`Control register`
769			`0x00`
770
771
772			`TWI_CTRL_EN`
773			`[0:0]`
774			`TWI enable flag`
775
776
777			`TWI_CTRL_START`
778			`[1:1]`
779			`Generate START condition, auto-clears`
780
781
782			`TWI_CTRL_STOP`
783			`[2:2]`
784			`Generate STOP condition, auto-clears`
785
786
787			`TWI_CTRL_PRSC`
788			`[5:3]`
789			`Clock prescaler select`
790
791
792			`TWI_CTRL_MACK`
793			`[6:6]`
794			`Generate ACK by controller for each transmission`
795
796
797			`TWI_CTRL_ACK`
798			`[30:30]`
799			`read-only`
800			`ACK received when set`
801
802
803			`TWI_CTRL_BUSY`
804			`[31:31]`
805			`read-only`
806			`Transfer in progress, busy flag`
807
808
809
810
811			`DATA`
812			`RX/TX data register`
813			`0x04`
814
815
816			`TWI_DATA`
817			`[7:0]`
818			`RX/TX data`
819
820
821
822
823
824
825
826
827			`TRNG`
828			`True random number generator`
829			`TRNG`
830			`0xFFFFFFB8`
831
832
833			`0`
834			`0x04`
835			`registers`
836
837
838
839
840			`CTRL`
841			`Control and data register`
842			`0x00`
843
844
845			`TRNG_CTRL_DATA`
846			`[7:0]`
847			`read-only`
848			`Random data`
849
850
851			`TRNG_CTRL_EN`
852			`[30:30]`
853			`TRNG enable flag`
854
855
856			`TRNG_CTRL_VALID`
857			`[31:31]`
858			`read-only`
859			`Random data output valid`
860
861
862
863
864
865
866
867
868			`WDT`
869			`Watchdog timer`
870			`WDT`
871			`0xFFFFFFBC`
872
873			`WDT_FIRQ0`
874
875
876			`0`
877			`0x04`
878			`registers`
879
880
881
882
883			`CTRL`
884			`Control register`
885			`0x00`
886
887
888			`WDT_CTRL_EN`
889			`[0:0]`
890			`WDT enable flag`
891
892
893			`WDT_CTRL_CLK_SEL`
894			`[3:1]`
895			`Clock prescaler select`
896
897
898			`WDT_CTRL_MODE`
899			`[4:4]`
900			`Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset`
901
902
903			`WDT_CTRL_RCAUSE`
904			`[5:5]`
905			`read-only`
906			`Cause of last system reset: 0=external reset, 1=watchdog`
907
908
909			`WDT_CTRL_RESET`
910			`[6:6]`
911			`Reset WDT counter when set, auto-clears`
912
913
914			`WDT_CTRL_FORCE`
915			`[7:7]`
916			`Force WDT action, auto-clears`
917
918
919			`WDT_CTRL_LOCK`
920			`[8:8]`
921			`Lock write access to control register, clears on reset (HW or WDT) only`
922
923
924			`WDT_CTRL_DBEN`
925			`[9:9]`
926			`Allow WDT to continue operation even when in debug mode`
927
928
929			`WDT_CTRL_HALF`
930			`[10:10]`
931			`read-only`
932			`Set if at least half of the max. timeout counter value has been reached`
933
934
935
936
937
938
939
940
941			`GPIO`
942			`General purpose input/output port`
943			`GPIO`
944			`0xFFFFFFc0`
945
946
947			`0`
948			`0x10`
949			`registers`
950
951
952
953
954			`INPUT_LO`
955			`Parallel input register - low`
956			`0x00`
957			`read-only`
958
959
960			`INPUT_HI`
961			`Parallel input register - high`
962			`0x04`
963			`read-only`
964
965
966			`OUTPUT_LO`
967			`Parallel output register - low`
968			`0x08`
969
970
971			`OUTPUT_HI`
972			`Parallel output register - high`
973			`0x0C`
974
975
976
977
978
979
980			`NEOLED`
981			`Smart LED hardware interface`
982			`NEOLED`
983			`0xFFFFFFD8`
984
985			`NEOLED_FIRQ9`
986
987
988			`0`
989			`0x08`
990			`registers`
991
992
993
994
995			`CTRL`
996			`Control register`
997			`0x00`
998
999
1000			`NEOLED_CTRL_EN`
1001			`[0:0]`
1002			`NEOLED enable flag`
1003
1004
1005			`NEOLED_CTRL_MODE`
1006			`[1:1]`
1007			`TX mode (0=24-bit, 1=32-bit)`
1008
1009
1010			`NEOLED_CTRL_STROBE`
1011			`[2:2]`
1012			`Strobe (0=send normal data, 1=send RESET command on data write)`
1013
1014
1015			`NEOLED_CTRL_PRSC`
1016			`[5:3]`
1017			`Clock prescaler select`
1018
1019
1020			`NEOLED_CTRL_BUFS`
1021			`[9:6]`
1022			`read-only`
1023			`log2(tx buffer size)`
1024
1025
1026			`NEOLED_CTRL_T_TOT`
1027			`[14:10]`
1028			`pulse-clock ticks per total period bit`
1029
1030
1031			`NEOLED_CTRL_T_ZERO_H`
1032			`[19:15]`
1033			`pulse-clock ticks per ZERO high-time`
1034
1035
1036			`NEOLED_CTRL_T_ONE_H`
1037			`[24:20]`
1038			`pulse-clock ticks per ONE high-time`
1039
1040
1041			`NEOLED_CTRL_IRQ_CONF`
1042			`[27:27]`
1043			`TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty`
1044
1045
1046			`NEOLED_CTRL_TX_EMPTY`
1047			`[28:28]`
1048			`read-only`
1049			`TX FIFO is empty`
1050
1051
1052			`NEOLED_CTRL_TX_HALF`
1053			`[29:29]`
1054			`read-only`
1055			`TX FIFO is at least half-full`
1056
1057
1058			`NEOLED_CTRL_TX_FULL`
1059			`[30:30]`
1060			`read-only`
1061			`TX FIFO is full`
1062
1063
1064			`NEOLED_CTRL_TX_BUSY`
1065			`[31:31]`
1066			`read-only`
1067			`busy flag`
1068
1069
1070
1071
1072			`DATA`
1073			`Data register`
1074			`0x04`
1075
1076
1077
1078
1079
1080
1081			`SYSINFO`
1082			`System configuration information memory`
1083			`SYSINFO`
1084			`0xFFFFFFE0`
1085
1086
1087			`0`
1088			`0x20`
1089			`registers`
1090
1091
1092
1093
1094			`CLK`
1095			`Clock speed in Hz`
1096			`0x00`
1097			`read-only`
1098
1099
1100			`CPU`
1101			`CPU core features`
1102			`0x04`
1103			`read-only`
1104
1105			`SYSINFO_CPU_ZICSR[0:0]Zicsr extension (I sub-extension) available when set`
1106			`SYSINFO_CPU_ZIFENCEI[1:1]Zifencei extension (I sub-extension) available when set`
1107			`SYSINFO_CPU_ZMMUL[2:2]Zmmul extension (M sub-extension) available when set`
1108			`SYSINFO_CPU_ZFINX[5:5]Zfinx extension (F sub-/alternative-extension) available when set`
1109			`SYSINFO_CPU_ZXSCNT[6:6]Custom extension - Small CPU counters`
1110			`SYSINFO_CPU_ZICNTR[7:7]Basic CPU counters available when set`
1111			`SYSINFO_CPU_PMP[8:8]PMP (physical memory protection) extension available when set`
1112			`SYSINFO_CPU_ZIHPM[9:9]HPM (hardware performance monitors) extension available when set`
1113			`SYSINFO_CPU_DEBUGMODE[10:10]RISC-V CPU debug mode available when set`
1114			`SYSINFO_CPU_FASTMUL[30:30]fast multiplications (via FAST_MUL_EN generic) available when set`
1115			`SYSINFO_CPU_FASTSHIFT[31:31]fast shifts (via FAST_SHIFT_EN generic) available when set`
1116
1117
1118
1119			`SOC`
1120			`SoC features`
1121			`0x08`
1122			`read-only`
1123
1124			`SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented`
1125			`SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented`
1126			`SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented`
1127			`SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented`
1128			`SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order`
1129			`SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented`
1130			`SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated`
1131			`SYSINFO_SOC_OCD[14:14]On-chip debugger implemented`
1132			`SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented`
1133			`SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented`
1134			`SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented`
1135			`SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented`
1136			`SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented`
1137			`SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented`
1138			`SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented`
1139			`SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented`
1140			`SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented`
1141			`SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented`
1142			`SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented`
1143			`SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented`
1144			`SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented`
1145			`SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented`
1146			`SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented`
1147
1148
1149
1150			`CACHE`
1151			`Cache configuration`
1152			`0x0C`
1153			`read-only`
1154
1155			`SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes)`
1156			`SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines)`
1157			`SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity)`
1158			`SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)`
1159
1160
1161
1162			`ISPACE_BASE`
1163			`Instruction memory address space base address`
1164			`0x10`
1165			`read-only`
1166
1167
1168			`DSPACE_BASE`
1169			`Data memory address space base address`
1170			`0x14`
1171			`read-only`
1172
1173
1174			`IMEM_SIZE`
1175			`Internal instruction memory (IMEM) size in bytes`
1176			`0x18`
1177			`read-only`
1178
1179
1180			`DMEM_SIZE`
1181			`Internal data memory (DMEM) size in bytes`
1182			`0x1C`
1183			`read-only`
1184
1185
1186
1187
1188
1189