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ndumitrach |
//////////////////////////////////////////////////////////////////////////////////
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//
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// This file is part of the Next186 project
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// http://opencores.org/project,next186
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//
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// Filename: Next186_ALU.v
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// Description: Part of the Next186 CPU project, arithmetic-logic unit and effective address unit implementation
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// Version 1.0
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// Creation date: 11Apr2011 - 07Jun2011
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//
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// Author: Nicolae Dumitrache
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// e-mail: ndumitrache@opencores.org
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//
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/////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2011 Nicolae Dumitrache
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//
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///////////////////////////////////////////////////////////////////////////////////
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// Additional Comments:
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//
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// ADD 00_000
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// OR 00_001
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// ADC 00_010
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// SBB 00_011
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// AND 00_100
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// SUB 00_101
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// XOR 00_110
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// CMP 00_111
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//
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// INC 01_000
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// DEC 01_001
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// NOT 01_010
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// NEG 01_011
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// DAA 01_100 // +0066h
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// DAS 01_101 // -0066h
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// AAA 01_110 // +0106h
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// AAS 01_111 // -0106h
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//
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// MUL 10_000
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// IMUL 10_001
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//
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// FLAGOP 11_001
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// CBW 11_010
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// CWD 11_011
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// SHF/ROT 1 11_100
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// SHF/ROT n 11_101
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// PASS FLAGS 11_110 // ALUOP <- FLAGS, clear TF, IF
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// PASS RB 11_111 // ALUOP <- RB, FLAGS <- RA
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//
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//
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// FLAGS: X X X X OF DF IF TF | SF ZF X AF X PF X CF
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//
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9 |
ndumitrach |
// 09Feb2013 - fixed DAA,DAS bug
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16 |
ndumitrach |
// 07Jul2013 - fixed OV/CY flags for IMUL
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2 |
ndumitrach |
//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module Next186_ALU(
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input [15:0] RA,
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input [15:0] RB,
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input [15:0] TMP16,
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input [15:0] FETCH23,
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input [15:0]FIN,
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input [4:0]ALUOP,
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input [2:0]EXOP,
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input [3:0]FLAGOP,
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input WORD,
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input INC2,
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output reg [15:0]FOUT,
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output reg [15:0]ALUOUT,
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20 |
ndumitrach |
output [15:0]ALUOUTA,
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2 |
ndumitrach |
output reg ALUCONT,
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output NULLSHIFT,
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output COUT,
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input [2:0]STAGE,
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input CLK
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);
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reg CPLOP2;
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wire [15:0]SUMOP1 = ALUOP[3:1] == 3'b101 ? 16'h0000 : RA; // NEG, NOT
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reg [15:0]SUMOP21;
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wire [15:0]SUMOP2 = CPLOP2 ? ~SUMOP21 : SUMOP21;
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wire SCIN1 = ALUOP[3:1] == 3'b001 ? FIN[0] : ALUOP[3:0] == 4'b1010 ? 1'b1 : 1'b0; //ADD/ADC, NOT
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wire SCIN = CPLOP2 ? ~SCIN1 : SCIN1; // carry in
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wire SC16OUT;
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wire SC8OUT;
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wire AF;
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wire [15:0]SUMOUT;
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wire parity = ~^ALUOUT[7:0];
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wire zero8 = ~|ALUOUT[7:0];
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wire zero = ~|ALUOUT[15:0];
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wire overflow8 = (SUMOP1[7] & SUMOP2[7] & !SUMOUT[7]) | (!SUMOP1[7] & !SUMOP2[7] & SUMOUT[7]);
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wire overflow = (SUMOP1[15] & SUMOP2[15] & !SUMOUT[15]) | (!SUMOP1[15] & !SUMOP2[15] & SUMOUT[15]);
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9 |
ndumitrach |
wire LONIBBLE = (RA[3:0] > 4'h9) || FIN[4];
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wire HINIBBLE = (RA[7:0] > 8'h99) || FIN[0];
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2 |
ndumitrach |
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// ADDER
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assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
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assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
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assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
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assign COUT = (WORD ? SC16OUT : SC8OUT) ^ CPLOP2;
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20 |
ndumitrach |
assign ALUOUTA = ALUOP == 5'b11111 ? RB : SUMOUT;
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2 |
ndumitrach |
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// SHIFTER
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reg [4:0]SHNOPT; // optimized shift
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wire [4:0]SHN = {STAGE[2:1] ^ SHNOPT[4:3], SHNOPT[2:0]};
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assign NULLSHIFT = ~|SHNOPT;
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wire [2:0]COUNT = |SHN[4:3] ? 0 : SHN[2:0];
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wire [2:0]SCOUNT = (EXOP[0] ? COUNT[2:0] : 3'b000) - (EXOP[0] ? 3'b001 : COUNT[2:0]);
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reg [7:0]SHEX;
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wire [17:0]SHBAR = (EXOP[0] ? {1'bx, SHEX, WORD ? RA[15:8]: SHEX, RA[7:0]} : {RA, SHEX, 1'bx}) >> SCOUNT;
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// MULTIPLIER
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wire signed [16:0]MULOP1 = WORD ? {ALUOP[0] & TMP16[15], TMP16} : {ALUOP[0] ? {9{TMP16[7]}} : 9'b000000000, TMP16[7:0]};
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wire signed [16:0]MULOP2 = WORD ? {ALUOP[0] & FETCH23[15], FETCH23} : {ALUOP[0] ? {9{FETCH23[7]}} : 9'b000000000, FETCH23[7:0]};
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wire signed [31:0]MUL = MULOP1 * MULOP2;
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always @* begin
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FOUT[15:8] = {4'bxxxx, WORD ? overflow : overflow8, FIN[10:8]};
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FOUT[7] = WORD ? ALUOUT[15] : ALUOUT[7];
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FOUT[6] = WORD ? zero : zero8;
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FOUT[5] = 1'bx;
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FOUT[4] = AF ^ CPLOP2;
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FOUT[3] = 1'bx;
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FOUT[2] = parity;
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FOUT[1] = 1'bx;
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FOUT[0] = COUT;
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ALUOUT = 16'hxxxx;
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ALUCONT = 1'bx;
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case(ALUOP[3:0]) // complement second operand
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4'b0000, 4'b0010, 4'b1000, 4'b1100, 4'b1110: CPLOP2 = 1'b0; // ADD, ADC, INC, DEC, DAA, AAA
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default: CPLOP2 = 1'b1;
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endcase
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case(ALUOP[3:0])
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4'b1000, 4'b1001: SUMOP21 = INC2 && WORD ? 2 : 1; // INC/DEC
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4'b1100, 4'b1101: SUMOP21 = {9'b000000000, HINIBBLE, HINIBBLE, 2'b00, LONIBBLE, LONIBBLE, 1'b0};
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4'b1110, 4'b1111: SUMOP21 = {7'b0000000, LONIBBLE, 5'b00000, LONIBBLE, LONIBBLE, 1'b0};
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default: SUMOP21 = RB;
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endcase
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if(ALUOP[0])
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case({WORD, EXOP[2:1]})
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3'b000: SHNOPT = {2'b00, RB[2:0]};
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3'b001, 3'b101: SHNOPT = RB[4:0];
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3'b010, 3'b011: SHNOPT = |RB[4:3] ? 5'b01000 : RB[4:0];
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3'b100: SHNOPT = {1'b0, RB[3:0]};
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3'b110, 3'b111: SHNOPT = RB[4] ? 5'b10000 : RB[4:0];
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endcase
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else SHNOPT = 5'b00001;
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case({WORD, EXOP})
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4'b1000: SHEX = RA[15:8]; // ROL16
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4'b0010: SHEX = {FIN[0], RA[7:1]}; // RCL8
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4'b0011, 4'b1011: SHEX = {RA[6:0], FIN[0]}; // RCR8, RCR16
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4'b0111: SHEX = {8{RA[7]}}; // SAR8
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4'b0000, 4'b0001, 4'b1001: SHEX = RA[7:0]; // ROL8, ROR8, ROR16
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4'b1010: SHEX = {FIN[0], RA[15:9]}; // RCL16
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4'b1111: SHEX = {8{RA[15]}}; // SAR16
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default: SHEX = 8'h00; // SHL16, SHR16, SHL8, SHR8
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endcase
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case(ALUOP)
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5'b00000, 5'b00010, 5'b00011, 5'b00101, 5'b00111, 5'b01010, 5'b01011: ALUOUT = SUMOUT; // ADD, ADC, SBB, SUB, CMP, NOT, NEG
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5'b00001: begin // OR
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ALUOUT = RA | RB;
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FOUT[0] = 1'b0;
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FOUT[11] = 1'b0;
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FOUT[4] = FIN[4];
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end
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5'b00100: begin // AND
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ALUOUT = RA & RB;
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FOUT[0] = 1'b0;
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FOUT[11] = 1'b0;
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FOUT[4] = FIN[4];
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end
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5'b00110: begin // XOR
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ALUOUT = RA ^ RB;
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FOUT[0] = 1'b0;
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FOUT[11] = 1'b0;
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FOUT[4] = FIN[4];
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end
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5'b01000, 5'b01001: begin // INC, DEC
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ALUOUT = SUMOUT;
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FOUT[0] = FIN[0];
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end
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5'b01100, 5'b01101: begin // DAA, DAS
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ALUOUT = SUMOUT;
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9 |
ndumitrach |
FOUT[0] = HINIBBLE;
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FOUT[4] = LONIBBLE;
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2 |
ndumitrach |
end
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5'b01110, 5'b01111: begin // AAA, AAS
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ALUOUT = {SUMOUT[15:8], 4'b0000, SUMOUT[3:0]};
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FOUT[0] = LONIBBLE;
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FOUT[4] = LONIBBLE;
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end
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5'b10000, 5'b10001 : begin // MUL, IMUL
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ALUOUT = STAGE[1] ? MUL[31:16] : MUL[15:0];
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17 |
ndumitrach |
//07Jul2013 - fixed OV/CY flags for IMUL
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18 |
ndumitrach |
FOUT[0] = WORD ? MUL[31:16] != {16{MUL[15] & ALUOP[0]}} : MUL[15:8] != {8{MUL[7] & ALUOP[0]}};
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2 |
ndumitrach |
FOUT[11] = FOUT[0];
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end
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5'b11001: begin // flag op
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FOUT[11:8] = FIN[11:8];
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FOUT[7] = FIN[7];
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FOUT[6] = FIN[6];
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FOUT[4] = FIN[4];
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FOUT[2] = FIN[2];
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FOUT[0] = FIN[0];
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case(FLAGOP)
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4'b1000: FOUT[0] = 1'b0; // CLC
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4'b0101: FOUT[0] = !FIN[0]; // CMC
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4'b1001: FOUT[0] = 1'b1; // STC
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4'b1100: FOUT[10] = 1'b0; // CLD
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4'b1101: FOUT[10] = 1'b1; // STD
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4'b1010: FOUT[9] = 1'b0; // CLI
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default: FOUT[9] = 1'b1; // STI
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endcase
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end
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5'b11010: ALUOUT[7:0] = {8{RB[7]}};
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5'b11011: ALUOUT[15:0] = {16{RB[15]}};
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5'b11100, 5'b11101: begin // ROT/SHF
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ALUOUT = SHBAR[16:1];
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FOUT[0] = EXOP[0] ? SHBAR[0] : WORD ? SHBAR[17] : SHBAR[9];
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FOUT[11] = WORD ? RA[15] ^ ALUOUT[15] : RA[7] ^ ALUOUT[7]; // OF is defined only for 1bit rotate/shift
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if(!EXOP[2]) begin // ROT
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FOUT[7] = FIN[7];
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FOUT[6] = FIN[6];
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FOUT[4] = FIN[4];
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FOUT[2] = FIN[2];
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end
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case({SHN[4:3], STAGE[2:1]})
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4'b0100, 4'b1101, 4'b0110: ALUCONT = |SHN[2:0];
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4'b1000, 4'b1100, 4'b1001: ALUCONT = 1'b1;
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default: ALUCONT = 1'b0;
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endcase
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end
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5'b11110: begin
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ALUOUT = FIN;
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FOUT[11] = FIN[11];
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FOUT[9] = 1'b0; // IF
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| 265 |
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FOUT[8] = 1'b0; // TF
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FOUT[7] = FIN[7];
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| 267 |
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FOUT[6] = FIN[6];
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| 268 |
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FOUT[4] = FIN[4];
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FOUT[2] = FIN[2];
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FOUT[0] = FIN[0];
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end
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5'b11111: begin
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ALUOUT = RB;
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FOUT = {WORD ? RA[15:8] : FIN[15:8], RA[7:0]};
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end
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endcase
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end
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endmodule
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| 281 |
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// 0000 - BX+SI+DISP
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// 0001 - BX+DI+DISP
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| 283 |
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// 0010 - BP+SI+DISP
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| 284 |
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// 0011 - BP+DI+DISP
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| 285 |
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// 0100 - SI+DISP
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| 286 |
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// 0101 - DI+DISP
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| 287 |
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// 0110 - BP+DISP
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| 288 |
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// 0111 - BX+DISP
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| 289 |
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// 1000 - SP-2
|
| 290 |
|
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// 1001 - SP+2
|
| 291 |
|
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// 1010 - BX+AL
|
| 292 |
|
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// 1011 - TMP16+2
|
| 293 |
|
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// 1100 -
|
| 294 |
|
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// 1101 - SP+2+DISP
|
| 295 |
|
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// 1110 - DISP[7:0]<<2
|
| 296 |
20 |
ndumitrach |
// 1111 -
|
| 297 |
2 |
ndumitrach |
module Next186_EA(
|
| 298 |
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input [15:0] SP,
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| 299 |
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input [15:0] BX,
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| 300 |
|
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input [15:0] BP,
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| 301 |
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input [15:0] SI,
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| 302 |
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input [15:0] DI,
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| 303 |
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input [15:0] TMP16,
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| 304 |
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input [7:0] AL,
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| 305 |
|
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input [15:0] AIMM,
|
| 306 |
|
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input [3:0]EAC,
|
| 307 |
|
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output [15:0] ADDR16
|
| 308 |
|
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);
|
| 309 |
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|
|
| 310 |
|
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reg [15:0]OP1;
|
| 311 |
|
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reg [15:0]OP2;
|
| 312 |
|
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reg [15:0]OP3;
|
| 313 |
|
|
|
| 314 |
|
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always @* begin
|
| 315 |
|
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case(EAC)
|
| 316 |
|
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4'b0000, 4'b0001, 4'b0111, 4'b1010: OP1 = BX;
|
| 317 |
|
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4'b0010, 4'b0011, 4'b0110: OP1 = BP;
|
| 318 |
|
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4'b1000, 4'b1001, 4'b1101: OP1 = SP;
|
| 319 |
|
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4'b1011: OP1 = TMP16;
|
| 320 |
|
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default: OP1 = 16'h0000;
|
| 321 |
|
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endcase
|
| 322 |
|
|
case(EAC)
|
| 323 |
|
|
4'b0000, 4'b0010, 4'b0100: OP2 = SI;
|
| 324 |
|
|
4'b0001, 4'b0011, 4'b0101: OP2 = DI;
|
| 325 |
|
|
4'b1001, 4'b1011, 4'b1101: OP2 = 16'h0002; // SP/TMP16 + 2
|
| 326 |
|
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default: OP2 = 16'h0000;
|
| 327 |
|
|
endcase
|
| 328 |
|
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case(EAC)
|
| 329 |
|
|
4'b1000: OP3 = 16'hfffe; // SP - 2
|
| 330 |
|
|
4'b1010: OP3 = {8'b00000000, AL}; // XLAT
|
| 331 |
|
|
4'b1001, 4'b1011: OP3 = 16'h0000; // SP/TMP16 + 2
|
| 332 |
|
|
4'b1110: OP3 = {6'b000000, AIMM[7:0], 2'b00}; // int
|
| 333 |
|
|
default: OP3 = AIMM;
|
| 334 |
|
|
endcase
|
| 335 |
|
|
end
|
| 336 |
|
|
|
| 337 |
|
|
assign ADDR16 = OP1 + OP2 + OP3;
|
| 338 |
|
|
endmodule
|
