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//////////////////////////////////////////////////////////////////////////////////

//

// This file is part of the Next186 project

// http://opencores.org/project,next186

//

// Filename: Next186_CPU.v

// Description: Implementation of 80186 instruction compatible CPU

// Version 1.0

// Creation date: 24Mar2011 - 07Jun2011

//

// Author: Nicolae Dumitrache 

// e-mail: ndumitrache@opencores.org

//

/////////////////////////////////////////////////////////////////////////////////

// 

// Copyright (C) 2011 Nicolae Dumitrache

// 

// This source file may be used and distributed without 

// restriction provided that this copyright statement is not 

// removed from the file and that any derivative work contains 

// the original copyright notice and the associated disclaimer.

// 

// This source file is free software; you can redistribute it 

// and/or modify it under the terms of the GNU Lesser General 

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any 

// later version. 

// 

// This source is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied 

// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

// PURPOSE. See the GNU Lesser General Public License for more 

// details. 

// 

// You should have received a copy of the GNU Lesser General 

// Public License along with this source; if not, download it 

// from http://www.opencores.org/lgpl.shtml 

// 

///////////////////////////////////////////////////////////////////////////////////

//

// Comments:

// This project was developed and tested on a XILINX Spartan3AN board.

//

//      Next186 processor features:

//              All 80186 intstructions are implemented according with the 80186 specifications (excepting ENTER instruction, 

//              which uses always 0 as the second parameter - level).

//              Designed with 2 buses: 16bit/20bit data/data_address and 48bit/20bit instruction/instruction_address.

//              This allows most instructions to be executed in one clock cycle.

//              In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by

//              a dedicated bus interface unit (BIU).

//              It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.

//              Small size, the CPU + BIU requires ~25%  or 1500 slices - on Spartan XC3S700AN

// 

//      16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item

// 23Dec2012 - fixed DIV bug (exception on sign bit)

// 27Feb2013 - fixed MUL/IMUL 8bit flags bug

// 03Apr2013 - fix RET n alignment bug

// 04Apr2013 - fix TRAP interrupt acknowledge

// 12Apr2013 - fix IDIV when Q=0

///////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module Next186_CPU(

    output [19:0] ADDR,

    input [15:0] DIN,

    output [15:0] DOUT,

         input CLK,

         input CE,

         input INTR,

         input NMI,

         input RST,

         output reg MREQ,

         output wire IORQ,

         output reg INTA,

         output reg WR,

         output reg WORD,

         output LOCK,

         output [19:0]IADDR,

         input [47:0]INSTR,

         output reg IFETCH,

         output FLUSH,

         output reg [2:0]ISIZE,

         output reg HALT

    );

// connections  

        wire [15:0]RA;

        wire [15:0]RB;

        wire [15:0]TMP16;

        wire [15:0]SP;

        wire [15:0]IP;

        wire [15:0]AX;

        wire [15:0]BX;

        wire [15:0]BP;

        wire [15:0]SI;

        wire [15:0]DI;

        wire [15:0]DX;

        wire [15:0]FLAGS;

        wire [15:0]FIN;

        wire [15:0]ALUOUT;

        wire [15:0]AIMM1;

        reg [15:0]DIMM1;

        wire [15:0]RS;

        wire [15:0]ADDR16;

        wire [15:0]CS;

        wire ALUCONT;

        wire NULLSHIFT;

        wire [1:0]CXZ;

        wire COUT; // adder carry out

        wire DIVEXC; // exit carry for unsigned DIV 

// Registers

        reg [7:0]FETCH[5:0];

        reg [6:0]STAGE = 0;

        reg [5:0]CPUStatus = 0;   //1:0=SR override, 2=override ON/OFF, 3=Z(REP), 4=REP ON/OFF, 5=LOCK

        reg TZF = 0, TLF = 0;

        reg SRST = 0;

        reg SNMI = 0, FNMI = 0;

        reg SINTR = 0;

        reg [15:0]CRTIP; // current instruction ptr (used by interrupts)

        reg DIVQSGN;

        reg RDIVEXC;

// control      

        reg [2:0]RASEL;

        reg [2:0]RBSEL;

        reg BASEL;

        reg [1:0]BBSEL;

        reg [1:0]RSSEL;

        reg [4:0]WE; // 4=flags, 3=TMP16, 2=RSSEL, 1=RASEL_HI, 0=RASEL_LO

        reg [4:0]ALUOP;

        reg [3:0]EAC;

        reg [1:0]DISEL;

        reg [1:0]ISEL;

        reg ASEL;

        reg AEXT;

        reg DEXT;

        reg [1:0]DOSEL;

        reg IPWSEL;

        reg [5:0]status; //1:0=SR override, 2=override ON/OFF, 3=Z(REP), 4=REP ON/OFF, 5=lock

        reg NOBP;

        reg ALUSTAGE;   // inc STAGE with 2

        reg DIVSTAGE;  // inc STAGE with 4

        reg DISP16;

        reg DECCX;

        reg IRQ;

        reg [2:0]IRQL;

        reg REPINT;

        reg [5:0]ICODE1 = 23;

        reg NULLSEG;

        reg DIVOP;

// signals

        assign IORQ = &EAC;

        assign LOCK = CPUStatus[5];

        assign FLUSH = ~IPWSEL || (ISIZE == 3'b000);

        wire [15:0]IPADD = ISIZE == 3'b000 ? CRTIP : IP + ISIZE;

        wire [15:0]IPIN = IPWSEL ? IPADD : ALUOUT;

        wire [1:0]MOD = FETCH[1][7:6];

        wire [2:0]REG = FETCH[1][5:3];

        wire [2:0]RM  = FETCH[1][2:0];

        wire USEBP = RM[1] && ~&RM;

        wire POP = {EAC[3], EAC[1:0]} == 3'b101;

        wire [15:0]ADDR16_SP = POP ? SP : ADDR16;

        wire [1:0]WBIT = {WORD | RASEL[2], WORD | !RASEL[2]};

        wire [1:0]ISELS = {DISP16 | AEXT, DISP16 | ~AEXT};

        wire [2:0]ISIZES = DISP16 ? 4 : AEXT ? 3 : 2;

        reg  [2:0]ISIZEW;

        reg  [2:0]ISIZEI;        // ise imm

        wire [1:0]WRBIT = WR ? 2'b00 : WBIT;

        wire RCXZ = CPUStatus[4] && ~|CXZ;

        wire NRORCXLE1 = ~CPUStatus[4] || ~CXZ[1];

        wire [7:0]JMPC = {(FLAGS[7] ^ FLAGS[11]) | FLAGS[6], FLAGS[7] ^ FLAGS[11], FLAGS[2], FLAGS[7], FLAGS[0] | FLAGS[6], FLAGS[6], FLAGS[0], FLAGS[11]};

        wire [3:0]LOOPC = {CXZ != 2'b00, CXZ == 2'b01, CXZ == 2'b01 || !FLAGS[6], CXZ == 2'b01 || FLAGS[6]};

        wire IDIV = FETCH[0][1] & FETCH[1][3];

        wire DIVRSGN = (WORD ? FETCH[3][7] : FETCH[2][7]) & IDIV;

        wire DIVSGN = DIVQSGN ^ DIVRSGN;

        wire DIVEND = FETCH[0][0] ? STAGE[6] : STAGE[5];

        wire DIVC = ((COUT & ~RDIVEXC) ^ ~DIVRSGN);

        wire QSGN = (WORD ? DX[15] : AX[15]) & IDIV;

// interrupts

        wire SAMPLEINT = ~(WE[2] & RASEL[1:0] == 2'b10) & ~status[2] & ~status[4] & ~status[5]; // not load SS, no prefix

        wire NMIACK = SNMI & ~FNMI;     // NMI acknowledged

        wire INTRACK = FLAGS[9] & (~WE[4] | FIN[9]) & SINTR;                    // INTR acknowledged (IF and not CLI in progress)

        wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK | (~HALT & FLAGS[8]))); // interrupt acknowledged (fixed 04Apr2013)

        reg CMPS;       // early EQ test for CMPS

        reg SCAS;   // early EQ test for SCAS

        Next186_Regs REGS (

    .RASEL(RASEL),

    .RBSEL(RBSEL),

    .BASEL(BASEL),

    .BBSEL(BBSEL),

    .RSSEL(RSSEL),

    .DIN(DIN),

         .ALUOUT(ALUOUT),

         .ADDR16(ADDR16),

         .DIMM(DEXT ? {{8{DIMM1[7]}}, DIMM1[7:0]} : DIMM1),

    .WE(WE),

         .IFETCH(IFETCH),

    .RA(RA),

    .RB(RB),

    .TMP16(TMP16),

    .SP(SP),

    .IP(IP),

         .AX(AX),

         .BX(BX),

         .BP(BP),

         .SI(SI),

         .DI(DI),

         .DX(DX),

         .RS(RS),

         .FIN(FIN),

         .FOUT(FLAGS),

         .DISEL(DISEL),

         .WORD(WORD | &DISEL),

         .IPIN(IPIN),

         .CLK(CLK),

         .CLKEN(CE),

         .CS(CS),

         .INCSP(POP),

         .CXZ(CXZ),

         .DECCX(DECCX),

         .DIVOP(DIVOP),

         .DIVEND(DIVEND),

         .DIVSGN(DIVSGN),

         .DIVC(DIVC),

         .DIVEXC(DIVEXC)

    );

        Next186_ALU ALU16 (

         .RA(DOSEL == 2'b01 ? IPADD : RA),

         .RB(RB),

         .TMP16(TMP16),

         .FETCH23({FETCH[3], FETCH[2]}),

         .FIN(FLAGS),

         .FOUT(FIN),

         .ALUOP(ALUOP),

         .EXOP(FETCH[1][5:3]),

         .FLAGOP(FETCH[0][3:0]),

         .ALUOUT(ALUOUT),

         .WORD(WORD),

         .ALUCONT(ALUCONT),

         .NULLSHIFT(NULLSHIFT),

         .STAGE(STAGE[2:0]),

         .INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD

         .COUT(COUT),

         .CLK(CLK)

         );

        Next186_EA EA (

    .SP(SP),

    .BX(BX),

    .BP(NOBP ? 16'h0000 : BP),

    .SI(SI),

    .DI(DI),

         .PIO(FETCH[0][3] ? DX : {8'h00, FETCH[1]}),

         .TMP16(TMP16),

         .AL(AX[7:0]),

    .AIMM(AEXT ? {{8{AIMM1[7]}}, AIMM1[7:0]} : (DISP16 ? AIMM1 : 16'h0000)),

    .ADDR16(ADDR16),

         .EAC(EAC)

    );

         assign DOUT = DOSEL[1] ? DOSEL[0] ? AX : TMP16 : DOSEL[0] ? IPADD : ALUOUT;

         assign ADDR = {{NULLSEG ? 16'h0000 : RS} + {4'b0000, ADDR16_SP[15:4]}, ADDR16_SP[3:0]};

         assign IADDR = {CS + {4'b0000, IPIN[15:4]}, IPIN[3:0]};

         assign AIMM1 = ASEL ? {FETCH[3], FETCH[2]} : {FETCH[2], FETCH[1]};

         always @(posedge CLK)

                if(CE) begin

                        if(SRST) begin          // reset

//                              FETCH[0] <= 8'h0f;

                                FETCH[0][0] <= 1'b1; // for word=1

                                ICODE1 <= 54;

                                FETCH[5][1:0] <= 2'b01;  // RESET

                                STAGE <= 4'b1000;

                        end else begin

                                if(IACK & (IFETCH | HALT | REPINT)) begin // interrupt sampled and acknowledged

                                        FETCH[0][1:0] <= 2'b11;

                                        ICODE1 <= 54;

                                        STAGE <= 4'b1000;

                                        FETCH[5][2:0] <= {HALT, 2'b00};

                                        if(IRQ) FETCH[2] <= IRQL != 3'b010 ? {5'b00000, IRQL} : FETCH[1];

                                        else if(NMIACK) begin

                                                FETCH[2] <= 8'h02;

                                                FNMI <= 1'b1;

                                        end else if(INTRACK) FETCH[5][1:0] <= 2'b10;

                                        else FETCH[2] <= 8'h01; // trap

                                end else if(IFETCH) begin               // no interrupt, fetch

                                        FETCH[5] <= INSTR[47:40];

                                        FETCH[4] <= INSTR[39:32];

                                        FETCH[3] <= INSTR[31:24];

                                        FETCH[2] <= INSTR[23:16];

                                        FETCH[1] <= INSTR[15:8];

                                        FETCH[0] <= INSTR[7:0];

                                        STAGE <= 0;

                                        CPUStatus[5:0] <= status[5:0];

                                        ICODE1 <= ICODE(INSTR[7:0]);

                                end else begin          // no interrupt, no fetch

                                        STAGE <= STAGE + {DIVSTAGE, ALUSTAGE} + 1;

                                        if(&DOSEL) {FETCH[3], FETCH[2]} <= |DISEL ? DIN : RB;

                                        TZF <= FIN[6];          // zero flag for BOUND

                                        TLF <= FIN[7] != FIN[11];       // less flag for BOUND

                                end

                        end

                        if(IFETCH & ~status[2] & ~status[4] & ~status[5]) CRTIP <= IPIN; // no prefix

                        SRST <= RST;                            // level detection RST

                        SINTR <= INTR;                          // level detection INTR

                        if(NMI) SNMI <= 1'b1;   // edge detection NMI

                        else if(FNMI) begin

                                SNMI <= 1'b0;

                                FNMI <= 1'b0;

                        end

                        if(~|STAGE[1:0]) DIVQSGN <= QSGN;

                        RDIVEXC <= DIVOP & DIVEXC & ~IDIV; // bit 8/16 for unsigned DIV

                        CMPS <= (~FETCH[0][0] | (FETCH[3] == DIN[15:8])) & (FETCH[2] == DIN[7:0]); // early EQ test for CMPS

                        SCAS <= (~FETCH[0][0] | (AX[15:8] == DIN[15:8])) & (AX[7:0] == DIN[7:0]);  // early EQ test for SCAS

                end

        always @(ISEL, FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5])

                case(ISEL)

                        2'b00: DIMM1 = {FETCH[2], FETCH[1]};

                        2'b01: DIMM1 = {FETCH[3], FETCH[2]};

                        2'b10: DIMM1 = {FETCH[4], FETCH[3]};

                        2'b11: DIMM1 = {FETCH[5], FETCH[4]};

                endcase

        always @(FETCH[0], WORD, DISP16, AEXT) begin

                case({WORD, DISP16, AEXT})

                        3'b000: ISIZEW = 3;

                        3'b001, 3'b100: ISIZEW = 4;

                        3'b010, 3'b101: ISIZEW = 5;

                        default: ISIZEW = 6;

                endcase

                case({FETCH[0][1:0] == 2'b01, DISP16, AEXT})

                        3'b000: ISIZEI = 3;

                        3'b001, 3'b100: ISIZEI = 4;

                        3'b110: ISIZEI = 6;

                        default: ISIZEI = 5;

                endcase

        end

         always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,

                                 WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, FIN, IDIV, AX) begin

                WORD = FETCH[0][0];

                BASEL = FETCH[0][1] | &MOD;

                RASEL = FETCH[0][1] ? REG : RM; // destination

                BBSEL = {1'b0, !FETCH[0][1] | &MOD};

                RBSEL = FETCH[0][1] ? RM : REG; // source

                RSSEL = CPUStatus[2] ? CPUStatus[1:0] : (USEBP && !NOBP ? 2'b10 : 2'b11);

                WE = 5'b00000;          // 5=flags, 3=TMP16, 2=RSSEL, 1=RASEL_HI, 0=RASEL_LO

                ALUOP = 5'bxxxxx;

                EAC = {1'b0, RM};

                DISEL = 2'b01;          // ALU

                ISEL = 2'bxx;

                ASEL = 1'bx;

                AEXT = MOD == 2'b01;

                DEXT = 1'b0;

                DOSEL = 2'b00;  // ALU   

                MREQ = 1'b1;

                WR = 1'b0;

                ISIZE = 3'bxxx;

                IPWSEL = 1'b1;          // IP + ISIZE

                IFETCH = 1'b1;

                status = 6'b00x0xx;

                DISP16 = MOD == 2'b10 || NOBP;

                NOBP = {MOD, RM} == 5'b00110;

                HALT = 1'b0;

                INTA = 1'b0;

                ALUSTAGE = 1'b0;

                DIVSTAGE = 1'b0;

                DECCX = 1'b0;

                IRQ = 1'b0;

                IRQL = 3'b110;  // unused opcode

                REPINT = 1'b0;

                NULLSEG = 1'b0;

                DIVOP = 1'b0;

                case(ICODE1) // one hot synthesis

// --------------------------------  mov R/M to/from R/SR  --------------------------------

                        0: begin

                                if(FETCH[0][2]) WORD = 1'b1;

                                if(FETCH[0][2:1] == 2'b10) BBSEL = 2'b11; // RB = SR

                                ALUOP = 31;     // PASS B

                                DISEL = {1'b0, &MOD};

                                ASEL = 1'b1;

                                MREQ = ~&MOD;

                                WR = MREQ & !FETCH[0][1];

                                WE = WR ? 5'b00000 : &FETCH[0][2:1] ? {2'b00, FETCH[1][4:3] != 2'b01, 2'b00} : {3'b000, WBIT};           // RSSEL, RASEL_HI/RASEL_LO

                                ISIZE = ISIZES;

                        end

// --------------------------------  mov IMM to R/M  --------------------------------

                        1: begin

                                RASEL = RM; // destination

                                BBSEL = 2'b10;

                                ALUOP = 31;     // PASS B

                                ISEL = ISELS;

                                ASEL = 1'b1;

                                MREQ = ~&MOD;

                                WR = MREQ;

                                WE[1:0] = WRBIT;         // RASEL_HI/RASEL_LO

                                ISIZE = ISIZEW;

                        end

// --------------------------------  mov IMM to R --------------------------------

                        2: begin

                                WORD = FETCH[0][3];

                                RASEL = FETCH[0][2:0]; // destination

                                BBSEL = 2'b10;                          // imm

                                WE[1:0] = WBIT;          // RASEL_HI/RASEL_LO

                                ALUOP = 31;     // PASS B

                                ISEL = 2'b00;

                                MREQ = 1'b0;

                                ISIZE = WORD ? 3 : 2;

                        end

// --------------------------------  mov mem to/from ACC --------------------------------

                        3: begin

                                RASEL = 0; // ACC

                                BBSEL = 2'b01;          // reg

                                RBSEL = 0; // ACC

                                ALUOP = 31;     // PASS B

                                EAC = 4'b0110;

                                DISEL = 2'b00;

                                ASEL = 1'b0;

                                AEXT = 1'b0;

                                MREQ = 1'b1;

                                WR = FETCH[0][1];

                                WE[1:0] = WRBIT;         // IP, RASEL_HI/RASEL_LO

                                ISIZE = 3;

                                NOBP = 1'b1;

                        end

// --------------------------------  segment override prefix --------------------------------

                        4: begin

                                status = {CPUStatus[5:3], 1'b1, FETCH[0][4:3]};

                                MREQ = 1'b0;

                                ISIZE = 1;

                        end

// --------------------------------  rep prefix --------------------------------

                        5: begin

                                status = {CPUStatus[5], 1'b1, FETCH[0][0], CPUStatus[2:0]};

                                MREQ = 1'b0;

                                ISIZE = 1;

                        end

// --------------------------------  lock prefix --------------------------------

                        6: begin

                                status = {1'b1, CPUStatus[4:0]};

                                MREQ = 1'b0;

                                ISIZE = 1;

                        end

// --------------------------------  FF block --------------------------------

                        7:      begin

                                ISIZE = ISIZES;

                                case({FETCH[0][0], REG})

                // --------------------------------  push R/M --------------------------------

                                        4'b1110:

                                                if(!(&MOD || STAGE[0])) begin    // stage1, read data in TMP16

                                                        WE[3] = 1'b1;           // TMP16

                                                        DISEL = 2'b00;

                                                        ASEL = 1'b1;

                                                        IFETCH = 1'b0;

                                                end else begin          // stage2, push R/TMP16

                                                        RASEL = 3'b100;         // write SP

                                                        RSSEL = 2'b10;                  // SS

                                                        ALUOP = 31;     // PASS B

                                                        WE[1:0] = 2'b11;         // RASEL_HI/RASEL_LO

                                                        EAC = 4'b1000;                  // SP - 2

                                                        DISEL = 2'b10;                  // ADDR

                                                        WR = 1'b1;

                                                end

                // --------------------------------  inc/dec R/M --------------------------------

                                        4'b0000, 4'b1000, 4'b0001, 4'b1001: begin

                                                ASEL = 1'b1;

                                                if(!(&MOD || STAGE[0])) begin    // stage1, load op from memory in TMP16

                                                        WE[3] = 1'b1;           // TMP16

                                                        DISEL = 2'b00;                  // DIN

                                                        IFETCH = 1'b0;

                                                end else begin                                          // stage2, execute and write            

                                                        BASEL = &MOD;

                                                        RASEL = RM;                     // destination

                                                        ALUOP = {2'b01, FETCH[1][5:3]};

                                                        MREQ = ~BASEL;

                                                        WR = MREQ;

                                                        WE = {3'b100, WRBIT};           // flags, IP, RASEL_HI, RASEL_LO

                                                end

                                        end

                // --------------------------------  call/jmp near R/M --------------------------------

                                        4'b1010, 4'b1100: begin

                                                if(!STAGE[0] && ~&MOD) begin     // stage1, load op in TMP16

                                                        ASEL = 1'b1;

                                                        WE[3] = 1'b1;           // TMP16

                                                        DISEL = 2'b00;                  // DIN

                                                        IFETCH = 1'b0;

                                                end else begin          // stage2, push IP, jump

                                                        RASEL = 3'b100;         // write SP

                                                        RSSEL = 2'b10;          // SS

                                                        ALUOP = 31;     // PASS B

                                                        EAC = 4'b1000;          // SP - 2

                                                        DISEL = 2'b10;          // ADDR

                                                        DOSEL = 2'b01;  // IP    

                                                        MREQ = REG[1];

                                                        WR = MREQ;

                                                        WE[1:0] = {WR, WR};

                                                        IPWSEL = 1'b0;          // ALU

                                                end

                                        end

                // --------------------------------  call/jmp far R/M --------------------------------

                                        4'b1011, 4'b1101: begin

                                                ALUOP = 31;                             // PASS B

                                                IRQ = &MOD;

                                                case({STAGE[1:0], REG[1]})

                                                        3'b001: begin   // stage1, push CS

                                                                RASEL = 3'b100;         // write SP

                                                                BBSEL = 2'b11;