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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /   Vendor             : Xilinx

// \   \   \/    Version            : 3.6.1

//  \   \        Application        : MIG

//  /   /        Filename           : ddr_ram8d_0.v

// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $

// \   \  /  \   Date Created       : Mon May 2 2005

//  \___\/\___\

// Device       : Spartan-3/3A/3A-DSP

// Design Name  : DDR2 SDRAM

// Purpose      : This module instantiates RAM16X1 premitives. There will be 

//                8 or 4 RAM16X1 instances depending on the number of data bits 

//                per strobe.

//*****************************************************************************

`timescale 1ns/100ps

`include "../rtl/ddr_parameters_0.v"

module ddr_ram8d_0

  (

   output [(`DATABITSPERSTROBE -1):0] dout,

   input [3:0]                        waddr,

   input [(`DATABITSPERSTROBE -1):0]  din,

   input [3:0]                        raddr,

   input                              wclk0,

   input                              wclk1,

   input                              we

  );

   RAM16X1D fifo_bit0

     (

    .DPO (dout[0]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[0]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk1),

    .WE(we)

    );

   RAM16X1D fifo_bit1

     (

    .DPO (dout[1]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[1]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk0),

    .WE(we)

    );

   RAM16X1D fifo_bit2

     (

    .DPO (dout[2]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[2]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk1),

    .WE(we)

    );

   RAM16X1D fifo_bit3

     (

    .DPO (dout[3]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[3]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk0),

    .WE(we)

    );

   RAM16X1D fifo_bit4

     (

    .DPO (dout[4]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[4]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk1),

    .WE(we)

    );

   RAM16X1D fifo_bit5

     (

    .DPO (dout[5]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[5]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk0),

    .WE(we)

    );

   RAM16X1D fifo_bit6

     (

    .DPO (dout[6]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[6]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk1),

    .WE(we)

    );

   RAM16X1D fifo_bit7

     (

    .DPO (dout[7]),

    .A0(waddr[0]),

    .A1(waddr[1]),

    .A2(waddr[2]),

    .A3(waddr[3]),

    .D(din[7]),

    .DPRA0(raddr[0]),

    .DPRA1(raddr[1]),

    .DPRA2(raddr[2]),

    .DPRA3(raddr[3]),

    .SPO(),

    .WCLK(wclk0),

    .WE(we)

    );

  endmodule