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//   ____  ____

//  /   /\/   /

// /___/  \  /   Vendor             : Xilinx

// \   \   \/    Version            : 3.6.1

//  \   \        Application        : MIG

//  /   /        Filename           : ddr_s3_dm_iob_%controllerNo.v

// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $

// \   \  /  \   Date Created       : Mon May 2 2005

//  \___\/\___\

// Device       : Spartan-3/3A/3A-DSP

// Design Name  : DDR2 SDRAM

// Purpose      : This module has instantiation DDR IOB output flip-flops, 

//                and an output buffer for the data mask bits.

//*****************************************************************************

`timescale 1ns/100ps

module ddr_s3_dm_iob

  (

   input   mask_falling,

   input   mask_rising,

   input   clk90,

   output  ddr_dm

   );

   wire mask_o;

   wire gnd;

   wire vcc;

   assign gnd = 1'b0;

   assign vcc = 1'b1;

// Data Mask Output during a write command

   FDDRRSE  DDR2_DM0_OUT

     (

      .Q  (mask_o),

      .C0 (~clk90),

      .C1 (clk90),

      .CE (vcc),

      .D0 (mask_rising),

      .D1 (mask_falling),

      .R  (gnd),

      .S  (gnd)

      );

   OBUF  DM0_OBUF

      (

       .I (mask_o),

       .O (ddr_dm)

       );

endmodule