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[/] [nios2ci/] [trunk/] [bitops/] [fls.vhd] - Blame information for rev 2

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1 2 tklauser
--
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-- FLS - Find last (most-significant) set bit in word
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--
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-- Custom instruction for Nios II
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--
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-- Copyright (C) 2012 Tobias Klauser <tklauser@distanz.ch>
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE.  See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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  use ieee.numeric_std.all;
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entity fls is
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  port(
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    signal dataa  : in std_logic_vector(31 downto 0);
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    signal result : out std_logic_vector(31 downto 0)
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  );
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end entity fls;
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architecture rtl of fls is
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begin
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  process(dataa)
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    variable word : unsigned(result'range);
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    variable ret  : unsigned(result'range);
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  begin
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    ret := to_unsigned(33, ret'length);
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    for i in dataa'reverse_range loop
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      if dataa(i) = '1' then
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        ret := to_unsigned(i + 1, ret'length);
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      end if;
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    end loop;
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    result <= std_logic_vector(ret);
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  end process;
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end architecture rtl;

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