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<HTML><HEAD><TITLE>Welcome to nnARM home site</TITLE>
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News
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<font color=#ffffff face=Verdana,Arial,Helvetica,helvetica size=3>
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<b>
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2001.6.3 nnARM moved to Opencores<br>
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<b>
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<br>I have just got this account, and I will try to learn how to use CVS and other rules and procedures of Opencores.<br><br>
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Now it is more convenient for anyone interested in this project to take part in it. Please refer to the Introduction page for what types of help we need.
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<br><br><br><br>
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<b>
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2001.6.2 Some sections of documentation v1.10 are released<br>
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<b>
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<br>Because I will be busy in the following 2 weeks for other things, I can not find time to write the full documentation. However, I think a partial document is better than no documentation.<br>
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<br>A full version will be released later.
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<br><br><br><br>
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2001.5.30 I need help on memory system. Cache system and memory bus.<br>
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<br> The memory and cache system of my design are not very suitable for this processor. Because I want to devote myself to the design of the processor itself, I have used a VERY SIMPLE model of cache and memory. <br>
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<br>Whoever can help me to develop a better model please<a href="mailto:skli@nudt.edu.cn">contact me</a><br><br><br><br>
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2001.5.29 It runs some complex asembly source code from ARM SDT 2.5<br>
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<br> I used some assembly source code with ARM SDT 2.5. It runs very well and obtains good results. For more detail,please refer to <a href="./Testbench/Testbench.htm">TestBench</a><br><br><br><br>
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2001.5.24 The PC can now be used as a source and/or target register.<br>
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<br>Because the PC is not a general register, when an instruction reaches the EXE and MEM stage, the current PC is ahead of the PC of the current instruction by 8 or 12 bytes. So it can not be read to the EXE stage as a general register. Therefore, it is read at the decoder stage and then adjusted the proper amount and at last sent to the EXE stage as an immediate value.<br>
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<br>For the case of a write to the PC, it is treated as a Branch instruction.<br><br><br><br>
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2001.5.23 Support for Multiply and Multiply-Accumulate (MUL, MLA)<br>
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<br>These two instructions can do multiply and multiply and then add operations.<br><br><br><br>
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2001.5.21 Support for branch and branch with link<br>
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<br>These two instructions change the PC, and the later can write the next instruction address to R14 for return from subrutine.<br><br><br><br>
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2001.5.20 Support for MRS and MSR instruction<br>
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<br>These two instructions write CPSR/SPSR to and from general registers.<br><br><br><br>
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2001.5.17 Support for CPSR and SPSR read/write<br>
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<br>The two registers (actually six registers,including cpsr spsr_fiq spsr_und spsr_svc spsr_irq spsr_abt) can now be read/written, and the pipeline can use the condition code from cpsr to decide if an instruction can be executed.<br><br><br><br>
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2001.5.16 Brand New Architecture and support for Load/Store<br>
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<br>Since the last update a month ago, I am working hard to change the architecture of nnARM,the main reason is described as follows:<br>
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<br>When I started to develop this soft core,I thought that the ARM instruction set is very similar to the typical risc machine (such as DLX and MIPS.) Thus, I thought I could develop a RISC core to run various RISC instruction sets. This idea is not wrong for a typical RISC architecture, but it is wrong for ARM. When I pushed forward with the development, I found that the ARM instruction set is very different from typical RISC. It is difficult to run the ARM instruction set on it efficiently. So I designed a brand new architecture for ARM. And all functions that have been supported by the old architecture are also supported by the new architecture.<br>
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<br>At the same time, I added support for load and store instructions. <br><br><br><br>
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2001.4.17 Full Function ALU<br>
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<br>A new full function ALU has been released. It can support all ALU operations in the ARM instruction set. Its documentation is online now. <br><br><br><br>
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2001.4.15 A new Barrel Shifter<br>
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<br>I have written documentation for the first release of this synthesable soft core in the last week. Now, the documentation has been updated. I started to push forword with this project again tonight. I have written a new barrel shifter (in BarrelShift.v) and its test bench(in tb_BarrelShift.v). New documentation sections about the new Barrel Shifter are also online now.<br><br><br><br>
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2001.4.10 IT RUNS NOW!<br>
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<br>After 2 weeks of hard work, the processor now can run the ADD Instruction, but I know that it does have some limitations:<br>
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<br>FIRST:the tomasulo structure still can not tell the decoder that an instruction has completed, so that the decoder can clear the register usage.<br>
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<br>SECOND:the ALUWrapper still can not read from the write bus,so it can only get results from within ALUWrapper, only from the other entry.<br>
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<br>Except the above two limitations,it runs fairly well. <br><br><br><br>
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