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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : Inter_mv_decoding.v
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// Generated : May 25, 2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Decoding the motion vector x and motion vector y for Inter prediction and P_skip
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// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0]
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end,
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slice_data_state,mb_pred_state,sub_mb_pred_state,mvd,
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mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx,
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MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD,
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mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF,
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skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA,
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mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din,
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mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din,
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mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din,
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mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din,
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mv_is16x16,
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mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,
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mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3);
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input clk,reset_n;
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input Is_skip_run_entry;
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input Is_skip_run_end;
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input [3:0] slice_data_state;
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input [2:0] mb_pred_state;
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input [1:0] sub_mb_pred_state;
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input [7:0] mvd;
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input [6:0] mb_num;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input [3:0] mb_type_general;
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input [1:0] sub_mb_type;
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input end_of_MB_DEC;
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input [1:0] mbPartIdx,subMbPartIdx;
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input compIdx;
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input [1:0] MBTypeGen_mbAddrA;
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input MBTypeGen_mbAddrD;
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input [21:0] MBTypeGen_mbAddrB_reg;
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input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout;
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input [7:0] mvx_mbAddrC_dout,mvy_mbAddrC_dout;
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input mv_mbAddrB_rd_for_DF;
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output skip_mv_calc;
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output Is_skipMB_mv_calc;
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output [31:0] mvx_mbAddrA,mvy_mbAddrA;
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output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
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output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
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output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
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output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
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output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
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output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
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output mv_is16x16;
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output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
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reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
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reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
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reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
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reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
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reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
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reg mv_is16x16;
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reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy;
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reg [31:0] mvx_mbAddrA,mvy_mbAddrA;
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wire [7:0] mvx_mbAddrD,mvy_mbAddrD;
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reg [7:0] mvpx,mvpy,mvx,mvy;
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reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before
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//trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB
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always @ (posedge clk)
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if (reset_n == 1'b0)
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skip_mv_calc <= 1'b0;
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else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end)
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skip_mv_calc <= 1'b1;
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else
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skip_mv_calc <= 1'b0;
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wire Is_skipMB_mv_calc;
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assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc;
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reg [1:0] MBTypeGen_mbAddrB;
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reg [1:0] MBTypeGen_mbAddrC;
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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case (mb_num_h)
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1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
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2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
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3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
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4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
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5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
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6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
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7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
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8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
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9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
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10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
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default:MBTypeGen_mbAddrB <= 0;
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endcase
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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case (mb_num_h)
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0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2];
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1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4];
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2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6];
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3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8];
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4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10];
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5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12];
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6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14];
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7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16];
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8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18];
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9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20];
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default:MBTypeGen_mbAddrC <= 0;
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endcase
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wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard
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wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard
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reg refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard
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assign refIdxL0_A = (
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//P_skip
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(Is_skipMB_mv_calc ||
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//Inter16x16,Inter16x8,Inter8x16 left blk
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(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) ||
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//Inter8x8,left most blk
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(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && (
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sub_mb_type == 0 ||
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sub_mb_type == 1 ||
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(sub_mb_type == 2 && subMbPartIdx == 0) ||
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(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) &&
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(mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0;
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assign refIdxL0_B = (
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//P_skip
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(Is_skipMB_mv_calc ||
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//Inter16x16,Inter16x8 upper blk,Inter8x16
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(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) ||
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//Inter8x8,left most blk
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(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && (
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sub_mb_type == 0 ||
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sub_mb_type == 2 ||
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(sub_mb_type == 1 && subMbPartIdx == 0) ||
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(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) &&
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(mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0;
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always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h
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or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
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or refIdxL0_A or refIdxL0_B)
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//P_skip,Inter16x16
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if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16))
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begin
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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end
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//Inter16x8
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else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8)
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begin
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if (mbPartIdx == 0) //upper blk
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begin
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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end
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else //bottom blk
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refIdxL0_C <= refIdxL0_A;
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end
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//Inter8x16
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else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16)
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begin
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if (mbPartIdx == 0) //left blk
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refIdxL0_C <= refIdxL0_B;
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else //right blk
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begin
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if (mb_num_v == 0 || mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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end
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end
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//Inter8x8 and below
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else if (sub_mb_pred_state == `sub_mvd_l0_s)
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case (mbPartIdx)
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2'b00: //left-top 8x8 blk
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case (sub_mb_type)
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0:refIdxL0_C <= refIdxL0_B;
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1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A;
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2:refIdxL0_C <= refIdxL0_B;
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3:
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case (subMbPartIdx)
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0,1:refIdxL0_C <= refIdxL0_B;
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2,3:refIdxL0_C <= 1'b0;
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endcase
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endcase
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2'b01: //right-top 8x8 blk
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case (sub_mb_type)
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0: //8x8
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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1: //8x4
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if (subMbPartIdx == 0)
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begin
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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end
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else
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refIdxL0_C <= 1'b0;
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2: //4x8
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if (subMbPartIdx == 0) refIdxL0_C <= refIdxL0_B;
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else
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begin
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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end
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3: //4x4
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case (subMbPartIdx)
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0:refIdxL0_C <= refIdxL0_B;
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1:
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begin
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
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else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
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end
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2,3:refIdxL0_C <= 1'b0;
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endcase
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endcase
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2'b10: //left-bottom 8x8 blk
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case (sub_mb_type)
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0:refIdxL0_C <= 1'b0;
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1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A;
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2:refIdxL0_C <= 1'b0;
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3:refIdxL0_C <= 1'b0;
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endcase
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2'b11: //right-bottom 8x8 blk
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refIdxL0_C <= 1'b0;
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endcase
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else
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refIdxL0_C <= 1'b0;
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//-------------
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//mvpAx
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//-------------
|
255 |
|
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state
|
256 |
|
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
257 |
|
|
or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
258 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
259 |
|
|
//P_skip or Inter16x16
|
260 |
|
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
261 |
|
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
262 |
|
|
//Inter16x8
|
263 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
264 |
|
|
begin
|
265 |
|
|
if (mbPartIdx == 0)
|
266 |
|
|
mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0];
|
267 |
|
|
else
|
268 |
|
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
269 |
|
|
end
|
270 |
|
|
//Inter8x16
|
271 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
272 |
|
|
begin
|
273 |
|
|
if (mbPartIdx == 0)
|
274 |
|
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
275 |
|
|
else
|
276 |
|
|
mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8];
|
277 |
|
|
end
|
278 |
|
|
//Inter8x8
|
279 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) //sub_mb_pred
|
280 |
|
|
case (mbPartIdx)
|
281 |
|
|
0:
|
282 |
|
|
case (sub_mb_type)
|
283 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
284 |
|
|
1: //8x4
|
285 |
|
|
case (subMbPartIdx)
|
286 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
287 |
|
|
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
|
288 |
|
|
default:mvpAx <= 0;
|
289 |
|
|
endcase
|
290 |
|
|
2: //4x8
|
291 |
|
|
case (subMbPartIdx)
|
292 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
293 |
|
|
1:mvpAx <= mvx_CurrMb0[7:0];
|
294 |
|
|
default:mvpAx <= 0;
|
295 |
|
|
endcase
|
296 |
|
|
3: //4x4
|
297 |
|
|
case (subMbPartIdx)
|
298 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
299 |
|
|
1:mvpAx <= mvx_CurrMb0[7:0];
|
300 |
|
|
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
|
301 |
|
|
3:mvpAx <= mvx_CurrMb0[23:16];
|
302 |
|
|
endcase
|
303 |
|
|
endcase
|
304 |
|
|
1:
|
305 |
|
|
case (sub_mb_type)
|
306 |
|
|
0:mvpAx <= mvx_CurrMb0[15:8];
|
307 |
|
|
1: //8x4
|
308 |
|
|
case (subMbPartIdx)
|
309 |
|
|
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb0[31:24];
|
310 |
|
|
default:mvpAx <= 0;
|
311 |
|
|
endcase
|
312 |
|
|
2: //4x8
|
313 |
|
|
case (subMbPartIdx)
|
314 |
|
|
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb1[7:0];
|
315 |
|
|
default:mvpAx <= 0;
|
316 |
|
|
endcase
|
317 |
|
|
3: //4x4
|
318 |
|
|
case (subMbPartIdx)
|
319 |
|
|
0:mvpAx <= mvx_CurrMb0[15:8] ; 1:mvpAx <= mvx_CurrMb1[7:0];
|
320 |
|
|
2:mvpAx <= mvx_CurrMb0[31:24]; 3:mvpAx <= mvx_CurrMb1[23:16];
|
321 |
|
|
endcase
|
322 |
|
|
endcase
|
323 |
|
|
2:
|
324 |
|
|
case (sub_mb_type)
|
325 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
326 |
|
|
1: //8x4
|
327 |
|
|
case (subMbPartIdx)
|
328 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
329 |
|
|
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
|
330 |
|
|
default:mvpAx <= 0;
|
331 |
|
|
endcase
|
332 |
|
|
2: //4x8
|
333 |
|
|
case (subMbPartIdx)
|
334 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
335 |
|
|
1:mvpAx <= mvx_CurrMb2[7:0];
|
336 |
|
|
default:mvpAx <= 0;
|
337 |
|
|
endcase
|
338 |
|
|
3: //4x4
|
339 |
|
|
case (subMbPartIdx)
|
340 |
|
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
341 |
|
|
1:mvpAx <= mvx_CurrMb2[7:0];
|
342 |
|
|
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
|
343 |
|
|
3:mvpAx <= mvx_CurrMb2[23:16];
|
344 |
|
|
endcase
|
345 |
|
|
endcase
|
346 |
|
|
3:
|
347 |
|
|
case (sub_mb_type)
|
348 |
|
|
0:mvpAx <= mvx_CurrMb2[15:8];
|
349 |
|
|
1: //8x4
|
350 |
|
|
case (subMbPartIdx)
|
351 |
|
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb2[31:24];
|
352 |
|
|
default:mvpAx <= 0;
|
353 |
|
|
endcase
|
354 |
|
|
2: //4x8
|
355 |
|
|
case (subMbPartIdx)
|
356 |
|
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0];
|
357 |
|
|
default:mvpAx <= 0;
|
358 |
|
|
endcase
|
359 |
|
|
3: //4x4
|
360 |
|
|
case (subMbPartIdx)
|
361 |
|
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0];
|
362 |
|
|
2:mvpAx <= mvx_CurrMb2[31:24]; 3:mvpAx <= mvx_CurrMb3[23:16];
|
363 |
|
|
endcase
|
364 |
|
|
endcase
|
365 |
|
|
endcase
|
366 |
|
|
else
|
367 |
|
|
mvpAx <= 0;
|
368 |
|
|
|
369 |
|
|
//-------------
|
370 |
|
|
//mvpAy
|
371 |
|
|
//-------------
|
372 |
|
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state
|
373 |
|
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
374 |
|
|
or mvy_mbAddrA or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
375 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
376 |
|
|
//P_skip or Inter16x16
|
377 |
|
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
378 |
|
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
379 |
|
|
//Inter16x8
|
380 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
381 |
|
|
begin
|
382 |
|
|
if (mbPartIdx == 0)
|
383 |
|
|
mvpAy <= {8{refIdxL0_B}} & mvy_mbAddrA[7:0];
|
384 |
|
|
else
|
385 |
|
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
386 |
|
|
end
|
387 |
|
|
//Inter8x16
|
388 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
389 |
|
|
begin
|
390 |
|
|
if (mbPartIdx == 0)
|
391 |
|
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
392 |
|
|
else
|
393 |
|
|
mvpAy <= {8{refIdxL0_C}} & mvy_CurrMb0[15:8];
|
394 |
|
|
end
|
395 |
|
|
//Inter8x8
|
396 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) //sub_mb_pred
|
397 |
|
|
case (mbPartIdx)
|
398 |
|
|
0:
|
399 |
|
|
case (sub_mb_type)
|
400 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
401 |
|
|
1: //8x4
|
402 |
|
|
case (subMbPartIdx)
|
403 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
404 |
|
|
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8];
|
405 |
|
|
default:mvpAy <= 0;
|
406 |
|
|
endcase
|
407 |
|
|
2: //4x8
|
408 |
|
|
case (subMbPartIdx)
|
409 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
410 |
|
|
1:mvpAy <= mvy_CurrMb0[7:0];
|
411 |
|
|
default:mvpAy <= 0;
|
412 |
|
|
endcase
|
413 |
|
|
3: //4x4
|
414 |
|
|
case (subMbPartIdx)
|
415 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
416 |
|
|
1:mvpAy <= mvy_CurrMb0[7:0];
|
417 |
|
|
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8];
|
418 |
|
|
3:mvpAy <= mvy_CurrMb0[23:16];
|
419 |
|
|
endcase
|
420 |
|
|
endcase
|
421 |
|
|
1:
|
422 |
|
|
case (sub_mb_type)
|
423 |
|
|
0:mvpAy <= mvy_CurrMb0[15:8];
|
424 |
|
|
1: //8x4
|
425 |
|
|
case (subMbPartIdx)
|
426 |
|
|
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb0[31:24];
|
427 |
|
|
default:mvpAy <= 0;
|
428 |
|
|
endcase
|
429 |
|
|
2: //4x8
|
430 |
|
|
case (subMbPartIdx)
|
431 |
|
|
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb1[7:0];
|
432 |
|
|
default:mvpAy <= 0;
|
433 |
|
|
endcase
|
434 |
|
|
3: //4x4
|
435 |
|
|
case (subMbPartIdx)
|
436 |
|
|
0:mvpAy <= mvy_CurrMb0[15:8] ; 1:mvpAy <= mvy_CurrMb1[7:0];
|
437 |
|
|
2:mvpAy <= mvy_CurrMb0[31:24]; 3:mvpAy <= mvy_CurrMb1[23:16];
|
438 |
|
|
endcase
|
439 |
|
|
endcase
|
440 |
|
|
2:
|
441 |
|
|
case (sub_mb_type)
|
442 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
443 |
|
|
1: //8x4
|
444 |
|
|
case (subMbPartIdx)
|
445 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
446 |
|
|
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24];
|
447 |
|
|
default:mvpAy <= 0;
|
448 |
|
|
endcase
|
449 |
|
|
2: //4x8
|
450 |
|
|
case (subMbPartIdx)
|
451 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
452 |
|
|
1:mvpAy <= mvy_CurrMb2[7:0];
|
453 |
|
|
default:mvpAy <= 0;
|
454 |
|
|
endcase
|
455 |
|
|
3: //4x4
|
456 |
|
|
case (subMbPartIdx)
|
457 |
|
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
458 |
|
|
1:mvpAy <= mvy_CurrMb2[7:0];
|
459 |
|
|
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24];
|
460 |
|
|
3:mvpAy <= mvy_CurrMb2[23:16];
|
461 |
|
|
endcase
|
462 |
|
|
endcase
|
463 |
|
|
3:
|
464 |
|
|
case (sub_mb_type)
|
465 |
|
|
0:mvpAy <= mvy_CurrMb2[15:8];
|
466 |
|
|
1: //8x4
|
467 |
|
|
case (subMbPartIdx)
|
468 |
|
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb2[31:24];
|
469 |
|
|
default:mvpAy <= 0;
|
470 |
|
|
endcase
|
471 |
|
|
2: //4x8
|
472 |
|
|
case (subMbPartIdx)
|
473 |
|
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0];
|
474 |
|
|
default:mvpAy <= 0;
|
475 |
|
|
endcase
|
476 |
|
|
3: //4x4
|
477 |
|
|
case (subMbPartIdx)
|
478 |
|
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0];
|
479 |
|
|
2:mvpAy <= mvy_CurrMb2[31:24]; 3:mvpAy <= mvy_CurrMb3[23:16];
|
480 |
|
|
endcase
|
481 |
|
|
endcase
|
482 |
|
|
endcase
|
483 |
|
|
else
|
484 |
|
|
mvpAy <= 0;
|
485 |
|
|
//-------------
|
486 |
|
|
//mvpBx
|
487 |
|
|
//-------------
|
488 |
|
|
//if B is not available,it can be predicted from A when both B and C are not available
|
489 |
|
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type
|
490 |
|
|
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1]
|
491 |
|
|
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
492 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
493 |
|
|
//P_skip or Inter16x16
|
494 |
|
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
495 |
|
|
begin
|
496 |
|
|
if (mb_num == 0) mvpBx <= 0;
|
497 |
|
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
498 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
499 |
|
|
end
|
500 |
|
|
//Inter16x8
|
501 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
502 |
|
|
begin
|
503 |
|
|
if (mbPartIdx == 0)
|
504 |
|
|
begin
|
505 |
|
|
if (mb_num == 0) mvpBx <= 0;
|
506 |
|
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
507 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
508 |
|
|
end
|
509 |
|
|
else //for bottom 8x8 block when mbAddrA is not available
|
510 |
|
|
mvpBx <= (!refIdxL0_A)? 0:mvx_CurrMb0[23:16];
|
511 |
|
|
end
|
512 |
|
|
//Inter8x16:for left 8x8 block when mbAddrA is not available
|
513 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
514 |
|
|
begin
|
515 |
|
|
if (mbPartIdx == 0) //left blk
|
516 |
|
|
mvpBx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[31:24]:0;
|
517 |
|
|
else //right blk
|
518 |
|
|
case (!refIdxL0_C)
|
519 |
|
|
1'b1:mvpBx <= 0;
|
520 |
|
|
1'b0:
|
521 |
|
|
if (mb_num_v == 0)
|
522 |
|
|
mvpBx <= mvx_CurrMb0[7:0];
|
523 |
|
|
else
|
524 |
|
|
mvpBx <= (!refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0;
|
525 |
|
|
endcase
|
526 |
|
|
end
|
527 |
|
|
//Inter8x8
|
528 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
529 |
|
|
case (mbPartIdx)
|
530 |
|
|
0:
|
531 |
|
|
case (sub_mb_type)
|
532 |
|
|
0:if (mb_num == 0) mvpBx <= 0;
|
533 |
|
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
534 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
535 |
|
|
1: //8x4
|
536 |
|
|
case (subMbPartIdx)
|
537 |
|
|
0:if (mb_num == 0) mvpBx <= 0;
|
538 |
|
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
539 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
540 |
|
|
1:mvpBx <= mvx_CurrMb0[7:0];
|
541 |
|
|
default:mvpBx <= 0;
|
542 |
|
|
endcase
|
543 |
|
|
2: //4x8
|
544 |
|
|
case (subMbPartIdx)
|
545 |
|
|
0:if (mb_num == 0) mvpBx <= 0;
|
546 |
|
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
547 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
548 |
|
|
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0];
|
549 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
550 |
|
|
default:mvpBx <= 0;
|
551 |
|
|
endcase
|
552 |
|
|
3: //4x4
|
553 |
|
|
case (subMbPartIdx)
|
554 |
|
|
0:if (mb_num == 0) mvpBx <= 0;
|
555 |
|
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
556 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
557 |
|
|
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0];
|
558 |
|
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
559 |
|
|
2:mvpBx <= mvx_CurrMb0[7:0];
|
560 |
|
|
3:mvpBx <= mvx_CurrMb0[15:8];
|
561 |
|
|
endcase
|
562 |
|
|
endcase
|
563 |
|
|
1:
|
564 |
|
|
case (sub_mb_type)
|
565 |
|
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
566 |
|
|
1: //8x4
|
567 |
|
|
case (subMbPartIdx)
|
568 |
|
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
569 |
|
|
1:mvpBx <= mvx_CurrMb1[7:0];
|
570 |
|
|
default:mvpBx <= 0;
|
571 |
|
|
endcase
|
572 |
|
|
2: //4x8
|
573 |
|
|
case (subMbPartIdx)
|
574 |
|
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
575 |
|
|
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]);
|
576 |
|
|
default:mvpBx <= 0;
|
577 |
|
|
endcase
|
578 |
|
|
3: //4x4
|
579 |
|
|
case (subMbPartIdx)
|
580 |
|
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
581 |
|
|
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]);
|
582 |
|
|
2:mvpBx <= mvx_CurrMb1[7:0];
|
583 |
|
|
3:mvpBx <= mvx_CurrMb1[15:8];
|
584 |
|
|
endcase
|
585 |
|
|
endcase
|
586 |
|
|
2:
|
587 |
|
|
case (sub_mb_type)
|
588 |
|
|
0:mvpBx <= mvx_CurrMb0[23:16];
|
589 |
|
|
1: //8x4
|
590 |
|
|
case (subMbPartIdx)
|
591 |
|
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb2[7:0]; default:mvpBx <= 0;
|
592 |
|
|
endcase
|
593 |
|
|
2: //4x8
|
594 |
|
|
case (subMbPartIdx)
|
595 |
|
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; default:mvpBx <= 0;
|
596 |
|
|
endcase
|
597 |
|
|
3: //4x4
|
598 |
|
|
case (subMbPartIdx)
|
599 |
|
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24];
|
600 |
|
|
2:mvpBx <= mvx_CurrMb2[7:0]; 3:mvpBx <= mvx_CurrMb2[15:8];
|
601 |
|
|
endcase
|
602 |
|
|
endcase
|
603 |
|
|
3:
|
604 |
|
|
case (sub_mb_type)
|
605 |
|
|
0:mvpBx <= mvx_CurrMb1[23:16];
|
606 |
|
|
1: //8x4
|
607 |
|
|
case (subMbPartIdx)
|
608 |
|
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb3[7:0]; default:mvpBx <= 0;
|
609 |
|
|
endcase
|
610 |
|
|
2: //4x8
|
611 |
|
|
case (subMbPartIdx)
|
612 |
|
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; default:mvpBx <= 0;
|
613 |
|
|
endcase
|
614 |
|
|
3: //4x4
|
615 |
|
|
case (subMbPartIdx)
|
616 |
|
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24];
|
617 |
|
|
2:mvpBx <= mvx_CurrMb3[7:0]; 3:mvpBx <= mvx_CurrMb3[15:8];
|
618 |
|
|
endcase
|
619 |
|
|
endcase
|
620 |
|
|
endcase
|
621 |
|
|
else
|
622 |
|
|
mvpBx <= 0;
|
623 |
|
|
//-------------
|
624 |
|
|
//mvpBy
|
625 |
|
|
//-------------
|
626 |
|
|
//if B is not available,it can be predicted from A when both B and C are not available
|
627 |
|
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type
|
628 |
|
|
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1]
|
629 |
|
|
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
630 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
631 |
|
|
//P_skip or Inter16x16
|
632 |
|
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
633 |
|
|
begin
|
634 |
|
|
if (mb_num == 0) mvpBy <= 0;
|
635 |
|
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
636 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
637 |
|
|
end
|
638 |
|
|
//Inter16x8
|
639 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
640 |
|
|
begin
|
641 |
|
|
if (mbPartIdx == 0) //upper 8x8 block
|
642 |
|
|
begin
|
643 |
|
|
if (mb_num == 0) mvpBy <= 0;
|
644 |
|
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
645 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
646 |
|
|
end
|
647 |
|
|
else //for bottom 8x8 block when mbAddrA is not available
|
648 |
|
|
mvpBy <= (!refIdxL0_A)? 0:mvy_CurrMb0[23:16];
|
649 |
|
|
end
|
650 |
|
|
//Inter8x16:for left 8x8 block when mbAddrA is not available
|
651 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
652 |
|
|
begin
|
653 |
|
|
if (mbPartIdx == 0) //left blk
|
654 |
|
|
mvpBy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[31:24]:0;
|
655 |
|
|
else //right blk
|
656 |
|
|
case (!refIdxL0_C)
|
657 |
|
|
1'b1:mvpBy <= 0;
|
658 |
|
|
1'b0:
|
659 |
|
|
if (mb_num_v == 0)
|
660 |
|
|
mvpBy <= mvy_CurrMb0[7:0];
|
661 |
|
|
else
|
662 |
|
|
mvpBy <= (!refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0;
|
663 |
|
|
endcase
|
664 |
|
|
end
|
665 |
|
|
//Inter8x8
|
666 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
667 |
|
|
case (mbPartIdx)
|
668 |
|
|
0:
|
669 |
|
|
case (sub_mb_type)
|
670 |
|
|
0:if (mb_num == 0) mvpBy <= 0;
|
671 |
|
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
672 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
673 |
|
|
1: //8x4
|
674 |
|
|
case (subMbPartIdx)
|
675 |
|
|
0:if (mb_num == 0) mvpBy <= 0;
|
676 |
|
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
677 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
678 |
|
|
1:mvpBy <= mvy_CurrMb0[7:0];
|
679 |
|
|
default:mvpBy <= 0;
|
680 |
|
|
endcase
|
681 |
|
|
2: //4x8
|
682 |
|
|
case (subMbPartIdx)
|
683 |
|
|
0:if (mb_num == 0) mvpBy <= 0;
|
684 |
|
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
685 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
686 |
|
|
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0];
|
687 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
688 |
|
|
default:mvpBy <= 0;
|
689 |
|
|
endcase
|
690 |
|
|
3: //4x4
|
691 |
|
|
case (subMbPartIdx)
|
692 |
|
|
0:if (mb_num == 0) mvpBy <= 0;
|
693 |
|
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
694 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
695 |
|
|
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0];
|
696 |
|
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
697 |
|
|
2:mvpBy <= mvy_CurrMb0[7:0];
|
698 |
|
|
3:mvpBy <= mvy_CurrMb0[15:8];
|
699 |
|
|
endcase
|
700 |
|
|
endcase
|
701 |
|
|
1:
|
702 |
|
|
case (sub_mb_type)
|
703 |
|
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
704 |
|
|
1: //8x4
|
705 |
|
|
case (subMbPartIdx)
|
706 |
|
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
707 |
|
|
1:mvpBy <= mvy_CurrMb1[7:0];
|
708 |
|
|
default:mvpBy <= 0;
|
709 |
|
|
endcase
|
710 |
|
|
2: //4x8
|
711 |
|
|
case (subMbPartIdx)
|
712 |
|
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
713 |
|
|
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]);
|
714 |
|
|
default:mvpBy <= 0;
|
715 |
|
|
endcase
|
716 |
|
|
3: //4x4
|
717 |
|
|
case (subMbPartIdx)
|
718 |
|
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
719 |
|
|
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]);
|
720 |
|
|
2:mvpBy <= mvy_CurrMb1[7:0];
|
721 |
|
|
3:mvpBy <= mvy_CurrMb1[15:8];
|
722 |
|
|
endcase
|
723 |
|
|
endcase
|
724 |
|
|
2:
|
725 |
|
|
case (sub_mb_type)
|
726 |
|
|
0:mvpBy <= mvy_CurrMb0[23:16];
|
727 |
|
|
1: //8x4
|
728 |
|
|
case (subMbPartIdx)
|
729 |
|
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb2[7:0]; default:mvpBy <= 0;
|
730 |
|
|
endcase
|
731 |
|
|
2: //4x8
|
732 |
|
|
case (subMbPartIdx)
|
733 |
|
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; default:mvpBy <= 0;
|
734 |
|
|
endcase
|
735 |
|
|
3: //4x4
|
736 |
|
|
case (subMbPartIdx)
|
737 |
|
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24];
|
738 |
|
|
2:mvpBy <= mvy_CurrMb2[7:0]; 3:mvpBy <= mvy_CurrMb2[15:8];
|
739 |
|
|
endcase
|
740 |
|
|
endcase
|
741 |
|
|
3:
|
742 |
|
|
case (sub_mb_type)
|
743 |
|
|
0:mvpBy <= mvy_CurrMb1[23:16];
|
744 |
|
|
1: //8x4
|
745 |
|
|
case (subMbPartIdx)
|
746 |
|
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb3[7:0]; default:mvpBy <= 0;
|
747 |
|
|
endcase
|
748 |
|
|
2: //4x8
|
749 |
|
|
case (subMbPartIdx)
|
750 |
|
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; default:mvpBy <= 0;
|
751 |
|
|
endcase
|
752 |
|
|
3: //4x4
|
753 |
|
|
case (subMbPartIdx)
|
754 |
|
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24];
|
755 |
|
|
2:mvpBy <= mvy_CurrMb3[7:0]; 3:mvpBy <= mvy_CurrMb3[15:8];
|
756 |
|
|
endcase
|
757 |
|
|
endcase
|
758 |
|
|
endcase
|
759 |
|
|
else
|
760 |
|
|
mvpBy <= 0;
|
761 |
|
|
//-------------
|
762 |
|
|
//mvpCx
|
763 |
|
|
//-------------
|
764 |
|
|
//if C is not available,it can be predicted from D,then from A
|
765 |
|
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v
|
766 |
|
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
767 |
|
|
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
|
768 |
|
|
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_mbAddrC_dout or mvx_mbAddrD
|
769 |
|
|
or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
770 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
771 |
|
|
//P_skip,Inter16x16
|
772 |
|
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
773 |
|
|
begin
|
774 |
|
|
if (mb_num == 0) mvpCx <= 0;
|
775 |
|
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
776 |
|
|
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrD == 1)? 0:mvx_mbAddrD;
|
777 |
|
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
778 |
|
|
end
|
779 |
|
|
//Inter16x8
|
780 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
781 |
|
|
begin
|
782 |
|
|
if (mbPartIdx == 0)
|
783 |
|
|
mvpCx <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvx_mbAddrD:mvx_mbAddrC_dout):0;
|
784 |
|
|
else
|
785 |
|
|
mvpCx <= 0;
|
786 |
|
|
end
|
787 |
|
|
//Inter8x16
|
788 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
789 |
|
|
begin
|
790 |
|
|
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived
|
791 |
|
|
if (mbPartIdx == 0) //left blk
|
792 |
|
|
mvpCx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0;
|
793 |
|
|
else //right blk
|
794 |
|
|
begin
|
795 |
|
|
if (mb_num == 0) mvpCx <= 0;
|
796 |
|
|
else if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
797 |
|
|
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
798 |
|
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
799 |
|
|
end
|
800 |
|
|
end
|
801 |
|
|
//Inter8x8
|
802 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
803 |
|
|
case (mbPartIdx)
|
804 |
|
|
0:
|
805 |
|
|
case (sub_mb_type)
|
806 |
|
|
0:if (mb_num == 0) mvpCx <= 0;
|
807 |
|
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
808 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
809 |
|
|
1: //8x4
|
810 |
|
|
case (subMbPartIdx)
|
811 |
|
|
0:if (mb_num == 0) mvpCx <= 0;
|
812 |
|
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
813 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
814 |
|
|
1:if (mb_num_h == 0) mvpCx <= 0;
|
815 |
|
|
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD;
|
816 |
|
|
default:mvpCx <= 0;
|
817 |
|
|
endcase
|
818 |
|
|
2: //4x8
|
819 |
|
|
case (subMbPartIdx)
|
820 |
|
|
0:if (mb_num == 0) mvpCx <= 0;
|
821 |
|
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
822 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
823 |
|
|
1:if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_CurrMb0[7:0];
|
824 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
825 |
|
|
default:mvpCx <= 0;
|
826 |
|
|
endcase
|
827 |
|
|
3: //4x4
|
828 |
|
|
case (subMbPartIdx)
|
829 |
|
|
0:if (mb_num == 0) mvpCx <= 0;
|
830 |
|
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
831 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
832 |
|
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[7:0];
|
833 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
834 |
|
|
2:mvpCx <= mvx_CurrMb0[15:8]; //always available
|
835 |
|
|
3:mvpCx <= mvx_CurrMb0[7:0]; //always from D
|
836 |
|
|
endcase
|
837 |
|
|
endcase
|
838 |
|
|
1:
|
839 |
|
|
case (sub_mb_type)
|
840 |
|
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
841 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
842 |
|
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
843 |
|
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
844 |
|
|
1: //8x4
|
845 |
|
|
case (subMbPartIdx)
|
846 |
|
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
847 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
848 |
|
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
849 |
|
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
850 |
|
|
1:mvpCx <= mvx_CurrMb0[15:8]; //C is always unavailable,D is always available
|
851 |
|
|
default:mvpCx <= 0;
|
852 |
|
|
endcase
|
853 |
|
|
2: //4x8
|
854 |
|
|
case (subMbPartIdx)
|
855 |
|
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
856 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0];
|
857 |
|
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0];
|
858 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB
|
859 |
|
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
860 |
|
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
861 |
|
|
default:mvpCx <= 0;
|
862 |
|
|
endcase
|
863 |
|
|
3: //4x4
|
864 |
|
|
case (subMbPartIdx)
|
865 |
|
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
866 |
|
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0];
|
867 |
|
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0];
|
868 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
869 |
|
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
870 |
|
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
871 |
|
|
2:mvpCx <= mvx_CurrMb1[15:8];
|
872 |
|
|
3:mvpCx <= mvx_CurrMb1[7:0];
|
873 |
|
|
endcase
|
874 |
|
|
endcase
|
875 |
|
|
2:
|
876 |
|
|
case (sub_mb_type)
|
877 |
|
|
0:mvpCx <= mvx_CurrMb1[23:16];
|
878 |
|
|
1: //8x4
|
879 |
|
|
case (subMbPartIdx)
|
880 |
|
|
0:mvpCx <= mvx_CurrMb1[23:16];
|
881 |
|
|
1:if (mb_num_h == 0) mvpCx <= 0;
|
882 |
|
|
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD;
|
883 |
|
|
default:mvpCx <= 0;
|
884 |
|
|
endcase
|
885 |
|
|
2: //4x8
|
886 |
|
|
case (subMbPartIdx)
|
887 |
|
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0;
|
888 |
|
|
endcase
|
889 |
|
|
3: //4x4
|
890 |
|
|
case (subMbPartIdx)
|
891 |
|
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16];
|
892 |
|
|
2:mvpCx <= mvx_CurrMb2[15:8]; 3:mvpCx <= mvx_CurrMb2[7:0];
|
893 |
|
|
endcase
|
894 |
|
|
endcase
|
895 |
|
|
3:
|
896 |
|
|
case (sub_mb_type)
|
897 |
|
|
0:mvpCx <= mvx_CurrMb0[31:24];
|
898 |
|
|
1: //8x4
|
899 |
|
|
case (subMbPartIdx)
|
900 |
|
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb2[15:8]; default:mvpCx <= 0;
|
901 |
|
|
endcase
|
902 |
|
|
2: //4x8
|
903 |
|
|
case (subMbPartIdx)
|
904 |
|
|
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0;
|
905 |
|
|
endcase
|
906 |
|
|
3: //4x4
|
907 |
|
|
case (subMbPartIdx)
|
908 |
|
|
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16];
|
909 |
|
|
2:mvpCx <= mvx_CurrMb3[15:8]; 3:mvpCx <= mvx_CurrMb3[7:0];
|
910 |
|
|
endcase
|
911 |
|
|
endcase
|
912 |
|
|
endcase
|
913 |
|
|
else
|
914 |
|
|
mvpCx <= 0;
|
915 |
|
|
//-------------
|
916 |
|
|
//mvpCy
|
917 |
|
|
//-------------
|
918 |
|
|
//if C is not available,it can be predicted from D,then from A
|
919 |
|
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v
|
920 |
|
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
921 |
|
|
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
|
922 |
|
|
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_mbAddrC_dout or mvy_mbAddrD
|
923 |
|
|
or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
924 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
925 |
|
|
//P_skip,Inter16x16
|
926 |
|
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
927 |
|
|
begin
|
928 |
|
|
if (mb_num == 0) mvpCy <= 0;
|
929 |
|
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
930 |
|
|
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrD == 1)? 0:mvy_mbAddrD;
|
931 |
|
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
932 |
|
|
end
|
933 |
|
|
//Inter16x8
|
934 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
935 |
|
|
begin
|
936 |
|
|
if (mbPartIdx == 0)
|
937 |
|
|
mvpCy <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvy_mbAddrD:mvy_mbAddrC_dout):0;
|
938 |
|
|
else
|
939 |
|
|
mvpCy <= 0;
|
940 |
|
|
end
|
941 |
|
|
//Inter8x16
|
942 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
943 |
|
|
begin
|
944 |
|
|
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived
|
945 |
|
|
if (mbPartIdx == 0) //left blk
|
946 |
|
|
mvpCy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0;
|
947 |
|
|
else //right blk
|
948 |
|
|
begin
|
949 |
|
|
if (mb_num == 0) mvpCy <= 0;
|
950 |
|
|
else if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
951 |
|
|
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
952 |
|
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
953 |
|
|
end
|
954 |
|
|
end
|
955 |
|
|
//Inter8x8
|
956 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
957 |
|
|
case (mbPartIdx)
|
958 |
|
|
0:
|
959 |
|
|
case (sub_mb_type)
|
960 |
|
|
0:if (mb_num == 0) mvpCy <= 0;
|
961 |
|
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
962 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
963 |
|
|
1: //8x4
|
964 |
|
|
case (subMbPartIdx)
|
965 |
|
|
0:if (mb_num == 0) mvpCy <= 0;
|
966 |
|
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
967 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
968 |
|
|
1:if (mb_num_h == 0) mvpCy <= 0;
|
969 |
|
|
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD;
|
970 |
|
|
default:mvpCy <= 0;
|
971 |
|
|
endcase
|
972 |
|
|
2: //4x8
|
973 |
|
|
case (subMbPartIdx)
|
974 |
|
|
0:if (mb_num == 0) mvpCy <= 0;
|
975 |
|
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
976 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
977 |
|
|
1:if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_CurrMb0[7:0];
|
978 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
979 |
|
|
default:mvpCy <= 0;
|
980 |
|
|
endcase
|
981 |
|
|
3: //4x4
|
982 |
|
|
case (subMbPartIdx)
|
983 |
|
|
0:if (mb_num == 0) mvpCy <= 0;
|
984 |
|
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
985 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
986 |
|
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[7:0];
|
987 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
988 |
|
|
2:mvpCy <= mvy_CurrMb0[15:8]; //always available
|
989 |
|
|
3:mvpCy <= mvy_CurrMb0[7:0]; //always from D
|
990 |
|
|
endcase
|
991 |
|
|
endcase
|
992 |
|
|
1:
|
993 |
|
|
case (sub_mb_type)
|
994 |
|
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
995 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
996 |
|
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
997 |
|
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
998 |
|
|
1: //8x4
|
999 |
|
|
case (subMbPartIdx)
|
1000 |
|
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
1001 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
1002 |
|
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
1003 |
|
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
1004 |
|
|
1:mvpCy <= mvy_CurrMb0[15:8]; //C is always unavailable,D is always available
|
1005 |
|
|
default:mvpCy <= 0;
|
1006 |
|
|
endcase
|
1007 |
|
|
2: //4x8
|
1008 |
|
|
case (subMbPartIdx)
|
1009 |
|
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
1010 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0];
|
1011 |
|
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0];
|
1012 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB
|
1013 |
|
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
1014 |
|
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
1015 |
|
|
default:mvpCy <= 0;
|
1016 |
|
|
endcase
|
1017 |
|
|
3: //4x4
|
1018 |
|
|
case (subMbPartIdx)
|
1019 |
|
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
1020 |
|
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0];
|
1021 |
|
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0];
|
1022 |
|
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
1023 |
|
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
1024 |
|
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
1025 |
|
|
2:mvpCy <= mvy_CurrMb1[15:8];
|
1026 |
|
|
3:mvpCy <= mvy_CurrMb1[7:0];
|
1027 |
|
|
endcase
|
1028 |
|
|
endcase
|
1029 |
|
|
2:
|
1030 |
|
|
case (sub_mb_type)
|
1031 |
|
|
0:mvpCy <= mvy_CurrMb1[23:16];
|
1032 |
|
|
1: //8x4
|
1033 |
|
|
case (subMbPartIdx)
|
1034 |
|
|
0:mvpCy <= mvy_CurrMb1[23:16];
|
1035 |
|
|
1:if (mb_num_h == 0) mvpCy <= 0;
|
1036 |
|
|
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD;
|
1037 |
|
|
default:mvpCy <= 0;
|
1038 |
|
|
endcase
|
1039 |
|
|
2: //4x8
|
1040 |
|
|
case (subMbPartIdx)
|
1041 |
|
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0;
|
1042 |
|
|
endcase
|
1043 |
|
|
3: //4x4
|
1044 |
|
|
case (subMbPartIdx)
|
1045 |
|
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16];
|
1046 |
|
|
2:mvpCy <= mvy_CurrMb2[15:8]; 3:mvpCy <= mvy_CurrMb2[7:0];
|
1047 |
|
|
endcase
|
1048 |
|
|
endcase
|
1049 |
|
|
3:
|
1050 |
|
|
case (sub_mb_type)
|
1051 |
|
|
0:mvpCy <= mvy_CurrMb0[31:24];
|
1052 |
|
|
1: //8x4
|
1053 |
|
|
case (subMbPartIdx)
|
1054 |
|
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb2[15:8]; default:mvpCy <= 0;
|
1055 |
|
|
endcase
|
1056 |
|
|
2: //4x8
|
1057 |
|
|
case (subMbPartIdx)
|
1058 |
|
|
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0;
|
1059 |
|
|
endcase
|
1060 |
|
|
3: //4x4
|
1061 |
|
|
case (subMbPartIdx)
|
1062 |
|
|
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16];
|
1063 |
|
|
2:mvpCy <= mvy_CurrMb3[15:8]; 3:mvpCy <= mvy_CurrMb3[7:0];
|
1064 |
|
|
endcase
|
1065 |
|
|
endcase
|
1066 |
|
|
endcase
|
1067 |
|
|
else
|
1068 |
|
|
mvpCy <= 0;
|
1069 |
|
|
//------------------------------------------------
|
1070 |
|
|
//obtain motion vector prediction for current Blk
|
1071 |
|
|
//------------------------------------------------
|
1072 |
|
|
wire [8:0] sub_ABx,sub_ACx,sub_BCx;
|
1073 |
|
|
wire flag_ABx,flag_ACx,flag_BCx;
|
1074 |
|
|
assign sub_ABx = {mvpAx[7],mvpAx[7:0]} - {mvpBx[7],mvpBx[7:0]};
|
1075 |
|
|
assign sub_ACx = {mvpAx[7],mvpAx[7:0]} - {mvpCx[7],mvpCx[7:0]};
|
1076 |
|
|
assign sub_BCx = {mvpBx[7],mvpBx[7:0]} - {mvpCx[7],mvpCx[7:0]};
|
1077 |
|
|
assign flag_ABx = sub_ABx[8];
|
1078 |
|
|
assign flag_ACx = sub_ACx[8];
|
1079 |
|
|
assign flag_BCx = sub_BCx[8];
|
1080 |
|
|
|
1081 |
|
|
reg [7:0] mvpx_median;
|
1082 |
|
|
always @ (flag_ABx or flag_ACx or flag_BCx or mvpAx or mvpBx or mvpCx)
|
1083 |
|
|
if (((flag_ABx == 1'b1) && (flag_ACx == 1'b0)) || ((flag_ABx == 1'b0) && (flag_ACx == 1'b1)))
|
1084 |
|
|
mvpx_median <= mvpAx;
|
1085 |
|
|
else if (((flag_ABx == 1'b0) && (flag_BCx == 1'b0)) || ((flag_ABx == 1'b1) && (flag_BCx == 1'b1)))
|
1086 |
|
|
mvpx_median <= mvpBx;
|
1087 |
|
|
else
|
1088 |
|
|
mvpx_median <= mvpCx;
|
1089 |
|
|
|
1090 |
|
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAx or mvpBx or mvpCx or mvpx_median)
|
1091 |
|
|
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C})
|
1092 |
|
|
3'b011:mvpx <= mvpAx;
|
1093 |
|
|
3'b101:mvpx <= mvpBx;
|
1094 |
|
|
3'b110:mvpx <= mvpCx;
|
1095 |
|
|
default:mvpx <= mvpx_median;
|
1096 |
|
|
endcase
|
1097 |
|
|
|
1098 |
|
|
wire [8:0] sub_ABy,sub_ACy,sub_BCy;
|
1099 |
|
|
wire flag_ABy,flag_ACy,flag_BCy;
|
1100 |
|
|
assign sub_ABy = {mvpAy[7],mvpAy[7:0]} - {mvpBy[7],mvpBy[7:0]};
|
1101 |
|
|
assign sub_ACy = {mvpAy[7],mvpAy[7:0]} - {mvpCy[7],mvpCy[7:0]};
|
1102 |
|
|
assign sub_BCy = {mvpBy[7],mvpBy[7:0]} - {mvpCy[7],mvpCy[7:0]};
|
1103 |
|
|
assign flag_ABy = sub_ABy[8];
|
1104 |
|
|
assign flag_ACy = sub_ACy[8];
|
1105 |
|
|
assign flag_BCy = sub_BCy[8];
|
1106 |
|
|
|
1107 |
|
|
reg [7:0] mvpy_median;
|
1108 |
|
|
always @ (flag_ABy or flag_ACy or flag_BCy or mvpAy or mvpBy or mvpCy)
|
1109 |
|
|
if (((flag_ABy == 1'b1) && (flag_ACy == 1'b0)) || ((flag_ABy == 1'b0) && (flag_ACy == 1'b1)))
|
1110 |
|
|
mvpy_median <= mvpAy;
|
1111 |
|
|
else if (((flag_ABy == 1'b0) && (flag_BCy == 1'b0)) || ((flag_ABy == 1'b1) && (flag_BCy == 1'b1)))
|
1112 |
|
|
mvpy_median <= mvpBy;
|
1113 |
|
|
else
|
1114 |
|
|
mvpy_median <= mvpCy;
|
1115 |
|
|
|
1116 |
|
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAy or mvpBy or mvpCy or mvpy_median)
|
1117 |
|
|
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C})
|
1118 |
|
|
3'b011:mvpy <= mvpAy;
|
1119 |
|
|
3'b101:mvpy <= mvpBy;
|
1120 |
|
|
3'b110:mvpy <= mvpCy;
|
1121 |
|
|
default:mvpy <= mvpy_median;
|
1122 |
|
|
endcase
|
1123 |
|
|
|
1124 |
|
|
always @ (Is_skipMB_mv_calc or mb_num_h or mb_num_v or mb_pred_state or sub_mb_pred_state or compIdx or mvpx or mvpy
|
1125 |
|
|
or mvd or mvpAx or mvpBx or mvpCx or mvpAy or mvpBy or mvpCy or mb_type_general or mbPartIdx
|
1126 |
|
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
1127 |
|
|
if (Is_skipMB_mv_calc)
|
1128 |
|
|
begin
|
1129 |
|
|
//Refer to Page113,section 8.4.1.1 of H.264/AVC 2003.05 standard
|
1130 |
|
|
if (mb_num_h == 0 || mb_num_v == 0 || (refIdxL0_A == 0 && mvpAx == 0 && mvpAy == 0) ||
|
1131 |
|
|
(refIdxL0_B == 0 && mvpBx == 0 && mvpBy == 0))
|
1132 |
|
|
begin mvx <= 0; mvy <= 0; end
|
1133 |
|
|
else
|
1134 |
|
|
begin mvx <= mvpx; mvy <= mvpy; end
|
1135 |
|
|
end
|
1136 |
|
|
else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s)
|
1137 |
|
|
begin
|
1138 |
|
|
if (mb_type_general == `MB_Inter16x8) //16x8
|
1139 |
|
|
case (mbPartIdx)
|
1140 |
|
|
2'b00: //upper blk
|
1141 |
|
|
if (!refIdxL0_B)
|
1142 |
|
|
begin
|
1143 |
|
|
mvx <= (compIdx == 0)? (mvpBx + mvd):0;
|
1144 |
|
|
mvy <= (compIdx == 1)? (mvpBy + mvd):0;
|
1145 |
|
|
end
|
1146 |
|
|
else
|
1147 |
|
|
begin
|
1148 |
|
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
1149 |
|
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
1150 |
|
|
end
|
1151 |
|
|
default: //bottom blk
|
1152 |
|
|
if (!refIdxL0_A)
|
1153 |
|
|
begin
|
1154 |
|
|
mvx <= (compIdx == 0)? (mvpAx + mvd):0;
|
1155 |
|
|
mvy <= (compIdx == 1)? (mvpAy + mvd):0;
|
1156 |
|
|
end
|
1157 |
|
|
else
|
1158 |
|
|
begin
|
1159 |
|
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
1160 |
|
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
1161 |
|
|
end
|
1162 |
|
|
endcase
|
1163 |
|
|
else if (mb_type_general == `MB_Inter8x16) //8x16
|
1164 |
|
|
case (mbPartIdx)
|
1165 |
|
|
2'b00: //left blk
|
1166 |
|
|
if (!refIdxL0_A)
|
1167 |
|
|
begin
|
1168 |
|
|
mvx <= (compIdx == 0)? (mvpAx + mvd):0;
|
1169 |
|
|
mvy <= (compIdx == 1)? (mvpAy + mvd):0;
|
1170 |
|
|
end
|
1171 |
|
|
else
|
1172 |
|
|
begin
|
1173 |
|
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
1174 |
|
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
1175 |
|
|
end
|
1176 |
|
|
default: //right blk
|
1177 |
|
|
//if mbAddrC is not available but mbAddrB (= mbAddrD) is INTER available (not only available,but also inter
|
1178 |
|
|
//available),it still predicted from mbAddrC <- mbAddrD
|
1179 |
|
|
if (!refIdxL0_C || (mb_num_h == 10 && !refIdxL0_B))
|
1180 |
|
|
begin
|
1181 |
|
|
mvx <= (compIdx == 0)? (mvpCx + mvd):0;
|
1182 |
|
|
mvy <= (compIdx == 1)? (mvpCy + mvd):0;
|
1183 |
|
|
end
|
1184 |
|
|
else
|
1185 |
|
|
begin
|
1186 |
|
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
1187 |
|
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
1188 |
|
|
end
|
1189 |
|
|
endcase
|
1190 |
|
|
else
|
1191 |
|
|
begin
|
1192 |
|
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
1193 |
|
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
1194 |
|
|
end
|
1195 |
|
|
end
|
1196 |
|
|
else
|
1197 |
|
|
begin
|
1198 |
|
|
mvx <= 0; mvy <= 0;
|
1199 |
|
|
end
|
1200 |
|
|
//-----------------------------------------------------
|
1201 |
|
|
//Current MB write --> CurrMb0,CurrMb1,CurrMb2,CurrMb3
|
1202 |
|
|
//-----------------------------------------------------
|
1203 |
|
|
always @ (posedge clk)
|
1204 |
|
|
if (reset_n == 0)
|
1205 |
|
|
mv_is16x16 <= 0;
|
1206 |
|
|
else if (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_P_skip)
|
1207 |
|
|
mv_is16x16 <= 1;
|
1208 |
|
|
else
|
1209 |
|
|
mv_is16x16 <= 0;
|
1210 |
|
|
|
1211 |
|
|
always @ (posedge clk)
|
1212 |
|
|
if (reset_n == 0)
|
1213 |
|
|
begin
|
1214 |
|
|
mvx_CurrMb0 <= 0; mvx_CurrMb1 <= 0; mvx_CurrMb2 <= 0; mvx_CurrMb3 <= 0;
|
1215 |
|
|
end
|
1216 |
|
|
//Inter16x16 or P_skip
|
1217 |
|
|
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
1218 |
|
|
mvx_CurrMb0[7:0] <= mvx;
|
1219 |
|
|
//Inter16x8
|
1220 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
1221 |
|
|
case (mbPartIdx)
|
1222 |
|
|
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; end
|
1223 |
|
|
1:begin mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end
|
1224 |
|
|
endcase
|
1225 |
|
|
//Inter8x16
|
1226 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
1227 |
|
|
case (mbPartIdx)
|
1228 |
|
|
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; end
|
1229 |
|
|
1:begin mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end
|
1230 |
|
|
endcase
|
1231 |
|
|
//Inter8x8
|
1232 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
1233 |
|
|
case (mbPartIdx)
|
1234 |
|
|
0:
|
1235 |
|
|
case (sub_mb_type)
|
1236 |
|
|
0:mvx_CurrMb0 <= {mvx,mvx,mvx,mvx};
|
1237 |
|
|
1: //8x4
|
1238 |
|
|
case (subMbPartIdx)
|
1239 |
|
|
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[15:8] <= mvx; end
|
1240 |
|
|
1:begin mvx_CurrMb0[23:16] <= mvx; mvx_CurrMb0[31:24] <= mvx; end
|
1241 |
|
|
endcase
|
1242 |
|
|
2: //4x8
|
1243 |
|
|
case (subMbPartIdx)
|
1244 |
|
|
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[23:16] <= mvx; end
|
1245 |
|
|
1:begin mvx_CurrMb0[15:8] <= mvx; mvx_CurrMb0[31:24] <= mvx; end
|
1246 |
|
|
endcase
|
1247 |
|
|
3: //4x4
|
1248 |
|
|
case (subMbPartIdx)
|
1249 |
|
|
0:mvx_CurrMb0[7:0] <= mvx;
|
1250 |
|
|
1:mvx_CurrMb0[15:8] <= mvx;
|
1251 |
|
|
2:mvx_CurrMb0[23:16] <= mvx;
|
1252 |
|
|
3:mvx_CurrMb0[31:24] <= mvx;
|
1253 |
|
|
endcase
|
1254 |
|
|
endcase
|
1255 |
|
|
1:
|
1256 |
|
|
case (sub_mb_type)
|
1257 |
|
|
0:mvx_CurrMb1 <= {mvx,mvx,mvx,mvx};
|
1258 |
|
|
1: //8x4
|
1259 |
|
|
case (subMbPartIdx)
|
1260 |
|
|
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[15:8] <= mvx; end
|
1261 |
|
|
1:begin mvx_CurrMb1[23:16] <= mvx; mvx_CurrMb1[31:24] <= mvx; end
|
1262 |
|
|
endcase
|
1263 |
|
|
2: //4x8
|
1264 |
|
|
case (subMbPartIdx)
|
1265 |
|
|
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[23:16] <= mvx; end
|
1266 |
|
|
1:begin mvx_CurrMb1[15:8] <= mvx; mvx_CurrMb1[31:24] <= mvx; end
|
1267 |
|
|
endcase
|
1268 |
|
|
3: //4x4
|
1269 |
|
|
case (subMbPartIdx)
|
1270 |
|
|
0:mvx_CurrMb1[7:0] <= mvx;
|
1271 |
|
|
1:mvx_CurrMb1[15:8] <= mvx;
|
1272 |
|
|
2:mvx_CurrMb1[23:16] <= mvx;
|
1273 |
|
|
3:mvx_CurrMb1[31:24] <= mvx;
|
1274 |
|
|
endcase
|
1275 |
|
|
endcase
|
1276 |
|
|
2:
|
1277 |
|
|
case (sub_mb_type)
|
1278 |
|
|
0:mvx_CurrMb2 <= {mvx,mvx,mvx,mvx};
|
1279 |
|
|
1: //8x4
|
1280 |
|
|
case (subMbPartIdx)
|
1281 |
|
|
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[15:8] <= mvx; end
|
1282 |
|
|
1:begin mvx_CurrMb2[23:16] <= mvx; mvx_CurrMb2[31:24] <= mvx; end
|
1283 |
|
|
endcase
|
1284 |
|
|
2: //4x8
|
1285 |
|
|
case (subMbPartIdx)
|
1286 |
|
|
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[23:16] <= mvx; end
|
1287 |
|
|
1:begin mvx_CurrMb2[15:8] <= mvx; mvx_CurrMb2[31:24] <= mvx; end
|
1288 |
|
|
endcase
|
1289 |
|
|
3: //4x4
|
1290 |
|
|
case (subMbPartIdx)
|
1291 |
|
|
0:mvx_CurrMb2[7:0] <= mvx;
|
1292 |
|
|
1:mvx_CurrMb2[15:8] <= mvx;
|
1293 |
|
|
2:mvx_CurrMb2[23:16] <= mvx;
|
1294 |
|
|
3:mvx_CurrMb2[31:24] <= mvx;
|
1295 |
|
|
endcase
|
1296 |
|
|
endcase
|
1297 |
|
|
3:
|
1298 |
|
|
case (sub_mb_type)
|
1299 |
|
|
0:mvx_CurrMb3 <= {mvx,mvx,mvx,mvx};
|
1300 |
|
|
1: //8x4
|
1301 |
|
|
case (subMbPartIdx)
|
1302 |
|
|
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[15:8] <= mvx; end
|
1303 |
|
|
1:begin mvx_CurrMb3[23:16] <= mvx; mvx_CurrMb3[31:24] <= mvx; end
|
1304 |
|
|
endcase
|
1305 |
|
|
2: //4x8
|
1306 |
|
|
case (subMbPartIdx)
|
1307 |
|
|
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[23:16] <= mvx; end
|
1308 |
|
|
1:begin mvx_CurrMb3[15:8] <= mvx; mvx_CurrMb3[31:24] <= mvx; end
|
1309 |
|
|
endcase
|
1310 |
|
|
3: //4x4
|
1311 |
|
|
case (subMbPartIdx)
|
1312 |
|
|
0:mvx_CurrMb3[7:0] <= mvx;
|
1313 |
|
|
1:mvx_CurrMb3[15:8] <= mvx;
|
1314 |
|
|
2:mvx_CurrMb3[23:16] <= mvx;
|
1315 |
|
|
3:mvx_CurrMb3[31:24] <= mvx;
|
1316 |
|
|
endcase
|
1317 |
|
|
endcase
|
1318 |
|
|
endcase
|
1319 |
|
|
always @ (posedge clk)
|
1320 |
|
|
if (reset_n == 0)
|
1321 |
|
|
begin
|
1322 |
|
|
mvy_CurrMb0 <= 0; mvy_CurrMb1 <= 0; mvy_CurrMb2 <= 0; mvy_CurrMb3 <= 0;
|
1323 |
|
|
end
|
1324 |
|
|
//Inter16x16 or P_skip
|
1325 |
|
|
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
1326 |
|
|
begin
|
1327 |
|
|
mvy_CurrMb0[7:0] <= mvy;
|
1328 |
|
|
end
|
1329 |
|
|
//Inter16x8
|
1330 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
1331 |
|
|
case (mbPartIdx)
|
1332 |
|
|
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; end
|
1333 |
|
|
1:begin mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end
|
1334 |
|
|
endcase
|
1335 |
|
|
//Inter8x16
|
1336 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
1337 |
|
|
case (mbPartIdx)
|
1338 |
|
|
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; end
|
1339 |
|
|
1:begin mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end
|
1340 |
|
|
endcase
|
1341 |
|
|
//Inter8x8
|
1342 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
1343 |
|
|
case (mbPartIdx)
|
1344 |
|
|
0:
|
1345 |
|
|
case (sub_mb_type)
|
1346 |
|
|
0:mvy_CurrMb0 <= {mvy,mvy,mvy,mvy};
|
1347 |
|
|
1: //8x4
|
1348 |
|
|
case (subMbPartIdx)
|
1349 |
|
|
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[15:8] <= mvy; end
|
1350 |
|
|
1:begin mvy_CurrMb0[23:16] <= mvy; mvy_CurrMb0[31:24] <= mvy; end
|
1351 |
|
|
endcase
|
1352 |
|
|
2: //4x8
|
1353 |
|
|
case (subMbPartIdx)
|
1354 |
|
|
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[23:16] <= mvy; end
|
1355 |
|
|
1:begin mvy_CurrMb0[15:8] <= mvy; mvy_CurrMb0[31:24] <= mvy; end
|
1356 |
|
|
endcase
|
1357 |
|
|
3: //4x4
|
1358 |
|
|
case (subMbPartIdx)
|
1359 |
|
|
0:mvy_CurrMb0[7:0] <= mvy;
|
1360 |
|
|
1:mvy_CurrMb0[15:8] <= mvy;
|
1361 |
|
|
2:mvy_CurrMb0[23:16] <= mvy;
|
1362 |
|
|
3:mvy_CurrMb0[31:24] <= mvy;
|
1363 |
|
|
endcase
|
1364 |
|
|
endcase
|
1365 |
|
|
1:
|
1366 |
|
|
case (sub_mb_type)
|
1367 |
|
|
0:mvy_CurrMb1 <= {mvy,mvy,mvy,mvy};
|
1368 |
|
|
1: //8x4
|
1369 |
|
|
case (subMbPartIdx)
|
1370 |
|
|
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[15:8] <= mvy; end
|
1371 |
|
|
1:begin mvy_CurrMb1[23:16] <= mvy; mvy_CurrMb1[31:24] <= mvy; end
|
1372 |
|
|
endcase
|
1373 |
|
|
2: //4x8
|
1374 |
|
|
case (subMbPartIdx)
|
1375 |
|
|
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[23:16] <= mvy; end
|
1376 |
|
|
1:begin mvy_CurrMb1[15:8] <= mvy; mvy_CurrMb1[31:24] <= mvy; end
|
1377 |
|
|
endcase
|
1378 |
|
|
3: //4x4
|
1379 |
|
|
case (subMbPartIdx)
|
1380 |
|
|
0:mvy_CurrMb1[7:0] <= mvy;
|
1381 |
|
|
1:mvy_CurrMb1[15:8] <= mvy;
|
1382 |
|
|
2:mvy_CurrMb1[23:16] <= mvy;
|
1383 |
|
|
3:mvy_CurrMb1[31:24] <= mvy;
|
1384 |
|
|
endcase
|
1385 |
|
|
endcase
|
1386 |
|
|
2:
|
1387 |
|
|
case (sub_mb_type)
|
1388 |
|
|
0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy};
|
1389 |
|
|
1: //8x4
|
1390 |
|
|
case (subMbPartIdx)
|
1391 |
|
|
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[15:8] <= mvy; end
|
1392 |
|
|
1:begin mvy_CurrMb2[23:16] <= mvy; mvy_CurrMb2[31:24] <= mvy; end
|
1393 |
|
|
endcase
|
1394 |
|
|
2: //4x8
|
1395 |
|
|
case (subMbPartIdx)
|
1396 |
|
|
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[23:16] <= mvy; end
|
1397 |
|
|
1:begin mvy_CurrMb2[15:8] <= mvy; mvy_CurrMb2[31:24] <= mvy; end
|
1398 |
|
|
endcase
|
1399 |
|
|
3: //4x4
|
1400 |
|
|
case (subMbPartIdx)
|
1401 |
|
|
0:mvy_CurrMb2[7:0] <= mvy;
|
1402 |
|
|
1:mvy_CurrMb2[15:8] <= mvy;
|
1403 |
|
|
2:mvy_CurrMb2[23:16] <= mvy;
|
1404 |
|
|
3:mvy_CurrMb2[31:24] <= mvy;
|
1405 |
|
|
endcase
|
1406 |
|
|
endcase
|
1407 |
|
|
3:
|
1408 |
|
|
case (sub_mb_type)
|
1409 |
|
|
0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy};
|
1410 |
|
|
1: //8x4
|
1411 |
|
|
case (subMbPartIdx)
|
1412 |
|
|
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[15:8] <= mvy; end
|
1413 |
|
|
1:begin mvy_CurrMb3[23:16] <= mvy; mvy_CurrMb3[31:24] <= mvy; end
|
1414 |
|
|
endcase
|
1415 |
|
|
2: //4x8
|
1416 |
|
|
case (subMbPartIdx)
|
1417 |
|
|
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[23:16] <= mvy; end
|
1418 |
|
|
1:begin mvy_CurrMb3[15:8] <= mvy; mvy_CurrMb3[31:24] <= mvy; end
|
1419 |
|
|
endcase
|
1420 |
|
|
3: //4x4
|
1421 |
|
|
case (subMbPartIdx)
|
1422 |
|
|
0:mvy_CurrMb3[7:0] <= mvy;
|
1423 |
|
|
1:mvy_CurrMb3[15:8] <= mvy;
|
1424 |
|
|
2:mvy_CurrMb3[23:16] <= mvy;
|
1425 |
|
|
3:mvy_CurrMb3[31:24] <= mvy;
|
1426 |
|
|
endcase
|
1427 |
|
|
endcase
|
1428 |
|
|
endcase
|
1429 |
|
|
//----------------------------
|
1430 |
|
|
//mbAddrA write --> mvx_mbAddrA
|
1431 |
|
|
//----------------------------
|
1432 |
|
|
always @ (posedge clk)
|
1433 |
|
|
if (reset_n == 0)
|
1434 |
|
|
mvx_mbAddrA <= 0;
|
1435 |
|
|
else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use
|
1436 |
|
|
begin
|
1437 |
|
|
//P_skip
|
1438 |
|
|
if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
|
1439 |
|
|
mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
|
1440 |
|
|
//Inter16x16
|
1441 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
1442 |
|
|
mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
|
1443 |
|
|
//Inter16x8
|
1444 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
1445 |
|
|
case (mbPartIdx)
|
1446 |
|
|
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end
|
1447 |
|
|
1:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end
|
1448 |
|
|
endcase
|
1449 |
|
|
//Inter8x16
|
1450 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0)
|
1451 |
|
|
mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
|
1452 |
|
|
//Inter8x8
|
1453 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
1454 |
|
|
case (mbPartIdx)
|
1455 |
|
|
1:
|
1456 |
|
|
case (sub_mb_type)
|
1457 |
|
|
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end
|
1458 |
|
|
1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0] <= mvx;
|
1459 |
|
|
else mvx_mbAddrA[15:8] <= mvx;
|
1460 |
|
|
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end
|
1461 |
|
|
3:if (subMbPartIdx == 1) mvx_mbAddrA[7:0] <= mvx;
|
1462 |
|
|
else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx;
|
1463 |
|
|
endcase
|
1464 |
|
|
3:
|
1465 |
|
|
case (sub_mb_type)
|
1466 |
|
|
0:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end
|
1467 |
|
|
1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16] <= mvx;
|
1468 |
|
|
else mvx_mbAddrA[31:24] <= mvx;
|
1469 |
|
|
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end
|
1470 |
|
|
3:if (subMbPartIdx == 1) mvx_mbAddrA[23:16] <= mvx;
|
1471 |
|
|
else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx;
|
1472 |
|
|
endcase
|
1473 |
|
|
endcase
|
1474 |
|
|
end
|
1475 |
|
|
always @ (posedge clk)
|
1476 |
|
|
if (reset_n == 0)
|
1477 |
|
|
mvy_mbAddrA <= 0;
|
1478 |
|
|
else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use
|
1479 |
|
|
begin
|
1480 |
|
|
//P_skip
|
1481 |
|
|
if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
|
1482 |
|
|
mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
|
1483 |
|
|
//Inter16x16
|
1484 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
1485 |
|
|
mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
|
1486 |
|
|
//Inter16x8
|
1487 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
1488 |
|
|
case (mbPartIdx)
|
1489 |
|
|
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end
|
1490 |
|
|
1:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end
|
1491 |
|
|
endcase
|
1492 |
|
|
//Inter8x16
|
1493 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1)
|
1494 |
|
|
mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
|
1495 |
|
|
//Inter8x8
|
1496 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
1497 |
|
|
case (mbPartIdx)
|
1498 |
|
|
1:
|
1499 |
|
|
case (sub_mb_type)
|
1500 |
|
|
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end
|
1501 |
|
|
1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0] <= mvy;
|
1502 |
|
|
else mvy_mbAddrA[15:8] <= mvy;
|
1503 |
|
|
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end
|
1504 |
|
|
3:if (subMbPartIdx == 1) mvy_mbAddrA[7:0] <= mvy;
|
1505 |
|
|
else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy;
|
1506 |
|
|
endcase
|
1507 |
|
|
3:
|
1508 |
|
|
case (sub_mb_type)
|
1509 |
|
|
0:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end
|
1510 |
|
|
1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16] <= mvy;
|
1511 |
|
|
else mvy_mbAddrA[31:24] <= mvy;
|
1512 |
|
|
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end
|
1513 |
|
|
3:if (subMbPartIdx == 1) mvy_mbAddrA[23:16] <= mvy;
|
1514 |
|
|
else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy;
|
1515 |
|
|
endcase
|
1516 |
|
|
endcase
|
1517 |
|
|
end
|
1518 |
|
|
//-----------------------------------------
|
1519 |
|
|
//mbAddrB RF read and write --> mvx_mbAddrB
|
1520 |
|
|
//-----------------------------------------
|
1521 |
|
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF
|
1522 |
|
|
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v
|
1523 |
|
|
or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3
|
1524 |
|
|
or refIdxL0_A or refIdxL0_C)
|
1525 |
|
|
if (reset_n == 0)
|
1526 |
|
|
begin
|
1527 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1528 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1529 |
|
|
mvx_mbAddrB_din <= 0;
|
1530 |
|
|
end
|
1531 |
|
|
//read for DF boundary strength decoding
|
1532 |
|
|
else if (mv_mbAddrB_rd_for_DF)
|
1533 |
|
|
begin
|
1534 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
1535 |
|
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
1536 |
|
|
mvx_mbAddrB_din <= 0;
|
1537 |
|
|
end
|
1538 |
|
|
//P_skip
|
1539 |
|
|
else if (slice_data_state == `skip_run_duration)
|
1540 |
|
|
begin
|
1541 |
|
|
if (Is_skipMB_mv_calc) //read
|
1542 |
|
|
begin
|
1543 |
|
|
if (mb_num_v == 0)
|
1544 |
|
|
begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0; end
|
1545 |
|
|
else
|
1546 |
|
|
begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end
|
1547 |
|
|
mvx_mbAddrB_wr_n <= 1;
|
1548 |
|
|
mvx_mbAddrB_wr_addr <= 0;
|
1549 |
|
|
mvx_mbAddrB_din <= 0;
|
1550 |
|
|
end
|
1551 |
|
|
else if (end_of_MB_DEC) //write
|
1552 |
|
|
begin
|
1553 |
|
|
if (mb_num_v == 8)
|
1554 |
|
|
begin
|
1555 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1556 |
|
|
mvx_mbAddrB_wr_addr <= 0; mvx_mbAddrB_din <= 0;
|
1557 |
|
|
end
|
1558 |
|
|
else
|
1559 |
|
|
begin
|
1560 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1561 |
|
|
mvx_mbAddrB_wr_addr <= mb_num_h;
|
1562 |
|
|
mvx_mbAddrB_din <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
|
1563 |
|
|
end
|
1564 |
|
|
mvx_mbAddrB_rd_addr <= 0;
|
1565 |
|
|
end
|
1566 |
|
|
else
|
1567 |
|
|
begin
|
1568 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1569 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1570 |
|
|
mvx_mbAddrB_din <= 0;
|
1571 |
|
|
end
|
1572 |
|
|
end
|
1573 |
|
|
//Inter16x16
|
1574 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
1575 |
|
|
begin
|
1576 |
|
|
if (mb_num_v == 0) //!read,write
|
1577 |
|
|
begin
|
1578 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1579 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1580 |
|
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
1581 |
|
|
end
|
1582 |
|
|
else if (mb_num_v == 8) //read,!write
|
1583 |
|
|
begin
|
1584 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
1585 |
|
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
1586 |
|
|
mvx_mbAddrB_din <= 0;
|
1587 |
|
|
end
|
1588 |
|
|
else //read,write
|
1589 |
|
|
begin
|
1590 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
1591 |
|
|
mvx_mbAddrB_wr_n <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1592 |
|
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
1593 |
|
|
end
|
1594 |
|
|
end
|
1595 |
|
|
//Inter16x8
|
1596 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
1597 |
|
|
case (mbPartIdx)
|
1598 |
|
|
0: //read,!write
|
1599 |
|
|
begin
|
1600 |
|
|
if (mb_num_v == 0) //!read,!write
|
1601 |
|
|
begin
|
1602 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1603 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1604 |
|
|
mvx_mbAddrB_din <= 0;
|
1605 |
|
|
end
|
1606 |
|
|
else //read,!write
|
1607 |
|
|
begin
|
1608 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
1609 |
|
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0;
|
1610 |
|
|
mvx_mbAddrB_din <= 0;
|
1611 |
|
|
end
|
1612 |
|
|
end
|
1613 |
|
|
1: //!read,write
|
1614 |
|
|
begin
|
1615 |
|
|
if (mb_num_v == 8) //!read,!write
|
1616 |
|
|
begin
|
1617 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
1618 |
|
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
1619 |
|
|
mvx_mbAddrB_din <= 0;
|
1620 |
|
|
end
|
1621 |
|
|
else //!read,write
|
1622 |
|
|
begin
|
1623 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1624 |
|
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1625 |
|
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
1626 |
|
|
end
|
1627 |
|
|
end
|
1628 |
|
|
default:
|
1629 |
|
|
begin
|
1630 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1631 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1632 |
|
|
mvx_mbAddrB_din <= 0;
|
1633 |
|
|
end
|
1634 |
|
|
endcase
|
1635 |
|
|
//Inter8x16
|
1636 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
1637 |
|
|
case (mbPartIdx)
|
1638 |
|
|
0: //read when mbAddrA is not available for inter pred,!write
|
1639 |
|
|
if (refIdxL0_A == 1'b1)
|
1640 |
|
|
begin
|
1641 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
1642 |
|
|
mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr <= 0;
|
1643 |
|
|
mvx_mbAddrB_din <= 0;
|
1644 |
|
|
end
|
1645 |
|
|
else
|
1646 |
|
|
begin
|
1647 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1648 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1649 |
|
|
mvx_mbAddrB_din <= 0;
|
1650 |
|
|
end
|
1651 |
|
|
1: //need read :mb_num_h == 10 && mb_num_v != 0
|
1652 |
|
|
//need write:mb_num_v != 8
|
1653 |
|
|
begin
|
1654 |
|
|
mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
|
1655 |
|
|
mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
|
1656 |
|
|
mvx_mbAddrB_rd_addr <= mb_num_h;
|
1657 |
|
|
mvx_mbAddrB_wr_addr <= mb_num_h;
|
1658 |
|
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
1659 |
|
|
end
|
1660 |
|
|
default:
|
1661 |
|
|
begin
|
1662 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1663 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1664 |
|
|
mvx_mbAddrB_din <= 0;
|
1665 |
|
|
end
|
1666 |
|
|
endcase
|
1667 |
|
|
//8x8
|
1668 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
1669 |
|
|
case (mbPartIdx)
|
1670 |
|
|
0,1: //read,!write
|
1671 |
|
|
if (mb_num_v == 0) //!read,!write
|
1672 |
|
|
begin
|
1673 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1674 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1675 |
|
|
mvx_mbAddrB_din <= 0;
|
1676 |
|
|
end
|
1677 |
|
|
else //read,!write
|
1678 |
|
|
begin
|
1679 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
1680 |
|
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0;
|
1681 |
|
|
mvx_mbAddrB_din <= 0;
|
1682 |
|
|
end
|
1683 |
|
|
2: //!read,!write
|
1684 |
|
|
begin
|
1685 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1686 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1687 |
|
|
mvx_mbAddrB_din <= 0;
|
1688 |
|
|
end
|
1689 |
|
|
3: //!read,write
|
1690 |
|
|
if (mb_num_v == 8) //!read,!write
|
1691 |
|
|
begin
|
1692 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1693 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1694 |
|
|
mvx_mbAddrB_din <= 0;
|
1695 |
|
|
end
|
1696 |
|
|
else
|
1697 |
|
|
case (sub_mb_type)
|
1698 |
|
|
0: //8x8
|
1699 |
|
|
begin
|
1700 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1701 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1702 |
|
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
1703 |
|
|
end
|
1704 |
|
|
1: //8x4
|
1705 |
|
|
case (subMbPartIdx)
|
1706 |
|
|
1:
|
1707 |
|
|
begin
|
1708 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1709 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1710 |
|
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
1711 |
|
|
end
|
1712 |
|
|
default:
|
1713 |
|
|
begin
|
1714 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1715 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1716 |
|
|
mvx_mbAddrB_din <= 0;
|
1717 |
|
|
end
|
1718 |
|
|
endcase
|
1719 |
|
|
2: //4x8
|
1720 |
|
|
case (subMbPartIdx)
|
1721 |
|
|
1:
|
1722 |
|
|
begin
|
1723 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1724 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1725 |
|
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx_CurrMb3[23:16],mvx};
|
1726 |
|
|
end
|
1727 |
|
|
default:
|
1728 |
|
|
begin
|
1729 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1730 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1731 |
|
|
mvx_mbAddrB_din <= 0;
|
1732 |
|
|
end
|
1733 |
|
|
endcase
|
1734 |
|
|
3: //4x4
|
1735 |
|
|
case (subMbPartIdx)
|
1736 |
|
|
3:
|
1737 |
|
|
begin
|
1738 |
|
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
1739 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
1740 |
|
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],
|
1741 |
|
|
mvx_CurrMb3[23:16],mvx};
|
1742 |
|
|
end
|
1743 |
|
|
default:
|
1744 |
|
|
begin
|
1745 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1746 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1747 |
|
|
mvx_mbAddrB_din <= 0;
|
1748 |
|
|
end
|
1749 |
|
|
endcase
|
1750 |
|
|
endcase
|
1751 |
|
|
endcase
|
1752 |
|
|
else
|
1753 |
|
|
begin
|
1754 |
|
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
1755 |
|
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
1756 |
|
|
mvx_mbAddrB_din <= 0;
|
1757 |
|
|
end
|
1758 |
|
|
|
1759 |
|
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF
|
1760 |
|
|
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v
|
1761 |
|
|
or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] or mvy_CurrMb2 or mvy_CurrMb3
|
1762 |
|
|
or refIdxL0_A or refIdxL0_C)
|
1763 |
|
|
if (reset_n == 0)
|
1764 |
|
|
begin
|
1765 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1766 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1767 |
|
|
mvy_mbAddrB_din <= 0;
|
1768 |
|
|
end
|
1769 |
|
|
//read for DF boundary strength decoding
|
1770 |
|
|
else if (mv_mbAddrB_rd_for_DF)
|
1771 |
|
|
begin
|
1772 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
1773 |
|
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
1774 |
|
|
mvy_mbAddrB_din <= 0;
|
1775 |
|
|
end
|
1776 |
|
|
//P_skip
|
1777 |
|
|
else if (slice_data_state == `skip_run_duration)
|
1778 |
|
|
begin
|
1779 |
|
|
if (Is_skipMB_mv_calc) //read
|
1780 |
|
|
begin
|
1781 |
|
|
if (mb_num_v == 0)
|
1782 |
|
|
begin mvy_mbAddrB_cs_n <= 1;mvy_mbAddrB_rd_addr <= 0; end
|
1783 |
|
|
else
|
1784 |
|
|
begin mvy_mbAddrB_cs_n <= 0;mvy_mbAddrB_rd_addr <= mb_num_h;end
|
1785 |
|
|
mvy_mbAddrB_wr_n <= 1;
|
1786 |
|
|
mvy_mbAddrB_wr_addr <= 0;
|
1787 |
|
|
mvy_mbAddrB_din <= 0;
|
1788 |
|
|
end
|
1789 |
|
|
else if (end_of_MB_DEC) //write
|
1790 |
|
|
begin
|
1791 |
|
|
if (mb_num_v == 8)
|
1792 |
|
|
begin
|
1793 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1794 |
|
|
mvy_mbAddrB_wr_addr <= 0; mvy_mbAddrB_din <= 0;
|
1795 |
|
|
end
|
1796 |
|
|
else
|
1797 |
|
|
begin
|
1798 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1799 |
|
|
mvy_mbAddrB_wr_addr <= mb_num_h;
|
1800 |
|
|
mvy_mbAddrB_din <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
|
1801 |
|
|
end
|
1802 |
|
|
mvy_mbAddrB_rd_addr <= 0;
|
1803 |
|
|
end
|
1804 |
|
|
else
|
1805 |
|
|
begin
|
1806 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1807 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1808 |
|
|
mvy_mbAddrB_din <= 0;
|
1809 |
|
|
end
|
1810 |
|
|
end
|
1811 |
|
|
//Inter16x16
|
1812 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
1813 |
|
|
begin
|
1814 |
|
|
if (mb_num_v == 0) //!read,write
|
1815 |
|
|
begin
|
1816 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1817 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1818 |
|
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
1819 |
|
|
end
|
1820 |
|
|
else if (mb_num_v == 8) //read,!write
|
1821 |
|
|
begin
|
1822 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
1823 |
|
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
1824 |
|
|
mvy_mbAddrB_din <= 0;
|
1825 |
|
|
end
|
1826 |
|
|
else //read,write
|
1827 |
|
|
begin
|
1828 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
1829 |
|
|
mvy_mbAddrB_wr_n <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1830 |
|
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
1831 |
|
|
end
|
1832 |
|
|
end
|
1833 |
|
|
//Inter16x8
|
1834 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
1835 |
|
|
case (mbPartIdx)
|
1836 |
|
|
0: //read,!write
|
1837 |
|
|
begin
|
1838 |
|
|
if (mb_num_v == 0) //!read,!write
|
1839 |
|
|
begin
|
1840 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1841 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1842 |
|
|
mvy_mbAddrB_din <= 0;
|
1843 |
|
|
end
|
1844 |
|
|
else //read,!write
|
1845 |
|
|
begin
|
1846 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
1847 |
|
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0;
|
1848 |
|
|
mvy_mbAddrB_din <= 0;
|
1849 |
|
|
end
|
1850 |
|
|
end
|
1851 |
|
|
1: //!read,write
|
1852 |
|
|
begin
|
1853 |
|
|
if (mb_num_v == 8) //!read,!write
|
1854 |
|
|
begin
|
1855 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
1856 |
|
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
1857 |
|
|
mvy_mbAddrB_din <= 0;
|
1858 |
|
|
end
|
1859 |
|
|
else //!read,write
|
1860 |
|
|
begin
|
1861 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1862 |
|
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1863 |
|
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
1864 |
|
|
end
|
1865 |
|
|
end
|
1866 |
|
|
default:
|
1867 |
|
|
begin
|
1868 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1869 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1870 |
|
|
mvy_mbAddrB_din <= 0;
|
1871 |
|
|
end
|
1872 |
|
|
endcase
|
1873 |
|
|
//Inter8x16
|
1874 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
1875 |
|
|
case (mbPartIdx)
|
1876 |
|
|
0: //read when mbAddrA is not available for inter pred,!write
|
1877 |
|
|
if (refIdxL0_A == 1'b1)
|
1878 |
|
|
begin
|
1879 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
1880 |
|
|
mvy_mbAddrB_rd_addr <= mb_num_h;mvy_mbAddrB_wr_addr <= 0;
|
1881 |
|
|
mvy_mbAddrB_din <= 0;
|
1882 |
|
|
end
|
1883 |
|
|
else
|
1884 |
|
|
begin
|
1885 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1886 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1887 |
|
|
mvy_mbAddrB_din <= 0;
|
1888 |
|
|
end
|
1889 |
|
|
1: //need read :mb_num_h == 10 && mb_num_v != 0
|
1890 |
|
|
//need write:mb_num_v != 8
|
1891 |
|
|
begin
|
1892 |
|
|
mvy_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
|
1893 |
|
|
mvy_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
|
1894 |
|
|
mvy_mbAddrB_rd_addr <= mb_num_h;
|
1895 |
|
|
mvy_mbAddrB_wr_addr <= mb_num_h;
|
1896 |
|
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
1897 |
|
|
end
|
1898 |
|
|
default:
|
1899 |
|
|
begin
|
1900 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1901 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1902 |
|
|
mvy_mbAddrB_din <= 0;
|
1903 |
|
|
end
|
1904 |
|
|
endcase
|
1905 |
|
|
//8x8
|
1906 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
1907 |
|
|
case (mbPartIdx)
|
1908 |
|
|
0,1: //read,!write
|
1909 |
|
|
if (mb_num_v == 0) //!read,!write
|
1910 |
|
|
begin
|
1911 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1912 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1913 |
|
|
mvy_mbAddrB_din <= 0;
|
1914 |
|
|
end
|
1915 |
|
|
else //read,!write
|
1916 |
|
|
begin
|
1917 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
1918 |
|
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0;
|
1919 |
|
|
mvy_mbAddrB_din <= 0;
|
1920 |
|
|
end
|
1921 |
|
|
2: //!read,!write
|
1922 |
|
|
begin
|
1923 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1924 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1925 |
|
|
mvy_mbAddrB_din <= 0;
|
1926 |
|
|
end
|
1927 |
|
|
3: //!read,write
|
1928 |
|
|
if (mb_num_v == 8) //!read,!write
|
1929 |
|
|
begin
|
1930 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1931 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1932 |
|
|
mvy_mbAddrB_din <= 0;
|
1933 |
|
|
end
|
1934 |
|
|
else
|
1935 |
|
|
case (sub_mb_type)
|
1936 |
|
|
0: //8x8
|
1937 |
|
|
begin
|
1938 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1939 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1940 |
|
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
1941 |
|
|
end
|
1942 |
|
|
1: //8x4
|
1943 |
|
|
case (subMbPartIdx)
|
1944 |
|
|
1:
|
1945 |
|
|
begin
|
1946 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1947 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1948 |
|
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
1949 |
|
|
end
|
1950 |
|
|
default:
|
1951 |
|
|
begin
|
1952 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1953 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1954 |
|
|
mvy_mbAddrB_din <= 0;
|
1955 |
|
|
end
|
1956 |
|
|
endcase
|
1957 |
|
|
2: //4x8
|
1958 |
|
|
case (subMbPartIdx)
|
1959 |
|
|
1:
|
1960 |
|
|
begin
|
1961 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1962 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1963 |
|
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy_CurrMb3[23:16],mvy};
|
1964 |
|
|
end
|
1965 |
|
|
default:
|
1966 |
|
|
begin
|
1967 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1968 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1969 |
|
|
mvy_mbAddrB_din <= 0;
|
1970 |
|
|
end
|
1971 |
|
|
endcase
|
1972 |
|
|
3: //4x4
|
1973 |
|
|
case (subMbPartIdx)
|
1974 |
|
|
3:
|
1975 |
|
|
begin
|
1976 |
|
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
1977 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
1978 |
|
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],
|
1979 |
|
|
mvy_CurrMb3[23:16],mvy};
|
1980 |
|
|
end
|
1981 |
|
|
default:
|
1982 |
|
|
begin
|
1983 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1984 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1985 |
|
|
mvy_mbAddrB_din <= 0;
|
1986 |
|
|
end
|
1987 |
|
|
endcase
|
1988 |
|
|
endcase
|
1989 |
|
|
endcase
|
1990 |
|
|
else
|
1991 |
|
|
begin
|
1992 |
|
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
1993 |
|
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
1994 |
|
|
mvy_mbAddrB_din <= 0;
|
1995 |
|
|
end
|
1996 |
|
|
//-----------------------------------------
|
1997 |
|
|
//mbAddrC RF read and write --> mvx_mbAddrC
|
1998 |
|
|
//-----------------------------------------
|
1999 |
|
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state
|
2000 |
|
|
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0]
|
2001 |
|
|
or refIdxL0_B or refIdxL0_C)
|
2002 |
|
|
if (reset_n == 0)
|
2003 |
|
|
begin
|
2004 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2005 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2006 |
|
|
mvx_mbAddrC_din <= 0;
|
2007 |
|
|
end
|
2008 |
|
|
//P_skip
|
2009 |
|
|
else if (slice_data_state == `skip_run_duration)
|
2010 |
|
|
begin
|
2011 |
|
|
if (Is_skipMB_mv_calc) //read
|
2012 |
|
|
begin
|
2013 |
|
|
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write
|
2014 |
|
|
begin mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_rd_addr <= 0; end
|
2015 |
|
|
else
|
2016 |
|
|
begin mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_rd_addr <= mb_num_h; end
|
2017 |
|
|
mvx_mbAddrC_wr_n <= 1;
|
2018 |
|
|
mvx_mbAddrC_wr_addr <= 0;
|
2019 |
|
|
mvx_mbAddrC_din <= 0;
|
2020 |
|
|
end
|
2021 |
|
|
else if (end_of_MB_DEC) //write
|
2022 |
|
|
begin
|
2023 |
|
|
if (mb_num_v == 8 || mb_num_h == 0) //!write
|
2024 |
|
|
begin
|
2025 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2026 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2027 |
|
|
mvx_mbAddrC_din <= 0;
|
2028 |
|
|
end
|
2029 |
|
|
else //write
|
2030 |
|
|
begin
|
2031 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2032 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2033 |
|
|
mvx_mbAddrC_din <= mvx_CurrMb0[7:0];
|
2034 |
|
|
end
|
2035 |
|
|
end
|
2036 |
|
|
else
|
2037 |
|
|
begin
|
2038 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2039 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2040 |
|
|
mvx_mbAddrC_din <= 0;
|
2041 |
|
|
end
|
2042 |
|
|
end
|
2043 |
|
|
//Inter16x16
|
2044 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
2045 |
|
|
begin
|
2046 |
|
|
if (mb_num == 0)//!read,!write
|
2047 |
|
|
begin
|
2048 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2049 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2050 |
|
|
mvx_mbAddrC_din <= 0;
|
2051 |
|
|
end
|
2052 |
|
|
else if (mb_num_v == 0)//!read,write
|
2053 |
|
|
begin
|
2054 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2055 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2056 |
|
|
mvx_mbAddrC_din <= mvx;
|
2057 |
|
|
end
|
2058 |
|
|
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write
|
2059 |
|
|
begin
|
2060 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2061 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2062 |
|
|
mvx_mbAddrC_din <= 0;
|
2063 |
|
|
end
|
2064 |
|
|
else //read,write
|
2065 |
|
|
begin
|
2066 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2067 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2068 |
|
|
mvx_mbAddrC_din <= mvx;
|
2069 |
|
|
end
|
2070 |
|
|
end
|
2071 |
|
|
//Inter16x8
|
2072 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
2073 |
|
|
begin
|
2074 |
|
|
if (mbPartIdx == 0) //upper blk,may read,no write
|
2075 |
|
|
begin
|
2076 |
|
|
if (refIdxL0_B && !refIdxL0_C) //read,!write
|
2077 |
|
|
begin
|
2078 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2079 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2080 |
|
|
mvx_mbAddrC_din <= 0;
|
2081 |
|
|
end
|
2082 |
|
|
else //!read,!write
|
2083 |
|
|
begin
|
2084 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2085 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2086 |
|
|
mvx_mbAddrC_din <= 0;
|
2087 |
|
|
end
|
2088 |
|
|
end
|
2089 |
|
|
else //bottom blk,may write,no read
|
2090 |
|
|
begin
|
2091 |
|
|
if (mb_num_h != 0) //!read,write
|
2092 |
|
|
begin
|
2093 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2094 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2095 |
|
|
mvx_mbAddrC_din <= mvx;
|
2096 |
|
|
end
|
2097 |
|
|
else //!read,!write
|
2098 |
|
|
begin
|
2099 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2100 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2101 |
|
|
mvx_mbAddrC_din <= 0;
|
2102 |
|
|
end
|
2103 |
|
|
end
|
2104 |
|
|
end
|
2105 |
|
|
//Inter8x16
|
2106 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
2107 |
|
|
case (mbPartIdx)
|
2108 |
|
|
0: //!read,write
|
2109 |
|
|
if (mb_num_v == 8)
|
2110 |
|
|
begin
|
2111 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2112 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2113 |
|
|
mvx_mbAddrC_din <= 0;
|
2114 |
|
|
end
|
2115 |
|
|
else
|
2116 |
|
|
begin
|
2117 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2118 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2119 |
|
|
mvx_mbAddrC_din <= mvx;
|
2120 |
|
|
end
|
2121 |
|
|
default: //read,!write
|
2122 |
|
|
begin
|
2123 |
|
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
2124 |
|
|
begin
|
2125 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2126 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2127 |
|
|
mvx_mbAddrC_din <= 0;
|
2128 |
|
|
end
|
2129 |
|
|
else //read,!write
|
2130 |
|
|
begin
|
2131 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2132 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2133 |
|
|
mvx_mbAddrC_din <= 0;
|
2134 |
|
|
end
|
2135 |
|
|
end
|
2136 |
|
|
endcase
|
2137 |
|
|
//Inter8x8
|
2138 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
2139 |
|
|
case (mbPartIdx)
|
2140 |
|
|
1: //read,!write
|
2141 |
|
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
2142 |
|
|
begin
|
2143 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2144 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2145 |
|
|
mvx_mbAddrC_din <= 0;
|
2146 |
|
|
end
|
2147 |
|
|
else //read,!write
|
2148 |
|
|
case (sub_mb_type)
|
2149 |
|
|
0: //8x8
|
2150 |
|
|
begin
|
2151 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2152 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2153 |
|
|
mvx_mbAddrC_din <= mvx;
|
2154 |
|
|
end
|
2155 |
|
|
1: //8x4
|
2156 |
|
|
case (subMbPartIdx)
|
2157 |
|
|
0: //read,!write
|
2158 |
|
|
begin
|
2159 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2160 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2161 |
|
|
mvx_mbAddrC_din <= mvx;
|
2162 |
|
|
end
|
2163 |
|
|
default: //!read,!write
|
2164 |
|
|
begin
|
2165 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2166 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2167 |
|
|
mvx_mbAddrC_din <= 0;
|
2168 |
|
|
end
|
2169 |
|
|
endcase
|
2170 |
|
|
2: //4x8
|
2171 |
|
|
case (subMbPartIdx)
|
2172 |
|
|
1: //read,!write
|
2173 |
|
|
begin
|
2174 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2175 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2176 |
|
|
mvx_mbAddrC_din <= mvx;
|
2177 |
|
|
end
|
2178 |
|
|
default: //!read,!write
|
2179 |
|
|
begin
|
2180 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2181 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2182 |
|
|
mvx_mbAddrC_din <= 0;
|
2183 |
|
|
end
|
2184 |
|
|
endcase
|
2185 |
|
|
3: //4x4
|
2186 |
|
|
case (subMbPartIdx)
|
2187 |
|
|
1: //read,!write
|
2188 |
|
|
begin
|
2189 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
2190 |
|
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
2191 |
|
|
mvx_mbAddrC_din <= mvx;
|
2192 |
|
|
end
|
2193 |
|
|
default: //!read,!write
|
2194 |
|
|
begin
|
2195 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2196 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2197 |
|
|
mvx_mbAddrC_din <= 0;
|
2198 |
|
|
end
|
2199 |
|
|
endcase
|
2200 |
|
|
endcase
|
2201 |
|
|
2: //!read,write
|
2202 |
|
|
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write
|
2203 |
|
|
begin
|
2204 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2205 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2206 |
|
|
mvx_mbAddrC_din <= 0;
|
2207 |
|
|
end
|
2208 |
|
|
else //!read,write
|
2209 |
|
|
case (sub_mb_type)
|
2210 |
|
|
0: //8x8
|
2211 |
|
|
begin
|
2212 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2213 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2214 |
|
|
mvx_mbAddrC_din <= mvx;
|
2215 |
|
|
end
|
2216 |
|
|
1: //8x4
|
2217 |
|
|
case (subMbPartIdx)
|
2218 |
|
|
1: //!read,write
|
2219 |
|
|
begin
|
2220 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2221 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2222 |
|
|
mvx_mbAddrC_din <= mvx;
|
2223 |
|
|
end
|
2224 |
|
|
default: //!read,!write
|
2225 |
|
|
begin
|
2226 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2227 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2228 |
|
|
mvx_mbAddrC_din <= 0;
|
2229 |
|
|
end
|
2230 |
|
|
endcase
|
2231 |
|
|
2: //4x8
|
2232 |
|
|
case (subMbPartIdx)
|
2233 |
|
|
0: //!read,write
|
2234 |
|
|
begin
|
2235 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2236 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2237 |
|
|
mvx_mbAddrC_din <= mvx;
|
2238 |
|
|
end
|
2239 |
|
|
default: //!read,!write
|
2240 |
|
|
begin
|
2241 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2242 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2243 |
|
|
mvx_mbAddrC_din <= 0;
|
2244 |
|
|
end
|
2245 |
|
|
endcase
|
2246 |
|
|
3: //4x4
|
2247 |
|
|
case (subMbPartIdx)
|
2248 |
|
|
2: //!read,write
|
2249 |
|
|
begin
|
2250 |
|
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
2251 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
2252 |
|
|
mvx_mbAddrC_din <= mvx;
|
2253 |
|
|
end
|
2254 |
|
|
default: //!read,!write
|
2255 |
|
|
begin
|
2256 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2257 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2258 |
|
|
mvx_mbAddrC_din <= 0;
|
2259 |
|
|
end
|
2260 |
|
|
endcase
|
2261 |
|
|
endcase
|
2262 |
|
|
default:
|
2263 |
|
|
begin
|
2264 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2265 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2266 |
|
|
mvx_mbAddrC_din <= 0;
|
2267 |
|
|
end
|
2268 |
|
|
endcase
|
2269 |
|
|
else
|
2270 |
|
|
begin
|
2271 |
|
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
2272 |
|
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
2273 |
|
|
mvx_mbAddrC_din <= 0;
|
2274 |
|
|
end
|
2275 |
|
|
|
2276 |
|
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state
|
2277 |
|
|
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0]
|
2278 |
|
|
or refIdxL0_B or refIdxL0_C)
|
2279 |
|
|
if (reset_n == 0)
|
2280 |
|
|
begin
|
2281 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2282 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2283 |
|
|
mvy_mbAddrC_din <= 0;
|
2284 |
|
|
end
|
2285 |
|
|
//P_skip
|
2286 |
|
|
else if (slice_data_state == `skip_run_duration)
|
2287 |
|
|
begin
|
2288 |
|
|
if (Is_skipMB_mv_calc) //read
|
2289 |
|
|
begin
|
2290 |
|
|
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write
|
2291 |
|
|
begin mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_rd_addr <= 0; end
|
2292 |
|
|
else
|
2293 |
|
|
begin mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_rd_addr <= mb_num_h; end
|
2294 |
|
|
mvy_mbAddrC_wr_n <= 1;
|
2295 |
|
|
mvy_mbAddrC_wr_addr <= 0;
|
2296 |
|
|
mvy_mbAddrC_din <= 0;
|
2297 |
|
|
end
|
2298 |
|
|
else if (end_of_MB_DEC) //write
|
2299 |
|
|
begin
|
2300 |
|
|
if (mb_num_v == 8 || mb_num_h == 0) //!write
|
2301 |
|
|
begin
|
2302 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2303 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2304 |
|
|
mvy_mbAddrC_din <= 0;
|
2305 |
|
|
end
|
2306 |
|
|
else //write
|
2307 |
|
|
begin
|
2308 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2309 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2310 |
|
|
mvy_mbAddrC_din <= mvy_CurrMb0[7:0];
|
2311 |
|
|
end
|
2312 |
|
|
end
|
2313 |
|
|
else
|
2314 |
|
|
begin
|
2315 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2316 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2317 |
|
|
mvy_mbAddrC_din <= 0;
|
2318 |
|
|
end
|
2319 |
|
|
end
|
2320 |
|
|
//Inter16x16
|
2321 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
2322 |
|
|
begin
|
2323 |
|
|
if (mb_num == 0)//!read,!write
|
2324 |
|
|
begin
|
2325 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2326 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2327 |
|
|
mvy_mbAddrC_din <= 0;
|
2328 |
|
|
end
|
2329 |
|
|
else if (mb_num_v == 0)//!read,write
|
2330 |
|
|
begin
|
2331 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2332 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2333 |
|
|
mvy_mbAddrC_din <= mvy;
|
2334 |
|
|
end
|
2335 |
|
|
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write
|
2336 |
|
|
begin
|
2337 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2338 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2339 |
|
|
mvy_mbAddrC_din <= 0;
|
2340 |
|
|
end
|
2341 |
|
|
else //read,write
|
2342 |
|
|
begin
|
2343 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2344 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2345 |
|
|
mvy_mbAddrC_din <= mvy;
|
2346 |
|
|
end
|
2347 |
|
|
end
|
2348 |
|
|
//Inter16x8
|
2349 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
2350 |
|
|
begin
|
2351 |
|
|
if (mbPartIdx == 0) //upper blk,may read,no write
|
2352 |
|
|
begin
|
2353 |
|
|
if (refIdxL0_B && !refIdxL0_C) //read,!write
|
2354 |
|
|
begin
|
2355 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2356 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2357 |
|
|
mvy_mbAddrC_din <= 0;
|
2358 |
|
|
end
|
2359 |
|
|
else //!read,!write
|
2360 |
|
|
begin
|
2361 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2362 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2363 |
|
|
mvy_mbAddrC_din <= 0;
|
2364 |
|
|
end
|
2365 |
|
|
end
|
2366 |
|
|
else //bottom blk,may write,no read
|
2367 |
|
|
begin
|
2368 |
|
|
if (mb_num_h != 0) //!read,write
|
2369 |
|
|
begin
|
2370 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2371 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2372 |
|
|
mvy_mbAddrC_din <= mvy;
|
2373 |
|
|
end
|
2374 |
|
|
else //!read,!write
|
2375 |
|
|
begin
|
2376 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2377 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2378 |
|
|
mvy_mbAddrC_din <= 0;
|
2379 |
|
|
end
|
2380 |
|
|
end
|
2381 |
|
|
end
|
2382 |
|
|
//Inter8x16
|
2383 |
|
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
2384 |
|
|
case (mbPartIdx)
|
2385 |
|
|
0: //!read,write
|
2386 |
|
|
if (mb_num_v == 8)
|
2387 |
|
|
begin
|
2388 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2389 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2390 |
|
|
mvy_mbAddrC_din <= 0;
|
2391 |
|
|
end
|
2392 |
|
|
else
|
2393 |
|
|
begin
|
2394 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2395 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2396 |
|
|
mvy_mbAddrC_din <= mvy;
|
2397 |
|
|
end
|
2398 |
|
|
default: //read,!write
|
2399 |
|
|
begin
|
2400 |
|
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
2401 |
|
|
begin
|
2402 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2403 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2404 |
|
|
mvy_mbAddrC_din <= 0;
|
2405 |
|
|
end
|
2406 |
|
|
else //read,!write
|
2407 |
|
|
begin
|
2408 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2409 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2410 |
|
|
mvy_mbAddrC_din <= 0;
|
2411 |
|
|
end
|
2412 |
|
|
end
|
2413 |
|
|
endcase
|
2414 |
|
|
//Inter8x8
|
2415 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
2416 |
|
|
case (mbPartIdx)
|
2417 |
|
|
1: //read,!write
|
2418 |
|
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
2419 |
|
|
begin
|
2420 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2421 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2422 |
|
|
mvy_mbAddrC_din <= 0;
|
2423 |
|
|
end
|
2424 |
|
|
else //read,!write
|
2425 |
|
|
case (sub_mb_type)
|
2426 |
|
|
0: //8x8
|
2427 |
|
|
begin
|
2428 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2429 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2430 |
|
|
mvy_mbAddrC_din <= mvy;
|
2431 |
|
|
end
|
2432 |
|
|
1: //8x4
|
2433 |
|
|
case (subMbPartIdx)
|
2434 |
|
|
0: //read,!write
|
2435 |
|
|
begin
|
2436 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2437 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2438 |
|
|
mvy_mbAddrC_din <= mvy;
|
2439 |
|
|
end
|
2440 |
|
|
default: //!read,!write
|
2441 |
|
|
begin
|
2442 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2443 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2444 |
|
|
mvy_mbAddrC_din <= 0;
|
2445 |
|
|
end
|
2446 |
|
|
endcase
|
2447 |
|
|
2: //4x8
|
2448 |
|
|
case (subMbPartIdx)
|
2449 |
|
|
1: //read,!write
|
2450 |
|
|
begin
|
2451 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2452 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2453 |
|
|
mvy_mbAddrC_din <= mvy;
|
2454 |
|
|
end
|
2455 |
|
|
default: //!read,!write
|
2456 |
|
|
begin
|
2457 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2458 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2459 |
|
|
mvy_mbAddrC_din <= 0;
|
2460 |
|
|
end
|
2461 |
|
|
endcase
|
2462 |
|
|
3: //4x4
|
2463 |
|
|
case (subMbPartIdx)
|
2464 |
|
|
1: //read,!write
|
2465 |
|
|
begin
|
2466 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
2467 |
|
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
2468 |
|
|
mvy_mbAddrC_din <= mvy;
|
2469 |
|
|
end
|
2470 |
|
|
default: //!read,!write
|
2471 |
|
|
begin
|
2472 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2473 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2474 |
|
|
mvy_mbAddrC_din <= 0;
|
2475 |
|
|
end
|
2476 |
|
|
endcase
|
2477 |
|
|
endcase
|
2478 |
|
|
2: //!read,write
|
2479 |
|
|
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write
|
2480 |
|
|
begin
|
2481 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2482 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2483 |
|
|
mvy_mbAddrC_din <= 0;
|
2484 |
|
|
end
|
2485 |
|
|
else //!read,write
|
2486 |
|
|
case (sub_mb_type)
|
2487 |
|
|
0: //8x8
|
2488 |
|
|
begin
|
2489 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2490 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2491 |
|
|
mvy_mbAddrC_din <= mvy;
|
2492 |
|
|
end
|
2493 |
|
|
1: //8x4
|
2494 |
|
|
case (subMbPartIdx)
|
2495 |
|
|
1: //!read,write
|
2496 |
|
|
begin
|
2497 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2498 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2499 |
|
|
mvy_mbAddrC_din <= mvy;
|
2500 |
|
|
end
|
2501 |
|
|
default: //!read,!write
|
2502 |
|
|
begin
|
2503 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2504 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2505 |
|
|
mvy_mbAddrC_din <= 0;
|
2506 |
|
|
end
|
2507 |
|
|
endcase
|
2508 |
|
|
2: //4x8
|
2509 |
|
|
case (subMbPartIdx)
|
2510 |
|
|
0: //!read,write
|
2511 |
|
|
begin
|
2512 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2513 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2514 |
|
|
mvy_mbAddrC_din <= mvy;
|
2515 |
|
|
end
|
2516 |
|
|
default: //!read,!write
|
2517 |
|
|
begin
|
2518 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2519 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2520 |
|
|
mvy_mbAddrC_din <= 0;
|
2521 |
|
|
end
|
2522 |
|
|
endcase
|
2523 |
|
|
3: //4x4
|
2524 |
|
|
case (subMbPartIdx)
|
2525 |
|
|
2: //!read,write
|
2526 |
|
|
begin
|
2527 |
|
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
2528 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
2529 |
|
|
mvy_mbAddrC_din <= mvy;
|
2530 |
|
|
end
|
2531 |
|
|
default: //!read,!write
|
2532 |
|
|
begin
|
2533 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2534 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2535 |
|
|
mvy_mbAddrC_din <= 0;
|
2536 |
|
|
end
|
2537 |
|
|
endcase
|
2538 |
|
|
endcase
|
2539 |
|
|
default:
|
2540 |
|
|
begin
|
2541 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2542 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2543 |
|
|
mvy_mbAddrC_din <= 0;
|
2544 |
|
|
end
|
2545 |
|
|
endcase
|
2546 |
|
|
else
|
2547 |
|
|
begin
|
2548 |
|
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
2549 |
|
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
2550 |
|
|
mvy_mbAddrC_din <= 0;
|
2551 |
|
|
end
|
2552 |
|
|
|
2553 |
|
|
//-------------------------------
|
2554 |
|
|
//mbAddrD write --> mvx_mbAddrD
|
2555 |
|
|
//-------------------------------
|
2556 |
|
|
//mvx_mbAddrD
|
2557 |
|
|
reg [7:0] mvx_mbAddrD_subMB;
|
2558 |
|
|
reg [7:0] mvx_mbAddrD_MB,mvx_mbAddrD_MB_tmp;
|
2559 |
|
|
always @ (posedge clk)
|
2560 |
|
|
if (reset_n == 0)
|
2561 |
|
|
mvx_mbAddrD_subMB <= 0;
|
2562 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
2563 |
|
|
case (mbPartIdx)
|
2564 |
|
|
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
2565 |
|
|
mvx_mbAddrD_subMB <= mvx_mbAddrA[7:0];
|
2566 |
|
|
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
2567 |
|
|
mvx_mbAddrD_subMB <= mvx_mbAddrA[23:16];
|
2568 |
|
|
endcase
|
2569 |
|
|
|
2570 |
|
|
always @ (posedge clk)
|
2571 |
|
|
if (reset_n == 1'b0)
|
2572 |
|
|
mvx_mbAddrD_MB_tmp <= 0;
|
2573 |
|
|
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0)
|
2574 |
|
|
mvx_mbAddrD_MB_tmp <= (mv_is16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb3[31:24];
|
2575 |
|
|
|
2576 |
|
|
always @ (posedge clk)
|
2577 |
|
|
if (reset_n == 1'b0)
|
2578 |
|
|
mvx_mbAddrD_MB <= 0;
|
2579 |
|
|
else if (end_of_MB_DEC && mb_num_h == 10)
|
2580 |
|
|
mvx_mbAddrD_MB <= mvx_mbAddrD_MB_tmp;
|
2581 |
|
|
|
2582 |
|
|
assign mvx_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvx_mbAddrD_subMB:mvx_mbAddrD_MB;
|
2583 |
|
|
|
2584 |
|
|
//mvy_mbAddrD
|
2585 |
|
|
reg [7:0] mvy_mbAddrD_subMB;
|
2586 |
|
|
reg [7:0] mvy_mbAddrD_MB,mvy_mbAddrD_MB_tmp;
|
2587 |
|
|
always @ (posedge clk)
|
2588 |
|
|
if (reset_n == 0)
|
2589 |
|
|
mvy_mbAddrD_subMB <= 0;
|
2590 |
|
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
2591 |
|
|
case (mbPartIdx)
|
2592 |
|
|
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
2593 |
|
|
mvy_mbAddrD_subMB <= mvy_mbAddrA[7:0];
|
2594 |
|
|
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
2595 |
|
|
mvy_mbAddrD_subMB <= mvy_mbAddrA[23:16];
|
2596 |
|
|
endcase
|
2597 |
|
|
|
2598 |
|
|
always @ (posedge clk)
|
2599 |
|
|
if (reset_n == 1'b0)
|
2600 |
|
|
mvy_mbAddrD_MB_tmp <= 0;
|
2601 |
|
|
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0)
|
2602 |
|
|
mvy_mbAddrD_MB_tmp <= (mv_is16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb3[31:24];
|
2603 |
|
|
|
2604 |
|
|
always @ (posedge clk)
|
2605 |
|
|
if (reset_n == 1'b0)
|
2606 |
|
|
mvy_mbAddrD_MB <= 0;
|
2607 |
|
|
else if (end_of_MB_DEC && mb_num_h == 10)
|
2608 |
|
|
mvy_mbAddrD_MB <= mvy_mbAddrD_MB_tmp;
|
2609 |
|
|
|
2610 |
|
|
assign mvy_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvy_mbAddrD_subMB:mvy_mbAddrD_MB;
|
2611 |
|
|
|
2612 |
|
|
endmodule
|