| 1 |
2 |
eexuke |
//--------------------------------------------------------------------------------------------------
|
| 2 |
|
|
// Design : nova
|
| 3 |
|
|
// Author(s) : Ke Xu
|
| 4 |
|
|
// Email : eexuke@yahoo.com
|
| 5 |
|
|
// File : Intra4x4_PredMode_decoding.v
|
| 6 |
|
|
// Generated : May 31, 2005
|
| 7 |
|
|
// Copyright (C) 2008 Ke Xu
|
| 8 |
|
|
//-------------------------------------------------------------------------------------------------
|
| 9 |
|
|
// Description
|
| 10 |
|
|
// Decoding the prediction mode for Intra4x4
|
| 11 |
|
|
//-------------------------------------------------------------------------------------------------
|
| 12 |
|
|
|
| 13 |
|
|
// synopsys translate_off
|
| 14 |
|
|
`include "timescale.v"
|
| 15 |
|
|
// synopsys translate_on
|
| 16 |
|
|
`include "nova_defines.v"
|
| 17 |
|
|
|
| 18 |
|
|
module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v,
|
| 19 |
|
|
MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag,
|
| 20 |
|
|
rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout,
|
| 21 |
|
|
|
| 22 |
|
|
Intra4x4PredMode_CurrMb,
|
| 23 |
|
|
Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr,
|
| 24 |
|
|
Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din
|
| 25 |
|
|
);
|
| 26 |
|
|
input clk,reset_n;
|
| 27 |
|
|
input [2:0] mb_pred_state;
|
| 28 |
|
|
input [3:0] luma4x4BlkIdx;
|
| 29 |
|
|
input [3:0] mb_num_h,mb_num_v;
|
| 30 |
|
|
input [1:0] MBTypeGen_mbAddrA;
|
| 31 |
|
|
input [21:0] MBTypeGen_mbAddrB_reg;
|
| 32 |
|
|
input constrained_intra_pred_flag;
|
| 33 |
|
|
input [2:0] rem_intra4x4_pred_mode;
|
| 34 |
|
|
input prev_intra4x4_pred_mode_flag;
|
| 35 |
|
|
input [15:0] Intra4x4PredMode_mbAddrB_dout;
|
| 36 |
|
|
//input [8:0] pic_num;
|
| 37 |
|
|
|
| 38 |
|
|
output [63:0] Intra4x4PredMode_CurrMb;
|
| 39 |
|
|
output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
|
| 40 |
|
|
output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
|
| 41 |
|
|
output [15:0] Intra4x4PredMode_mbAddrB_din;
|
| 42 |
|
|
|
| 43 |
|
|
reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
|
| 44 |
|
|
reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
|
| 45 |
|
|
reg [15:0] Intra4x4PredMode_mbAddrB_din;
|
| 46 |
|
|
|
| 47 |
|
|
wire mbAddrA_availability;
|
| 48 |
|
|
wire mbAddrB_availability;
|
| 49 |
|
|
wire mbAddrA;
|
| 50 |
|
|
wire mbAddrB;
|
| 51 |
|
|
wire [3:0] predIntra4x4PredMode; //prediction mode obtained at `prev_intra4x4_pred_mode_flag_s
|
| 52 |
|
|
reg dcOnlyPredictionFlag;
|
| 53 |
|
|
reg [15:0] Intra4x4PredMode_mbAddrA;
|
| 54 |
|
|
reg [63:0] Intra4x4PredMode_CurrMb;
|
| 55 |
|
|
reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB;
|
| 56 |
|
|
|
| 57 |
|
|
reg [3:0] rem_Intra4x4PredMode; //prediction mode obtained at `rem_intra4x4_pred_mode_s
|
| 58 |
|
|
reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode
|
| 59 |
|
|
|
| 60 |
|
|
|
| 61 |
|
|
reg [1:0] MBTypeGen_mbAddrB;
|
| 62 |
|
|
always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
|
| 63 |
|
|
case (mb_num_h)
|
| 64 |
|
|
|
| 65 |
|
|
1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
|
| 66 |
|
|
2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
|
| 67 |
|
|
3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
|
| 68 |
|
|
4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
|
| 69 |
|
|
5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
|
| 70 |
|
|
6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
|
| 71 |
|
|
7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
|
| 72 |
|
|
8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
|
| 73 |
|
|
9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
|
| 74 |
|
|
10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
|
| 75 |
|
|
default:MBTypeGen_mbAddrB <= 0;
|
| 76 |
|
|
endcase
|
| 77 |
|
|
|
| 78 |
|
|
//neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order
|
| 79 |
|
|
assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2
|
| 80 |
|
|
|| luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1;
|
| 81 |
|
|
|
| 82 |
|
|
assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1
|
| 83 |
|
|
|| luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1;
|
| 84 |
|
|
|
| 85 |
|
|
assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8
|
| 86 |
|
|
|| luma4x4BlkIdx == 10)? 1'b0:1'b1; //0:left MB;1:curr MB
|
| 87 |
|
|
|
| 88 |
|
|
assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4
|
| 89 |
|
|
|| luma4x4BlkIdx == 5)? 1'b0:1'b1; //0:upper MB;1:curr MB
|
| 90 |
|
|
|
| 91 |
|
|
//dcOnlyPredictionFlag
|
| 92 |
|
|
always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or
|
| 93 |
|
|
MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag)
|
| 94 |
|
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
| 95 |
|
|
begin
|
| 96 |
|
|
if (mbAddrA_availability == 0)
|
| 97 |
|
|
dcOnlyPredictionFlag <= 1;
|
| 98 |
|
|
else if (mbAddrB_availability == 0)
|
| 99 |
|
|
dcOnlyPredictionFlag <= 1;
|
| 100 |
|
|
else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1)
|
| 101 |
|
|
dcOnlyPredictionFlag <= 1;
|
| 102 |
|
|
else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1)
|
| 103 |
|
|
dcOnlyPredictionFlag <= 1;
|
| 104 |
|
|
else
|
| 105 |
|
|
dcOnlyPredictionFlag <= 0;
|
| 106 |
|
|
end
|
| 107 |
|
|
else
|
| 108 |
|
|
dcOnlyPredictionFlag <= 0;
|
| 109 |
|
|
//Intra4x4PredModeA
|
| 110 |
|
|
always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA
|
| 111 |
|
|
or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
|
| 112 |
|
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
| 113 |
|
|
begin
|
| 114 |
|
|
if (dcOnlyPredictionFlag == 1)
|
| 115 |
|
|
Intra4x4PredModeA <= 2;
|
| 116 |
|
|
else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4
|
| 117 |
|
|
Intra4x4PredModeA <= 2;
|
| 118 |
|
|
else
|
| 119 |
|
|
case (luma4x4BlkIdx)
|
| 120 |
|
|
|
| 121 |
|
|
1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0];
|
| 122 |
|
|
2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4];
|
| 123 |
|
|
3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8];
|
| 124 |
|
|
4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4];
|
| 125 |
|
|
5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16];
|
| 126 |
|
|
6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12];
|
| 127 |
|
|
7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24];
|
| 128 |
|
|
8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8];
|
| 129 |
|
|
9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32];
|
| 130 |
|
|
10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12];
|
| 131 |
|
|
11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40];
|
| 132 |
|
|
12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36];
|
| 133 |
|
|
13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48];
|
| 134 |
|
|
14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44];
|
| 135 |
|
|
15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56];
|
| 136 |
|
|
endcase
|
| 137 |
|
|
end
|
| 138 |
|
|
else
|
| 139 |
|
|
Intra4x4PredModeA <= 0;
|
| 140 |
|
|
//Intra4x4PredModeB
|
| 141 |
|
|
always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB
|
| 142 |
|
|
or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
|
| 143 |
|
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
| 144 |
|
|
begin
|
| 145 |
|
|
if (dcOnlyPredictionFlag == 1)
|
| 146 |
|
|
Intra4x4PredModeB <= 2;
|
| 147 |
|
|
else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4) //not coded in Intra4x4
|
| 148 |
|
|
Intra4x4PredModeB <= 2;
|
| 149 |
|
|
else
|
| 150 |
|
|
case (luma4x4BlkIdx)
|
| 151 |
|
|
|
| 152 |
|
|
1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8];
|
| 153 |
|
|
2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0];
|
| 154 |
|
|
3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4];
|
| 155 |
|
|
4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4];
|
| 156 |
|
|
5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0];
|
| 157 |
|
|
6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16];
|
| 158 |
|
|
7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20];
|
| 159 |
|
|
8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8];
|
| 160 |
|
|
9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12];
|
| 161 |
|
|
10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32];
|
| 162 |
|
|
11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36];
|
| 163 |
|
|
12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24];
|
| 164 |
|
|
13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28];
|
| 165 |
|
|
14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48];
|
| 166 |
|
|
15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52];
|
| 167 |
|
|
endcase
|
| 168 |
|
|
end
|
| 169 |
|
|
else
|
| 170 |
|
|
Intra4x4PredModeB <= 0;
|
| 171 |
|
|
//obtain prediction mode at prev_intra4x4_pred_mode_flag_s
|
| 172 |
|
|
assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB;
|
| 173 |
|
|
always @ (posedge clk)
|
| 174 |
|
|
if (reset_n == 0)
|
| 175 |
|
|
predIntra4x4PredMode_reg <= 0;
|
| 176 |
|
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0)
|
| 177 |
|
|
predIntra4x4PredMode_reg <= predIntra4x4PredMode;
|
| 178 |
|
|
//obtain prediction mode at rem_intra4x4_pred_mode_s
|
| 179 |
|
|
always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg)
|
| 180 |
|
|
if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
| 181 |
|
|
rem_Intra4x4PredMode <= ({1'b0,rem_intra4x4_pred_mode} < predIntra4x4PredMode_reg)?
|
| 182 |
|
|
{1'b0,rem_intra4x4_pred_mode}:(rem_intra4x4_pred_mode + 1);
|
| 183 |
|
|
else
|
| 184 |
|
|
rem_Intra4x4PredMode <= 0;
|
| 185 |
|
|
//-----------------------------
|
| 186 |
|
|
//Intra4x4PredMode_CurrMb write
|
| 187 |
|
|
//-----------------------------
|
| 188 |
|
|
always @ (posedge clk)
|
| 189 |
|
|
if (reset_n == 0)
|
| 190 |
|
|
Intra4x4PredMode_CurrMb <= 0;
|
| 191 |
|
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
| 192 |
|
|
case (luma4x4BlkIdx)
|
| 193 |
|
|
|
| 194 |
|
|
1 :Intra4x4PredMode_CurrMb[7:4] <= predIntra4x4PredMode;
|
| 195 |
|
|
2 :Intra4x4PredMode_CurrMb[11:8] <= predIntra4x4PredMode;
|
| 196 |
|
|
3 :Intra4x4PredMode_CurrMb[15:12] <= predIntra4x4PredMode;
|
| 197 |
|
|
4 :Intra4x4PredMode_CurrMb[19:16] <= predIntra4x4PredMode;
|
| 198 |
|
|
5 :Intra4x4PredMode_CurrMb[23:20] <= predIntra4x4PredMode;
|
| 199 |
|
|
6 :Intra4x4PredMode_CurrMb[27:24] <= predIntra4x4PredMode;
|
| 200 |
|
|
7 :Intra4x4PredMode_CurrMb[31:28] <= predIntra4x4PredMode;
|
| 201 |
|
|
8 :Intra4x4PredMode_CurrMb[35:32] <= predIntra4x4PredMode;
|
| 202 |
|
|
9 :Intra4x4PredMode_CurrMb[39:36] <= predIntra4x4PredMode;
|
| 203 |
|
|
10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode;
|
| 204 |
|
|
11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode;
|
| 205 |
|
|
12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode;
|
| 206 |
|
|
13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode;
|
| 207 |
|
|
14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode;
|
| 208 |
|
|
15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode;
|
| 209 |
|
|
endcase
|
| 210 |
|
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
| 211 |
|
|
case (luma4x4BlkIdx)
|
| 212 |
|
|
|
| 213 |
|
|
1 :Intra4x4PredMode_CurrMb[7:4] <= rem_Intra4x4PredMode;
|
| 214 |
|
|
2 :Intra4x4PredMode_CurrMb[11:8] <= rem_Intra4x4PredMode;
|
| 215 |
|
|
3 :Intra4x4PredMode_CurrMb[15:12] <= rem_Intra4x4PredMode;
|
| 216 |
|
|
4 :Intra4x4PredMode_CurrMb[19:16] <= rem_Intra4x4PredMode;
|
| 217 |
|
|
5 :Intra4x4PredMode_CurrMb[23:20] <= rem_Intra4x4PredMode;
|
| 218 |
|
|
6 :Intra4x4PredMode_CurrMb[27:24] <= rem_Intra4x4PredMode;
|
| 219 |
|
|
7 :Intra4x4PredMode_CurrMb[31:28] <= rem_Intra4x4PredMode;
|
| 220 |
|
|
8 :Intra4x4PredMode_CurrMb[35:32] <= rem_Intra4x4PredMode;
|
| 221 |
|
|
9 :Intra4x4PredMode_CurrMb[39:36] <= rem_Intra4x4PredMode;
|
| 222 |
|
|
10 :Intra4x4PredMode_CurrMb[43:40] <= rem_Intra4x4PredMode;
|
| 223 |
|
|
11 :Intra4x4PredMode_CurrMb[47:44] <= rem_Intra4x4PredMode;
|
| 224 |
|
|
12 :Intra4x4PredMode_CurrMb[51:48] <= rem_Intra4x4PredMode;
|
| 225 |
|
|
13 :Intra4x4PredMode_CurrMb[55:52] <= rem_Intra4x4PredMode;
|
| 226 |
|
|
14 :Intra4x4PredMode_CurrMb[59:56] <= rem_Intra4x4PredMode;
|
| 227 |
|
|
15 :Intra4x4PredMode_CurrMb[63:60] <= rem_Intra4x4PredMode;
|
| 228 |
|
|
endcase
|
| 229 |
|
|
//------------------------------
|
| 230 |
|
|
//Intra4x4PredMode_mbAddrA write
|
| 231 |
|
|
//------------------------------
|
| 232 |
|
|
always @ (posedge clk)
|
| 233 |
|
|
if (reset_n == 0)
|
| 234 |
|
|
Intra4x4PredMode_mbAddrA <= 0;
|
| 235 |
|
|
else if (mb_num_h != 10) //mb_num_h == 10,no need to store mbAddrA
|
| 236 |
|
|
begin
|
| 237 |
|
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
| 238 |
|
|
case (luma4x4BlkIdx)
|
| 239 |
|
|
5: Intra4x4PredMode_mbAddrA[3:0] <= predIntra4x4PredMode;
|
| 240 |
|
|
7: Intra4x4PredMode_mbAddrA[7:4] <= predIntra4x4PredMode;
|
| 241 |
|
|
13:Intra4x4PredMode_mbAddrA[11:8] <= predIntra4x4PredMode;
|
| 242 |
|
|
15:Intra4x4PredMode_mbAddrA[15:12] <= predIntra4x4PredMode;
|
| 243 |
|
|
endcase
|
| 244 |
|
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
| 245 |
|
|
case (luma4x4BlkIdx)
|
| 246 |
|
|
5: Intra4x4PredMode_mbAddrA[3:0] <= rem_Intra4x4PredMode;
|
| 247 |
|
|
7: Intra4x4PredMode_mbAddrA[7:4] <= rem_Intra4x4PredMode;
|
| 248 |
|
|
13:Intra4x4PredMode_mbAddrA[11:8] <= rem_Intra4x4PredMode;
|
| 249 |
|
|
15:Intra4x4PredMode_mbAddrA[15:12] <= rem_Intra4x4PredMode;
|
| 250 |
|
|
endcase
|
| 251 |
|
|
end
|
| 252 |
|
|
//----------------------------------------
|
| 253 |
|
|
//Intra4x4PredMode_mbAddrB RF read & write
|
| 254 |
|
|
//----------------------------------------
|
| 255 |
|
|
always @ (reset_n or mb_num_v or mb_num_h or luma4x4BlkIdx or mb_pred_state or prev_intra4x4_pred_mode_flag
|
| 256 |
|
|
or Intra4x4PredMode_CurrMb or predIntra4x4PredMode or rem_Intra4x4PredMode)
|
| 257 |
|
|
if (reset_n == 0)
|
| 258 |
|
|
begin
|
| 259 |
|
|
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
| 260 |
|
|
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
| 261 |
|
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
| 262 |
|
|
end
|
| 263 |
|
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
| 264 |
|
|
begin
|
| 265 |
|
|
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
| 266 |
|
|
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
| 267 |
|
|
if (prev_intra4x4_pred_mode_flag == 1 && luma4x4BlkIdx == 15 && mb_num_v != 8)//write is conditional when mb_num_v != 8
|
| 268 |
|
|
begin
|
| 269 |
|
|
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
| 270 |
|
|
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
| 271 |
|
|
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
| 272 |
|
|
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],predIntra4x4PredMode};
|
| 273 |
|
|
end
|
| 274 |
|
|
else
|
| 275 |
|
|
begin
|
| 276 |
|
|
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
| 277 |
|
|
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
| 278 |
|
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
| 279 |
|
|
end
|
| 280 |
|
|
end
|
| 281 |
|
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
| 282 |
|
|
begin
|
| 283 |
|
|
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
| 284 |
|
|
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
| 285 |
|
|
if (luma4x4BlkIdx == 15 && mb_num_v != 8) //write is conditional when mb_num_v != 8
|
| 286 |
|
|
begin
|
| 287 |
|
|
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
| 288 |
|
|
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
| 289 |
|
|
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
| 290 |
|
|
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],rem_Intra4x4PredMode};
|
| 291 |
|
|
end
|
| 292 |
|
|
else
|
| 293 |
|
|
begin
|
| 294 |
|
|
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
| 295 |
|
|
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
| 296 |
|
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
| 297 |
|
|
end
|
| 298 |
|
|
end
|
| 299 |
|
|
else
|
| 300 |
|
|
begin
|
| 301 |
|
|
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
| 302 |
|
|
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
| 303 |
|
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
| 304 |
|
|
end
|
| 305 |
|
|
|
| 306 |
|
|
/*
|
| 307 |
|
|
// synopsys translate_off
|
| 308 |
|
|
integer tracefile;
|
| 309 |
|
|
wire [6:0] mb_num;
|
| 310 |
|
|
assign mb_num = mb_num_v * 11 + mb_num_h;
|
| 311 |
|
|
|
| 312 |
|
|
initial
|
| 313 |
|
|
begin
|
| 314 |
|
|
tracefile = $fopen("intra_4x4_trace.txt");
|
| 315 |
|
|
end
|
| 316 |
|
|
always @ (posedge clk)
|
| 317 |
|
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
| 318 |
|
|
begin
|
| 319 |
|
|
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
| 320 |
|
|
pic_num,mb_num,luma4x4BlkIdx,predIntra4x4PredMode);
|
| 321 |
|
|
if (luma4x4BlkIdx == 15)
|
| 322 |
|
|
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
| 323 |
|
|
end
|
| 324 |
|
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
| 325 |
|
|
begin
|
| 326 |
|
|
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
| 327 |
|
|
pic_num,mb_num,luma4x4BlkIdx,rem_Intra4x4PredMode);
|
| 328 |
|
|
if (luma4x4BlkIdx == 15)
|
| 329 |
|
|
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
| 330 |
|
|
end
|
| 331 |
|
|
// synopsys translate_on
|
| 332 |
|
|
*/
|
| 333 |
|
|
endmodule
|
