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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : ext_frame_RAM0_wrapper.v
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// Generated : April 23,2006
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit)
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// Sync Read,Sync Write
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//-------------------------------------------------------------------------------------------------
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// Revise log
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// 1.July 23,2006
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// Change the ext_frame_RAM0 from async read to sync read.
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//
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module ext_frame_RAM0_wrapper (clk,reset_n,ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,dis_frame_RAM_din,ext_frame_RAM0_data,
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pic_num,slice_header_s6);
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input clk;
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input reset_n;
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input ext_frame_RAM0_cs_n;
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input ext_frame_RAM0_wr;
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input [13:0] ext_frame_RAM0_addr;
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input [31:0] dis_frame_RAM_din;
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input [5:0] pic_num;
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input slice_header_s6;
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output [31:0] ext_frame_RAM0_data;
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reg [31:0] ext_frame_RAM0 [0:9503];
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reg [31:0] ext_frame_RAM0_data;
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always @ (posedge clk)
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if (!ext_frame_RAM0_cs_n && ext_frame_RAM0_wr)
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ext_frame_RAM0[ext_frame_RAM0_addr] <= dis_frame_RAM_din;
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//assign ext_frame_RAM0_data = (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr)? ext_frame_RAM0[ext_frame_RAM0_addr]:32'bz;
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always @ (posedge clk)
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if (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr)
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ext_frame_RAM0_data <= ext_frame_RAM0[ext_frame_RAM0_addr];
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// synopsys translate_off
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integer tracefile_display;
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integer tracefile_verify;
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integer mb_num;
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integer j;
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reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3;
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reg [31:0] Cb_out0,Cb_out1;
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reg [31:0] Cr_out0,Cr_out1;
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reg [8:0] pic_num_ext;
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parameter display = 1;
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parameter verify = 1;
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always @ (negedge reset_n or pic_num)
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if (reset_n == 1'b0)
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pic_num_ext <= 0;
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else
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pic_num_ext <= pic_num_ext + 1;
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always @ (posedge clk)
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if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b1)
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begin
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if (display == 1'b1) //display
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begin
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tracefile_display = $fopen("nova_display.log","a");
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for (j= 0; j < 9504; j= j + 1)
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begin
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$fdisplay (tracefile_display,"%h",ext_frame_RAM0[j]);
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end
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$fclose(tracefile_display);
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end
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if (verify == 1'b1) //verify
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begin
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tracefile_verify = $fopen("nova_MB_output.log","a");
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for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1)
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begin
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$fdisplay (tracefile_verify,"-------------------------------------------");
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$fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num);
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$fdisplay (tracefile_verify,"-------------------------------------------");
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$fdisplay (tracefile_verify," luma 16x16 block:");
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for (j = 0; j < 16; j = j + 1)
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begin
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luma_out0 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44];
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luma_out1 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+1];
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luma_out2 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+2];
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luma_out3 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+3];
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$fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H",
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luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24],
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luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24],
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luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24],
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luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]);
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if (j == 3 || j == 7 || j == 11)
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$fdisplay (tracefile_verify, "");
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end
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$fdisplay (tracefile_verify," Chroma Cb 8x8 block:");
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for (j = 0; j < 8; j = j + 1)
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begin
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Cb_out0 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22];
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Cb_out1 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1];
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$fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H",
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Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24],
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Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]);
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if (j == 3)
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$fdisplay (tracefile_verify, "");
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end
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$fdisplay (tracefile_verify," Chroma Cr 8x8 block:");
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for (j = 0; j < 8; j = j + 1)
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begin
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Cr_out0 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22];
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Cr_out1 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1];
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$fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H",
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Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24],
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Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]);
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if (j == 3)
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$fdisplay (tracefile_verify, "");
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end
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end
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$fclose(tracefile_verify);
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end
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end
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// synopsys translate_on
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endmodule
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