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[/] [nova/] [tags/] [Start/] [src/] [nova_defines.v] - Blame information for rev 11

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//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email           : eexuke@yahoo.com
// File      : nova_defines.v
// Generated : April 20,2008
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Global parameters of nova
//-------------------------------------------------------------------------------------------------
 
//-------------------------------------------------------------------------------------------------
//BitStream_controller parameters
//-------------------------------------------------------------------------------------------------
 
//---Beha_BitStream_ram.v---
`define Beha_Bitstream_ram_size 131071  //Beha_Bitstream_ram size
 
//bitstream_gclk_gen
//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame
//1)50,000 cycles are not enough for foreman300,8th   frame.So increase to 51,000 cycles
//2)51,000 cycles are not enough for foreman300,11th  frame.So increase to 51,500 cycles
//3)51,500 cycles are not enough for foreman300,38th  frame.So increase to 52,000 cycles
//4)52,000 cycles are not enough for foreman300,66th  frame.So increase to 52,500 cycles
//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles
//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles
//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read,
//the cycles required to decode each frame increased
//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles
//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles
`define cycles_per_frame0 17'd45000
`define cycles_per_frame1 17'd50000 //fast enough for akiyo300
`define cycles_per_frame2       17'd57300 //preferred frequency for most critical sequence:foreman300
`define cycles_per_frame3       17'd70000
 
//---pc_decoding---
`define rst_consumed_bits_sel 3'b000
`define exp_golomb            3'b001
`define fixed_length          3'b011
`define dependent_variable    3'b010
`define cavlc_consumed        3'b110
`define trailing_bits         3'b111
`define pcm_alignment         3'b101
 
//---syntax_decoding---
//mb_type_general
`define MB_Inter16x16            4'b0000
`define MB_Inter16x8             4'b0001
`define MB_Inter8x16             4'b0010
`define MB_P_8x8                 4'b0011
`define MB_P_8x8ref0             4'b0100
`define MB_P_skip                4'b0101
`define MB_I_PCM                 4'b0110
`define MB_type_reserved0        4'b0111
`define MB_Intra16x16_CBPChroma0 4'b1000
`define MB_Intra16x16_CBPChroma1 4'b1001
`define MB_Intra16x16_CBPChroma2 4'b1010
`define MB_type_reserved1        4'b1011
`define MB_Intra4x4              4'b1100
`define MB_type_reserved2        4'b1101
`define MB_type_reserved3        4'b1110
`define MB_type_rst              4'b1111
 
//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg
`define MB_addrA_addrB_Inter      2'b00
`define MB_addrA_addrB_P_skip     2'b01
`define MB_addrA_addrB_Intra16x16 2'b10
`define MB_addrA_addrB_Intra4x4   2'b11
 
//MBTypeGen_mbAddrD
`define MB_addrD_Inter_P_skip 1'b0
`define MB_addrD_Intra        1'b1
 
//Gray-encoded FSM states to reduce power consumption during state switching
`define rst_parser                  2'b00
`define start_code_prefix 2'b01
`define nal_unit                            2'b11
 
`define rst_nal_unit                                                       3'b000
`define forbidden_zero_bit_2_nal_unit_type 3'b001
`define slice_layer_non_IDR_rbsp                             3'b011
`define slice_layer_IDR_rbsp                                   3'b010
`define seq_parameter_set_rbsp                         3'b110
`define pic_parameter_set_rbsp                       3'b111
`define rbsp_trailing_one_bit                                  3'b101
`define rbsp_trailing_zero_bits                  3'b100
 
`define rst_slice_layer_wo_partitioning 2'b00
`define slice_header                                        2'b01
`define slice_data                                            2'b11
 
`define rst_seq_parameter_set                     4'b0000
`define fixed_header                              4'b0001
`define level_idc_s                               4'b0011
`define seq_parameter_set_id_sps_s                4'b0010
`define log2_max_frame_num_minus4_s               4'b0110
`define pic_order_cnt_type_s                      4'b0111
`define log2_max_pic_order_cnt_lsb_minus4_s       4'b0101
`define num_ref_frames_s                          4'b0100
`define gaps_in_frame_num_value_allowed_flag_s    4'b1100
`define pic_width_in_mbs_minus1_s                 4'b1101
`define pic_height_in_map_units_minus1_s          4'b1111
`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110
`define vui_parameter_present_flag_s              4'b1010
 
`define rst_pic_parameter_set                                                                                              4'b0000
`define pic_parameter_set_id_pps_s                                                                               4'b0001
`define seq_parameter_set_id_pps_s                                                                               4'b0011
`define entropy_coding_mode_flag_2_pic_order_present_flag                            4'b0010
`define num_slice_groups_minus1_s                                                                                        4'b0110
`define num_ref_idx_l0_active_minus1_pps_s                                                           4'b0111
`define num_ref_idx_l1_active_minus1_pps_s                                                           4'b0101
`define weighted_pred_flag_2_weighted_bipred_idc                                                 4'b0100
`define pic_init_qp_minus26_s                                                                                              4'b1100
`define pic_init_qs_minus26_s                                                                                              4'b1101
`define chroma_qp_index_offset_s                                                                                         4'b1111
`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110
 
`define rst_slice_header                                                                      4'b0000
`define first_mb_in_slice_s                                                           4'b0001
`define slice_type_s                                                                            4'b0011
`define pic_parameter_set_id_slice_header_s                   4'b0010
`define frame_num_s                                                                               4'b0110
`define idr_pic_id_s                                                                            4'b0111
`define pic_order_cnt_lsb_s                                                           4'b0101
`define num_ref_idx_active_override_flag_s                    4'b0100
`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100
`define ref_pic_list_reordering                                             4'b1101
`define dec_ref_pic_marking                                                           4'b1111
`define slice_qp_delta_s                                                                      4'b1110
`define disable_deblocking_filter_idc_s                         4'b1010
`define slice_alpha_c0_offset_div2_s                                    4'b1011
`define slice_beta_offset_div2_s                                                  4'b1001
 
//ref_pic_list_reordering_state 
`define rst_ref_pic_list_reordering                 3'b000
`define ref_pic_list_reordering_flag_l0_s 3'b001
 
//dec_ref_pic_marking_state 
`define rst_dec_ref_pic_marking                                                                           2'b00
`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01
`define adaptive_ref_pic_marking_mode_flag_s                                              2'b11
 
`define rst_slice_data                 4'b0000
`define mb_skip_run_s                          4'b0001
`define skip_run_duration                    4'b0011
`define mb_type_s                                        4'b0010
`define pcm_alignment_zero_bit_s 4'b0110
`define pcm_byte_s                               4'b0111
`define sub_mb_pred                              4'b0101
`define mb_pred                                    4'b0100
`define coded_block_pattern_s      4'b1100
`define mb_qp_delta_s                          4'b1101
`define residual                                         4'b1111
`define mb_num_update                          4'b1110
 
//mb_pred_state 
`define rst_mb_pred                                                3'b000
`define prev_intra4x4_pred_mode_flag_s 3'b001
`define rem_intra4x4_pred_mode_s             3'b011
`define intra_chroma_pred_mode_s             3'b010
`define ref_idx_l0_s                                       3'b110
`define mvd_l0_s                                                     3'b111
 
//sub_mb_pred_state 
`define rst_sub_mb_pred  2'b00
`define sub_mb_type_s      2'b01
`define sub_ref_idx_l0_s 2'b11
`define sub_mvd_l0_s       2'b10
 
`define rst_residual                  4'b0000
`define Intra16x16DCLevel_s       4'b0001
`define Intra16x16ACLevel_s       4'b0011
`define Intra16x16ACLevel_0_s 4'b0010
`define LumaLevel_s                           4'b0110
`define LumaLevel_0_s                 4'b0111
`define ChromaDCLevel_Cb_s    4'b0101
`define ChromaDCLevel_Cr_s        4'b0100
`define ChromaACLevel_Cb_s        4'b1100
`define ChromaACLevel_Cr_s        4'b1101
`define ChromaACLevel_0_s                 4'b1110
 
`define rst_cavlc_decoder                    4'b0000
`define nAnB_decoding_s                4'b0001
`define nC_decoding_s                          4'b0011
`define NumCoeffTrailingOnes_LUT 4'b0010
`define TrailingOnesSignFlag       4'b0110
`define LevelPrefix                              4'b0111
`define LevelSuffix                              4'b0101
`define total_zeros_LUT                4'b0100
`define run_before_LUT                 4'b1100
`define RunOfZeros                               4'b1101
`define LevelRunCombination          4'b1111
 
//---LumaLevel_mbAddrB_RF---
`define LumaLevel_mbAddrB_RF_data_width 20
`define LumaLevel_mbAddrB_RF_data_depth 11
//---ChromaLevel_Cb_mbAddrB_RF---                       
`define ChromaLevel_Cb_mbAddrB_RF_data_width 10
`define ChromaLevel_Cb_mbAddrB_RF_data_depth 11
//---ChromaLevel_Cr_mbAddrB_RF---
`define ChromaLevel_Cr_mbAddrB_RF_data_width 10
`define ChromaLevel_Cr_mbAddrB_RF_data_depth 11
 
//---Intra4x4_PredMode_RF---
`define Intra4x4_PredMode_RF_data_width 16
`define Intra4x4_PredMode_RF_data_depth 11
 
//---mvx_mbAddrB_RF---
`define mvx_mbAddrB_RF_data_width 32
`define mvx_mbAddrB_RF_data_depth 11
//---mvy_mbAddrB_RF---
`define mvy_mbAddrB_RF_data_width 32
`define mvy_mbAddrB_RF_data_depth 11
//---mvx_mbAddrB_RF---
`define mvx_mbAddrC_RF_data_width 8
`define mvx_mbAddrC_RF_data_depth 10
//---mvy_mbAddrB_RF---
`define mvy_mbAddrC_RF_data_width 8
`define mvy_mbAddrC_RF_data_depth 10
 
//-------------------------------------------------------------------------------------------------
//Intra prediction parameters
//-------------------------------------------------------------------------------------------------
 
//---Intra_mbAddrB_RAM---
`define Intra_mbAddrB_RAM_data_width 32
`define Intra_mbAddrB_RAM_data_depth 88
 
//---Intra_pred_PE,Intra_pred_pipeline,Intra_pred_reg_ctrl---
`define Intra4x4_Vertical            4'b0000
`define Intra4x4_Horizontal          4'b0001
`define Intra4x4_DC                  4'b0010
`define Intra4x4_Diagonal_Down_Left  4'b0011
`define Intra4x4_Diagonal_Down_Right 4'b0100
`define Intra4x4_Vertical_Right      4'b0101
`define Intra4x4_Horizontal_Down     4'b0110
`define Intra4x4_Vertical_Left       4'b0111
`define Intra4x4_Horizontal_Up       4'b1000
 
`define Intra16x16_Vertical          2'b00
`define Intra16x16_Horizontal        2'b01
`define Intra16x16_DC                2'b10
`define Intra16x16_Plane             2'b11
 
`define Intra_chroma_DC              2'b00
`define Intra_chroma_Horizontal      2'b01
`define Intra_chroma_Vertical        2'b10
`define Intra_chroma_Plane           2'b11
 
//-------------------------------------------------------------------------------------------------
//Inter prediction parameters
//-------------------------------------------------------------------------------------------------
 
//---Inter_pred_LPE,Inter_pred_pipeline,Inter_pred_reg_ctrl,Inter_pred_sliding_window---
`define pos_Int 4'b0000
`define pos_a   4'b0100
`define pos_b   4'b1000
`define pos_c   4'b1100
`define pos_d   4'b0001
`define pos_e   4'b0101
`define pos_f   4'b1001
`define pos_g   4'b1101
`define pos_h   4'b0010
`define pos_i   4'b0110
`define pos_j   4'b1010
`define pos_k   4'b1110
`define pos_n   4'b0011
`define pos_p   4'b0111
`define pos_q   4'b1011
`define pos_r   4'b1111
 
//---Inter_pred_pipeline
`define pic_width       8'd176
`define pic_height      8'd144
`define half_pic_width  7'd88
`define half_pic_height 7'd72
 
//-------------------------------------------------------------------------------------------------
//Deblocking filter parameters
//-------------------------------------------------------------------------------------------------
 
//---bs_decoding---
`define I8x8   2'b00 //size of inter prediction partitions
`define I16x8    2'b01
`define I8x16    2'b10
`define I16x16 2'b11
 
//---DF_mbAddrA_RAM---
`define DF_mbAddrA_RAM_data_width 32
`define DF_mbAddrA_RAM_data_depth 32
 
//---DF_mbAddrB_RAM---
`define DF_mbAddrB_RAM_data_width 32
`define DF_mbAddrB_RAM_data_depth 352
 
//---rec_DF_RAM0---
`define rec_DF_RAM0_data_width 32
`define rec_DF_RAM0_data_depth 96
 
//---rec_DF_RAM1---
`define rec_DF_RAM1_data_width 32
`define rec_DF_RAM1_data_depth 96
 
//-------------------------------------------------------------------------------------------------
//Hybrid pipeline control parameters
//-------------------------------------------------------------------------------------------------
 

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[/] [nova/] [tags/] [Start/] [src/] [nova_defines.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	2	eexuke	`//--------------------------------------------------------------------------------------------------`
2			`// Design : nova`
3			`// Author(s) : Ke Xu`
4			`// Email : eexuke@yahoo.com`
5			`// File : nova_defines.v`
6			`// Generated : April 20,2008`
7			`// Copyright (C) 2008 Ke Xu`
8			`//-------------------------------------------------------------------------------------------------`
9			`// Description`
10			`// Global parameters of nova`
11			`//-------------------------------------------------------------------------------------------------`
12
13			`//-------------------------------------------------------------------------------------------------`
14			`//BitStream_controller parameters`
15			`//-------------------------------------------------------------------------------------------------`
16
17			`//---Beha_BitStream_ram.v---`
18			`define Beha_Bitstream_ram_size 131071 //Beha_Bitstream_ram size
19
20			`//bitstream_gclk_gen`
21			`//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame`
22			`//1)50,000 cycles are not enough for foreman300,8th frame.So increase to 51,000 cycles`
23			`//2)51,000 cycles are not enough for foreman300,11th frame.So increase to 51,500 cycles`
24			`//3)51,500 cycles are not enough for foreman300,38th frame.So increase to 52,000 cycles`
25			`//4)52,000 cycles are not enough for foreman300,66th frame.So increase to 52,500 cycles`
26			`//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles`
27			`//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles`
28			`//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read,`
29			`//the cycles required to decode each frame increased`
30			`//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles`
31			`//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles`
32			`define cycles_per_frame0 17'd45000
33			`define cycles_per_frame1 17'd50000 //fast enough for akiyo300
34			`define cycles_per_frame2 17'd57300 //preferred frequency for most critical sequence:foreman300
35			`define cycles_per_frame3 17'd70000
36
37			`//---pc_decoding---`
38			`define rst_consumed_bits_sel 3'b000
39			`define exp_golomb 3'b001
40			`define fixed_length 3'b011
41			`define dependent_variable 3'b010
42			`define cavlc_consumed 3'b110
43			`define trailing_bits 3'b111
44			`define pcm_alignment 3'b101
45
46			`//---syntax_decoding---`
47			`//mb_type_general`
48			`define MB_Inter16x16 4'b0000
49			`define MB_Inter16x8 4'b0001
50			`define MB_Inter8x16 4'b0010
51			`define MB_P_8x8 4'b0011
52			`define MB_P_8x8ref0 4'b0100
53			`define MB_P_skip 4'b0101
54			`define MB_I_PCM 4'b0110
55			`define MB_type_reserved0 4'b0111
56			`define MB_Intra16x16_CBPChroma0 4'b1000
57			`define MB_Intra16x16_CBPChroma1 4'b1001
58			`define MB_Intra16x16_CBPChroma2 4'b1010
59			`define MB_type_reserved1 4'b1011
60			`define MB_Intra4x4 4'b1100
61			`define MB_type_reserved2 4'b1101
62			`define MB_type_reserved3 4'b1110
63			`define MB_type_rst 4'b1111
64
65			`//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg`
66			`define MB_addrA_addrB_Inter 2'b00
67			`define MB_addrA_addrB_P_skip 2'b01
68			`define MB_addrA_addrB_Intra16x16 2'b10
69			`define MB_addrA_addrB_Intra4x4 2'b11
70
71			`//MBTypeGen_mbAddrD`
72			`define MB_addrD_Inter_P_skip 1'b0
73			`define MB_addrD_Intra 1'b1
74
75			`//Gray-encoded FSM states to reduce power consumption during state switching`
76			`define rst_parser 2'b00
77			`define start_code_prefix 2'b01
78			`define nal_unit 2'b11
79
80			`define rst_nal_unit 3'b000
81			`define forbidden_zero_bit_2_nal_unit_type 3'b001
82			`define slice_layer_non_IDR_rbsp 3'b011
83			`define slice_layer_IDR_rbsp 3'b010
84			`define seq_parameter_set_rbsp 3'b110
85			`define pic_parameter_set_rbsp 3'b111
86			`define rbsp_trailing_one_bit 3'b101
87			`define rbsp_trailing_zero_bits 3'b100
88
89			`define rst_slice_layer_wo_partitioning 2'b00
90			`define slice_header 2'b01
91			`define slice_data 2'b11
92
93			`define rst_seq_parameter_set 4'b0000
94			`define fixed_header 4'b0001
95			`define level_idc_s 4'b0011
96			`define seq_parameter_set_id_sps_s 4'b0010
97			`define log2_max_frame_num_minus4_s 4'b0110
98			`define pic_order_cnt_type_s 4'b0111
99			`define log2_max_pic_order_cnt_lsb_minus4_s 4'b0101
100			`define num_ref_frames_s 4'b0100
101			`define gaps_in_frame_num_value_allowed_flag_s 4'b1100
102			`define pic_width_in_mbs_minus1_s 4'b1101
103			`define pic_height_in_map_units_minus1_s 4'b1111
104			`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110
105			`define vui_parameter_present_flag_s 4'b1010
106
107			`define rst_pic_parameter_set 4'b0000
108			`define pic_parameter_set_id_pps_s 4'b0001
109			`define seq_parameter_set_id_pps_s 4'b0011
110			`define entropy_coding_mode_flag_2_pic_order_present_flag 4'b0010
111			`define num_slice_groups_minus1_s 4'b0110
112			`define num_ref_idx_l0_active_minus1_pps_s 4'b0111
113			`define num_ref_idx_l1_active_minus1_pps_s 4'b0101
114			`define weighted_pred_flag_2_weighted_bipred_idc 4'b0100
115			`define pic_init_qp_minus26_s 4'b1100
116			`define pic_init_qs_minus26_s 4'b1101
117			`define chroma_qp_index_offset_s 4'b1111
118			`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110
119
120			`define rst_slice_header 4'b0000
121			`define first_mb_in_slice_s 4'b0001
122			`define slice_type_s 4'b0011
123			`define pic_parameter_set_id_slice_header_s 4'b0010
124			`define frame_num_s 4'b0110
125			`define idr_pic_id_s 4'b0111
126			`define pic_order_cnt_lsb_s 4'b0101
127			`define num_ref_idx_active_override_flag_s 4'b0100
128			`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100
129			`define ref_pic_list_reordering 4'b1101
130			`define dec_ref_pic_marking 4'b1111
131			`define slice_qp_delta_s 4'b1110
132			`define disable_deblocking_filter_idc_s 4'b1010
133			`define slice_alpha_c0_offset_div2_s 4'b1011
134			`define slice_beta_offset_div2_s 4'b1001
135
136			`//ref_pic_list_reordering_state`
137			`define rst_ref_pic_list_reordering 3'b000
138			`define ref_pic_list_reordering_flag_l0_s 3'b001
139
140			`//dec_ref_pic_marking_state`
141			`define rst_dec_ref_pic_marking 2'b00
142			`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01
143			`define adaptive_ref_pic_marking_mode_flag_s 2'b11
144
145			`define rst_slice_data 4'b0000
146			`define mb_skip_run_s 4'b0001
147			`define skip_run_duration 4'b0011
148			`define mb_type_s 4'b0010
149			`define pcm_alignment_zero_bit_s 4'b0110
150			`define pcm_byte_s 4'b0111
151			`define sub_mb_pred 4'b0101
152			`define mb_pred 4'b0100
153			`define coded_block_pattern_s 4'b1100
154			`define mb_qp_delta_s 4'b1101
155			`define residual 4'b1111
156			`define mb_num_update 4'b1110
157
158			`//mb_pred_state`
159			`define rst_mb_pred 3'b000
160			`define prev_intra4x4_pred_mode_flag_s 3'b001
161			`define rem_intra4x4_pred_mode_s 3'b011
162			`define intra_chroma_pred_mode_s 3'b010
163			`define ref_idx_l0_s 3'b110
164			`define mvd_l0_s 3'b111
165
166			`//sub_mb_pred_state`
167			`define rst_sub_mb_pred 2'b00
168			`define sub_mb_type_s 2'b01
169			`define sub_ref_idx_l0_s 2'b11
170			`define sub_mvd_l0_s 2'b10
171
172			`define rst_residual 4'b0000
173			`define Intra16x16DCLevel_s 4'b0001
174			`define Intra16x16ACLevel_s 4'b0011
175			`define Intra16x16ACLevel_0_s 4'b0010
176			`define LumaLevel_s 4'b0110
177			`define LumaLevel_0_s 4'b0111
178			`define ChromaDCLevel_Cb_s 4'b0101
179			`define ChromaDCLevel_Cr_s 4'b0100
180			`define ChromaACLevel_Cb_s 4'b1100
181			`define ChromaACLevel_Cr_s 4'b1101
182			`define ChromaACLevel_0_s 4'b1110
183
184			`define rst_cavlc_decoder 4'b0000
185			`define nAnB_decoding_s 4'b0001
186			`define nC_decoding_s 4'b0011
187			`define NumCoeffTrailingOnes_LUT 4'b0010
188			`define TrailingOnesSignFlag 4'b0110
189			`define LevelPrefix 4'b0111
190			`define LevelSuffix 4'b0101
191			`define total_zeros_LUT 4'b0100
192			`define run_before_LUT 4'b1100
193			`define RunOfZeros 4'b1101
194			`define LevelRunCombination 4'b1111
195
196			`//---LumaLevel_mbAddrB_RF---`
197			`define LumaLevel_mbAddrB_RF_data_width 20
198			`define LumaLevel_mbAddrB_RF_data_depth 11
199			`//---ChromaLevel_Cb_mbAddrB_RF---`
200			`define ChromaLevel_Cb_mbAddrB_RF_data_width 10
201			`define ChromaLevel_Cb_mbAddrB_RF_data_depth 11
202			`//---ChromaLevel_Cr_mbAddrB_RF---`
203			`define ChromaLevel_Cr_mbAddrB_RF_data_width 10
204			`define ChromaLevel_Cr_mbAddrB_RF_data_depth 11
205
206			`//---Intra4x4_PredMode_RF---`
207			`define Intra4x4_PredMode_RF_data_width 16
208			`define Intra4x4_PredMode_RF_data_depth 11
209
210			`//---mvx_mbAddrB_RF---`
211			`define mvx_mbAddrB_RF_data_width 32
212			`define mvx_mbAddrB_RF_data_depth 11
213			`//---mvy_mbAddrB_RF---`
214			`define mvy_mbAddrB_RF_data_width 32
215			`define mvy_mbAddrB_RF_data_depth 11
216			`//---mvx_mbAddrB_RF---`
217			`define mvx_mbAddrC_RF_data_width 8
218			`define mvx_mbAddrC_RF_data_depth 10
219			`//---mvy_mbAddrB_RF---`
220			`define mvy_mbAddrC_RF_data_width 8
221			`define mvy_mbAddrC_RF_data_depth 10
222
223			`//-------------------------------------------------------------------------------------------------`
224			`//Intra prediction parameters`
225			`//-------------------------------------------------------------------------------------------------`
226
227			`//---Intra_mbAddrB_RAM---`
228			`define Intra_mbAddrB_RAM_data_width 32
229			`define Intra_mbAddrB_RAM_data_depth 88
230
231			`//---Intra_pred_PE,Intra_pred_pipeline,Intra_pred_reg_ctrl---`
232			`define Intra4x4_Vertical 4'b0000
233			`define Intra4x4_Horizontal 4'b0001
234			`define Intra4x4_DC 4'b0010
235			`define Intra4x4_Diagonal_Down_Left 4'b0011
236			`define Intra4x4_Diagonal_Down_Right 4'b0100
237			`define Intra4x4_Vertical_Right 4'b0101
238			`define Intra4x4_Horizontal_Down 4'b0110
239			`define Intra4x4_Vertical_Left 4'b0111
240			`define Intra4x4_Horizontal_Up 4'b1000
241
242			`define Intra16x16_Vertical 2'b00
243			`define Intra16x16_Horizontal 2'b01
244			`define Intra16x16_DC 2'b10
245			`define Intra16x16_Plane 2'b11
246
247			`define Intra_chroma_DC 2'b00
248			`define Intra_chroma_Horizontal 2'b01
249			`define Intra_chroma_Vertical 2'b10
250			`define Intra_chroma_Plane 2'b11
251
252			`//-------------------------------------------------------------------------------------------------`
253			`//Inter prediction parameters`
254			`//-------------------------------------------------------------------------------------------------`
255
256			`//---Inter_pred_LPE,Inter_pred_pipeline,Inter_pred_reg_ctrl,Inter_pred_sliding_window---`
257			`define pos_Int 4'b0000
258			`define pos_a 4'b0100
259			`define pos_b 4'b1000
260			`define pos_c 4'b1100
261			`define pos_d 4'b0001
262			`define pos_e 4'b0101
263			`define pos_f 4'b1001
264			`define pos_g 4'b1101
265			`define pos_h 4'b0010
266			`define pos_i 4'b0110
267			`define pos_j 4'b1010
268			`define pos_k 4'b1110
269			`define pos_n 4'b0011
270			`define pos_p 4'b0111
271			`define pos_q 4'b1011
272			`define pos_r 4'b1111
273
274			`//---Inter_pred_pipeline`
275			`define pic_width 8'd176
276			`define pic_height 8'd144
277			`define half_pic_width 7'd88
278			`define half_pic_height 7'd72
279
280			`//-------------------------------------------------------------------------------------------------`
281			`//Deblocking filter parameters`
282			`//-------------------------------------------------------------------------------------------------`
283
284			`//---bs_decoding---`
285			`define I8x8 2'b00 //size of inter prediction partitions
286			`define I16x8 2'b01
287			`define I8x16 2'b10
288			`define I16x16 2'b11
289
290			`//---DF_mbAddrA_RAM---`
291			`define DF_mbAddrA_RAM_data_width 32
292			`define DF_mbAddrA_RAM_data_depth 32
293
294			`//---DF_mbAddrB_RAM---`
295			`define DF_mbAddrB_RAM_data_width 32
296			`define DF_mbAddrB_RAM_data_depth 352
297
298			`//---rec_DF_RAM0---`
299			`define rec_DF_RAM0_data_width 32
300			`define rec_DF_RAM0_data_depth 96
301
302			`//---rec_DF_RAM1---`
303			`define rec_DF_RAM1_data_width 32
304			`define rec_DF_RAM1_data_depth 96
305
306			`//-------------------------------------------------------------------------------------------------`
307			`//Hybrid pipeline control parameters`
308			`//-------------------------------------------------------------------------------------------------`
309