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[/] [nova/] [tags/] [Start/] [src/] [rec_DF_RAM_ctrl.v] - Blame information for rev 11

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1 2 eexuke 
//--------------------------------------------------------------------------------------------------
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// Design    : nova
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// Author(s) : Ke Xu
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// Email           : eexuke@yahoo.com
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// File      : rec_DF_RAM_ctrl.v
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// Generated : Nov 3, 2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Controller for rec_DF_RAM0 & rec_DF_RAM1,single port SRAM
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// write during reconstruction,read during DF
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// assume "_wr" & "_rd" are both high active
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module rec_DF_RAM_ctrl (clk,reset_n,disable_DF,end_of_MB_DEC,
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        DF_edge_counter_MR,one_edge_counter_MR,
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        blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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        blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM0_dout,rec_DF_RAM1_dout,
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        rec_DF_RAM_dout,
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        rec_DF_RAM0_wr,rec_DF_RAM0_rd,rec_DF_RAM0_addr,rec_DF_RAM0_din,
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        rec_DF_RAM1_wr,rec_DF_RAM1_rd,rec_DF_RAM1_addr,rec_DF_RAM1_din);
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        input clk,reset_n;
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        input disable_DF;
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        input end_of_MB_DEC;
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        input [5:0] DF_edge_counter_MR;
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        input [1:0] one_edge_counter_MR;
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        input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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        input [2:0] blk4x4_sum_counter;
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        input [4:0] blk4x4_rec_counter_2_raster_order;
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        input [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout;
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        output [31:0] rec_DF_RAM_dout;
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        output rec_DF_RAM0_wr;
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        output rec_DF_RAM0_rd;
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        output [6:0]rec_DF_RAM0_addr;
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        output [31:0] rec_DF_RAM0_din;
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        output rec_DF_RAM1_wr;
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        output rec_DF_RAM1_rd;
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        output [6:0]rec_DF_RAM1_addr;
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        output [31:0] rec_DF_RAM1_din;
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        reg rec_DF_RAM0_wr;
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        reg rec_DF_RAM0_rd;
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        reg [6:0]rec_DF_RAM0_addr;
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        reg [31:0] rec_DF_RAM0_din;
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        reg rec_DF_RAM1_wr;
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        reg rec_DF_RAM1_rd;
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        reg [6:0]rec_DF_RAM1_addr;
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        reg [31:0] rec_DF_RAM1_din;
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        //-----------------------------------------------------------------
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        //Write:after reconstruction
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        //-----------------------------------------------------------------
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        wire rec_DF_RAM_wr;
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        wire [4:0] rec_DF_RAM_wr_addr_blk4x4;
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        wire [1:0] rec_DF_RAM_wr_addr_offset;
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        wire [6:0] rec_DF_RAM_wr_addr;
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        wire [31:0] rec_DF_RAM_din;
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        assign rec_DF_RAM_wr = !disable_DF && (blk4x4_sum_counter[2] != 1'b1);
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        assign rec_DF_RAM_wr_addr_blk4x4 = {5{rec_DF_RAM_wr}} & blk4x4_rec_counter_2_raster_order;
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        assign rec_DF_RAM_wr_addr_offset = {2{rec_DF_RAM_wr}} & blk4x4_sum_counter[1:0];
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        assign rec_DF_RAM_wr_addr = {rec_DF_RAM_wr_addr_blk4x4,2'b0} + rec_DF_RAM_wr_addr_offset;
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        assign rec_DF_RAM_din = (rec_DF_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0;
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        //-----------------------------------------------------------------
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        //Read:during deblocking filter
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        //-----------------------------------------------------------------
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        wire rec_DF_RAM_rd;
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        reg [4:0] rec_DF_RAM_rd_addr_blk4x4;
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        wire [1:0] rec_DF_RAM_rd_addr_offset;
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        wire [6:0] rec_DF_RAM_rd_addr;
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        assign rec_DF_RAM_rd = ((DF_edge_counter_MR[5] == 1'b0 && (DF_edge_counter_MR[3:0] == 4'd0 ||
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        DF_edge_counter_MR[3:0] == 4'd1     ||  DF_edge_counter_MR[3:0] == 4'd2 || DF_edge_counter_MR[3:0] == 4'd3 ||
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        DF_edge_counter_MR[3:0] == 4'd6     ||  DF_edge_counter_MR[3:0] == 4'd7 || DF_edge_counter_MR[3:0] == 4'd10||
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        DF_edge_counter_MR[3:0] == 4'd11))  || (DF_edge_counter_MR[5] == 1'b1   && DF_edge_counter_MR[2] == 1'b0));
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        always @ (rec_DF_RAM_rd or DF_edge_counter_MR)
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                if (rec_DF_RAM_rd)
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                        case (DF_edge_counter_MR)
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                                6'd0 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd0;
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                                6'd1 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd1;
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                                6'd2 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd4;
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                                6'd3 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd5;
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                                6'd6 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd2;
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                                6'd7 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd6;
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                                6'd10:rec_DF_RAM_rd_addr_blk4x4 <= 5'd3;
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                                6'd11:rec_DF_RAM_rd_addr_blk4x4 <= 5'd7;
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                                6'd16:rec_DF_RAM_rd_addr_blk4x4 <= 5'd8;
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                                6'd17:rec_DF_RAM_rd_addr_blk4x4 <= 5'd9;
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                                6'd18:rec_DF_RAM_rd_addr_blk4x4 <= 5'd12;
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                                6'd19:rec_DF_RAM_rd_addr_blk4x4 <= 5'd13;
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                                6'd22:rec_DF_RAM_rd_addr_blk4x4 <= 5'd10;
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                                6'd23:rec_DF_RAM_rd_addr_blk4x4 <= 5'd14;
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                                6'd26:rec_DF_RAM_rd_addr_blk4x4 <= 5'd11;
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                                6'd27:rec_DF_RAM_rd_addr_blk4x4 <= 5'd15;
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                                6'd32:rec_DF_RAM_rd_addr_blk4x4 <= 5'd16;
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                                6'd33:rec_DF_RAM_rd_addr_blk4x4 <= 5'd17;
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                                6'd34:rec_DF_RAM_rd_addr_blk4x4 <= 5'd18;
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                                6'd35:rec_DF_RAM_rd_addr_blk4x4 <= 5'd19;
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                                6'd40:rec_DF_RAM_rd_addr_blk4x4 <= 5'd20;
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                                6'd41:rec_DF_RAM_rd_addr_blk4x4 <= 5'd21;
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                                6'd42:rec_DF_RAM_rd_addr_blk4x4 <= 5'd22;
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                                6'd43:rec_DF_RAM_rd_addr_blk4x4 <= 5'd23;
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                                default:rec_DF_RAM_rd_addr_blk4x4 <= 0;
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                        endcase
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                else
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                        rec_DF_RAM_rd_addr_blk4x4 <= 0;
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        assign rec_DF_RAM_rd_addr_offset = one_edge_counter_MR;
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        assign rec_DF_RAM_rd_addr = {rec_DF_RAM_rd_addr_blk4x4,2'b0} + rec_DF_RAM_rd_addr_offset;
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        //----------------------------------------------------------------------------------
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        //Generate control signals for rec_DF_RAM0 & rec_DF_RAM1
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        //----------------------------------------------------------------------------------
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        reg rec_DF_RAM_sel;     //0:rec_DF_RAM0 at reconstruction stage
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                                                //0:rec_DF_RAM1 at DF stage
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                                                //1:rec_DF_RAM0 at DF stage
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                                                //1:rec_DF_RAM1 at reconstruction stage
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        always @ (posedge clk)
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                if (reset_n == 1'b0)
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                        rec_DF_RAM_sel <= 1'b0;
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                else if (end_of_MB_DEC)
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                        rec_DF_RAM_sel <= ~ rec_DF_RAM_sel;
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        assign rec_DF_RAM_dout = (rec_DF_RAM_sel == 1'b0)? rec_DF_RAM1_dout:rec_DF_RAM0_dout;
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        always @ (rec_DF_RAM_sel
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                or rec_DF_RAM_wr or rec_DF_RAM_wr_addr or rec_DF_RAM_din
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                or rec_DF_RAM_rd or rec_DF_RAM_rd_addr)
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                case (rec_DF_RAM_sel)
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                        1'b0:   //rec_DF_RAM0 at reconstruction stage,rec_DF_RAM1 at DF stage
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                        begin
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                                rec_DF_RAM0_wr <= rec_DF_RAM_wr;
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                                rec_DF_RAM0_rd <= 1'b0;
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                                rec_DF_RAM0_addr <= rec_DF_RAM_wr_addr;
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                                rec_DF_RAM0_din  <= rec_DF_RAM_din;
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                                rec_DF_RAM1_wr <= 1'b0;
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                                rec_DF_RAM1_rd <= rec_DF_RAM_rd;
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                                rec_DF_RAM1_addr <= rec_DF_RAM_rd_addr;
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                                rec_DF_RAM1_din  <= 0;
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                        end
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                        1'b1:   //rec_DF_RAM0 at DF stage,rec_DF_RAM1 at reconstruction stage
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                        begin
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                                rec_DF_RAM0_wr <= 1'b0;
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                                rec_DF_RAM0_rd <= rec_DF_RAM_rd;
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                                rec_DF_RAM0_addr <= rec_DF_RAM_rd_addr;
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                                rec_DF_RAM0_din  <= 0;
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                                rec_DF_RAM1_wr <= rec_DF_RAM_wr;
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                                rec_DF_RAM1_rd <= 1'b0;
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                                rec_DF_RAM1_addr <= rec_DF_RAM_wr_addr;
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                                rec_DF_RAM1_din  <= rec_DF_RAM_din;
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                        end
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                endcase
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endmodule
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