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[/] [nova/] [trunk/] [src/] [DF_pipeline.v] - Blame information for rev 11

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1 10 eexuke
//-----------------------------------------------------------------------
2
// Design    : nova
3
// Author(s) : Ke Xu
4
// Email           : eexuke@yahoo.com
5
// File      : DF_pipeline.v
6
// Generated : Dec 2, 2005
7
// Copyright (C) 2008 Ke Xu                
8
//-------------------------------------------------------------------------------------------------
9
// Description 
10
// 5-stage pipeline control for deblocking filter
11
//-------------------------------------------------------------------------------------------------
12
 
13
// synopsys translate_off
14
`include "timescale.v"
15
// synopsys translate_on
16
`include "nova_defines.v"
17
 
18
module DF_pipeline (clk,gclk_DF,gclk_end_of_MB_DEC,reset_n,disable_DF,end_of_BS_DEC,
19
        end_of_MB_DF,end_of_lastMB_DF,
20
        bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
21
        QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
22
        DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout,
23
        buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3,
24
        buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3,
25
 
26
        DF_duration,
27
        DF_edge_counter_MR,DF_edge_counter_MW,
28
        one_edge_counter_MR,one_edge_counter_MW,
29
        bs_curr_MR,bs_curr_MW,
30
        p0_MW,p1_MW,p2_MW,p3_MW,q0_MW,q1_MW,q2_MW,q3_MW);
31
        input clk;
32
        input gclk_DF;
33
        input gclk_end_of_MB_DEC;
34
        input reset_n;
35
        input disable_DF;
36
        input end_of_BS_DEC;
37
        input end_of_MB_DF;
38
        input end_of_lastMB_DF;
39
        input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
40
        input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
41
        input [5:0] QPy,QPc;
42
        input [3:0]      slice_alpha_c0_offset_div2,slice_beta_offset_div2;
43
        input [31:0] DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout;
44
        input [31:0] buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3;
45
        input [31:0] buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3;
46
 
47
        output DF_duration;
48
        output [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
49
        output [1:0] one_edge_counter_MR,one_edge_counter_MW;
50
        output [2:0] bs_curr_MR;
51
        output [2:0] bs_curr_MW;
52
        output [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
53
        output [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
54
 
55
        reg DF_duration;
56
        always @ (posedge clk or negedge reset_n)
57
                if (reset_n == 1'b0)
58
                        DF_duration <= 1'b0;
59
                else if (end_of_BS_DEC)
60
                        DF_duration <= 1'b1;
61
                else if (end_of_MB_DF || end_of_lastMB_DF)
62
                        DF_duration <= 1'b0;
63
 
64
        //---------------------------------------------------------------------
65
        //1.MR: Memory Read
66
        //---------------------------------------------------------------------
67
        //DF_edge_counter_MR & one_edge_counter_MR
68
        reg [5:0] DF_edge_counter_MR;
69
        reg [1:0] one_edge_counter_MR;
70
        always @ (posedge gclk_DF or negedge reset_n)
71
                if (reset_n == 1'b0)
72
                        DF_edge_counter_MR <= 6'd48;
73
                else if (end_of_BS_DEC == 1'b1)
74
                        DF_edge_counter_MR <= 0;
75
                else if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd48)
76
                        DF_edge_counter_MR <= DF_edge_counter_MR + 1;
77
 
78
        always @ (posedge gclk_DF or negedge reset_n)
79
                if (reset_n == 0)
80
                        one_edge_counter_MR <= 2'd3;
81
                else if (end_of_BS_DEC == 1'b1)
82
                        one_edge_counter_MR <= 2'd0;
83
                else
84
                        begin
85
                                if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd47 && DF_edge_counter_MR[5:4] != 2'b11) //!47,!48
86
                                        one_edge_counter_MR <= 2'd0;
87
                                else if (one_edge_counter_MR != 2'd3)
88
                                        one_edge_counter_MR <= one_edge_counter_MR + 1;
89
                        end
90
 
91
        //lumaEdgeFlag_MR,chromaEdgeFlag_MR
92
        wire lumaEdgeFlag_MR,chromaEdgeFlag_MR;
93
        assign lumaEdgeFlag_MR   = !DF_edge_counter_MR[5];
94
        assign chromaEdgeFlag_MR =  DF_edge_counter_MR[5] && (DF_edge_counter_MR != 6'd48);
95
 
96
        //bs_curr_MR
97
        reg [2:0] bs_curr_MR;
98
        always @ (disable_DF or lumaEdgeFlag_MR or chromaEdgeFlag_MR or
99
                DF_edge_counter_MR[4:0] or one_edge_counter_MR[1] or
100
                bs_V0 or bs_V1 or bs_V2 or bs_V3 or bs_H0 or bs_H1 or bs_H2 or bs_H3)
101
                if (!disable_DF && lumaEdgeFlag_MR)
102
                        case (DF_edge_counter_MR[4:0])
103
                                5'd0 :bs_curr_MR <= bs_V0[2:0];
104
                                5'd1 :bs_curr_MR <= bs_V1[2:0];
105
                                5'd2 :bs_curr_MR <= bs_V0[5:3];
106
                                5'd3 :bs_curr_MR <= bs_V1[5:3];
107
                                5'd4 :bs_curr_MR <= bs_H0[2:0];
108
                                5'd5 :bs_curr_MR <= bs_H1[2:0];
109
                                5'd6 :bs_curr_MR <= bs_V2[2:0];
110
                                5'd7 :bs_curr_MR <= bs_V2[5:3];
111
                                5'd8 :bs_curr_MR <= bs_H0[5:3];
112
                                5'd9 :bs_curr_MR <= bs_H1[5:3];
113
                                5'd10:bs_curr_MR <= bs_V3[2:0];
114
                                5'd11:bs_curr_MR <= bs_V3[5:3];
115
                                5'd12:bs_curr_MR <= bs_H0[8:6];
116
                                5'd13:bs_curr_MR <= bs_H0[11:9];
117
                                5'd14:bs_curr_MR <= bs_H1[8:6];
118
                                5'd15:bs_curr_MR <= bs_H1[11:9];
119
                                5'd16:bs_curr_MR <= bs_V0[8:6];
120
                                5'd17:bs_curr_MR <= bs_V1[8:6];
121
                                5'd18:bs_curr_MR <= bs_V0[11:9];
122
                                5'd19:bs_curr_MR <= bs_V1[11:9];
123
                                5'd20:bs_curr_MR <= bs_H2[2:0];
124
                                5'd21:bs_curr_MR <= bs_H3[2:0];
125
                                5'd22:bs_curr_MR <= bs_V2[8:6];
126
                                5'd23:bs_curr_MR <= bs_V2[11:9];
127
                                5'd24:bs_curr_MR <= bs_H2[5:3];
128
                                5'd25:bs_curr_MR <= bs_H3[5:3];
129
                                5'd26:bs_curr_MR <= bs_V3[8:6];
130
                                5'd27:bs_curr_MR <= bs_V3[11:9];
131
                                5'd28:bs_curr_MR <= bs_H2[8:6];
132
                                5'd29:bs_curr_MR <= bs_H2[11:9];
133
                                5'd30:bs_curr_MR <= bs_H3[8:6];
134
                                5'd31:bs_curr_MR <= bs_H3[11:9];
135
                        endcase
136
                else if (!disable_DF && chromaEdgeFlag_MR)
137
                        case (DF_edge_counter_MR[3:0])
138
                                4'd0,4'd8:      //32,40
139
                                case (one_edge_counter_MR[1])
140
                                        1'b0:bs_curr_MR <= bs_V0[2:0];
141
                                        1'b1:bs_curr_MR <= bs_V0[5:3];
142
                                endcase
143
                                4'd2,4'd10:     //34,42
144
                                case (one_edge_counter_MR[1])
145
                                        1'b0:bs_curr_MR <= bs_V0[8:6];
146
                                        1'b1:bs_curr_MR <= bs_V0[11:9];
147
                                endcase
148
                                4'd1,4'd9:      //33,41
149
                                case (one_edge_counter_MR[1])
150
                                        1'b0:bs_curr_MR <= bs_V2[2:0];
151
                                        1'b1:bs_curr_MR <= bs_V2[5:3];
152
                                endcase
153
                                4'd3,4'd11:     //35,43
154
                                case (one_edge_counter_MR[1])
155
                                        1'b0:bs_curr_MR <= bs_V2[8:6];
156
                                        1'b1:bs_curr_MR <= bs_V2[11:9];
157
                                endcase
158
                                4'd4,4'd12:     //36,44
159
                                case (one_edge_counter_MR[1])
160
                                        1'b0:bs_curr_MR <= bs_H0[2:0];
161
                                        1'b1:bs_curr_MR <= bs_H0[5:3];
162
                                endcase
163
                                4'd5,4'd13:     //37,45
164
                                case (one_edge_counter_MR[1])
165
                                        1'b0:bs_curr_MR <= bs_H0[8:6];
166
                                        1'b1:bs_curr_MR <= bs_H0[11:9];
167
                                endcase
168
                                4'd6,4'd14:     //38,46
169
                                case (one_edge_counter_MR[1])
170
                                        1'b0:bs_curr_MR <= bs_H2[2:0];
171
                                        1'b1:bs_curr_MR <= bs_H2[5:3];
172
                                endcase
173
                                4'd7,4'd15:     //39,47
174
                                case (one_edge_counter_MR[1])
175
                                        1'b0:bs_curr_MR <= bs_H2[8:6];
176
                                        1'b1:bs_curr_MR <= bs_H2[11:9];
177
                                endcase
178
                        endcase
179
                else
180
                        bs_curr_MR <= 0;
181
 
182
        //      Pipelined parameters
183
        reg [2:0] bs_curr_TD;
184
        reg lumaEdgeFlag_TD,chromaEdgeFlag_TD;
185
        reg [5:0] DF_edge_counter_TD;
186
        reg [1:0] one_edge_counter_TD;
187
        always @ (posedge gclk_DF or negedge reset_n)
188
                if (reset_n == 1'b0)
189
                        begin
190
                                bs_curr_TD                      <= 0;
191
                                lumaEdgeFlag_TD         <= 0;
192
                                chromaEdgeFlag_TD       <= 0;
193
                                DF_edge_counter_TD      <= 6'd48;
194
                                one_edge_counter_TD <= 2'd3;
195
                        end
196
                else
197
                        begin
198
                                bs_curr_TD                      <= bs_curr_MR;
199
                                lumaEdgeFlag_TD         <= lumaEdgeFlag_MR;
200
                                chromaEdgeFlag_TD       <= chromaEdgeFlag_MR;
201
                                DF_edge_counter_TD      <= DF_edge_counter_MR;
202
                                one_edge_counter_TD     <= one_edge_counter_MR;
203
                        end
204
        //---------------------------------------------------------------------
205
        //2.TD: Threshold Decider
206
        //---------------------------------------------------------------------
207
        wire [6:0] indexA_y_unclipped,indexA_c_unclipped;
208
        wire [6:0] indexB_y_unclipped,indexB_c_unclipped;
209
        assign indexA_y_unclipped = QPy + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0};
210
        assign indexA_c_unclipped = QPc + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0};
211
        assign indexB_y_unclipped = QPy + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0};
212
        assign indexB_c_unclipped = QPc + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0};
213
 
214
        wire [5:0] indexA_y,indexA_c;
215
        wire [5:0] indexB_y,indexB_c;
216
        assign indexA_y = (indexA_y_unclipped[6] == 1)? 0:((indexA_y_unclipped[5:0] > 6'd51)? 6'd51:indexA_y_unclipped[5:0]);
217
        assign indexA_c = (indexA_c_unclipped[6] == 1)? 0:((indexA_c_unclipped[5:0] > 6'd51)? 6'd51:indexA_c_unclipped[5:0]);
218
        assign indexB_y = (indexB_y_unclipped[6] == 1)? 0:((indexB_y_unclipped[5:0] > 6'd51)? 6'd51:indexB_y_unclipped[5:0]);
219
        assign indexB_c = (indexB_c_unclipped[6] == 1)? 0:((indexB_c_unclipped[5:0] > 6'd51)? 6'd51:indexB_c_unclipped[5:0]);
220
 
221
        reg [5:0] indexA_y_reg,indexA_c_reg;
222
        reg [5:0] indexB_y_reg,indexB_c_reg;
223
        always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
224
                if (reset_n == 1'b0)
225
                        begin   indexA_y_reg <= 0;       indexA_c_reg <= 0;       indexB_y_reg <= 0;       indexB_c_reg <= 0; end
226
                else if (!disable_DF)
227
                        begin
228
                                indexA_y_reg <= indexA_y;       indexA_c_reg <= indexA_c;
229
                                indexB_y_reg <= indexB_y;       indexB_c_reg <= indexB_c;
230
                        end
231
 
232
        wire [5:0] indexA,indexB;
233
        assign indexA = (lumaEdgeFlag_TD)? indexA_y_reg:((chromaEdgeFlag_TD)? indexA_c_reg:0);
234
        assign indexB = (lumaEdgeFlag_TD)? indexB_y_reg:((chromaEdgeFlag_TD)? indexB_c_reg:0);
235
 
236
        reg [7:0] alpha,beta;
237
        //alpha
238
        always @ (indexA)
239
                if (indexA < 16)
240
                        alpha <= 0;
241
                else
242
                        case (indexA)
243
                                6'd16,6'd17:alpha <= 8'd4;
244
                                6'd18:alpha <= 8'd5;    6'd19:alpha <= 8'd6;    6'd20:alpha <= 8'd7;    6'd21:alpha <= 8'd8;
245
                                6'd22:alpha <= 8'd9;    6'd23:alpha <= 8'd10;   6'd24:alpha <= 8'd12;   6'd25:alpha <= 8'd13;
246
                                6'd26:alpha <= 8'd15;   6'd27:alpha <= 8'd17;   6'd28:alpha <= 8'd20;   6'd29:alpha <= 8'd22;
247
                                6'd30:alpha <= 8'd25;   6'd31:alpha <= 8'd28;   6'd32:alpha <= 8'd32;   6'd33:alpha <= 8'd36;
248
                                6'd34:alpha <= 8'd40;   6'd35:alpha <= 8'd45;   6'd36:alpha <= 8'd50;   6'd37:alpha <= 8'd56;
249
                                6'd38:alpha <= 8'd63;   6'd39:alpha <= 8'd71;   6'd40:alpha <= 8'd80;   6'd41:alpha <= 8'd90;
250
                                6'd42:alpha <= 8'd101;  6'd43:alpha <= 8'd113;  6'd44:alpha <= 8'd127;  6'd45:alpha <= 8'd144;
251
                                6'd46:alpha <= 8'd162;  6'd47:alpha <= 8'd182;  6'd48:alpha <= 8'd203;  6'd49:alpha <= 8'd226;
252
                                default:alpha <= 8'd255;
253
                        endcase
254
        //beta
255
        always @ (indexB)
256
                if (indexB < 16)
257
                        beta <= 0;
258
                else if (indexB > 15 && indexB < 26)
259
                        case (indexB)
260
                                6'd16,6'd17,6'd18               :beta <= 8'd2;
261
                                6'd19,6'd20,6'd21,6'd22 :beta <= 8'd3;
262
                                6'd23,6'd24,6'd25               :beta <= 8'd4;
263
                                default:beta <= 0;
264
                        endcase
265
                else
266
                        beta <= indexB[5:1] - 3'd7;
267
 
268
        wire [7:0] absolute_TD0_a,absolute_TD0_b;
269
        wire [7:0] absolute_TD1_a,absolute_TD1_b;
270
        wire [7:0] absolute_TD2_a,absolute_TD2_b;
271
        wire [7:0] absolute_TD0_out,absolute_TD1_out,absolute_TD2_out;
272
        absolute absolute_TD0 (.a(absolute_TD0_a),.b(absolute_TD0_b),.out(absolute_TD0_out));
273
        absolute absolute_TD1 (.a(absolute_TD1_a),.b(absolute_TD1_b),.out(absolute_TD1_out));
274
        absolute absolute_TD2 (.a(absolute_TD2_a),.b(absolute_TD2_b),.out(absolute_TD2_out));
275
 
276
        //p0 ~ p3
277
        wire Is_p_from_mbAddrA;
278
        wire Is_p_from_mbAddrB;
279
        wire Is_p_from_buf0;
280
        wire Is_p_from_buf1;
281
        wire Is_p_from_buf2;
282
        wire Is_p_from_buf3;
283
        assign Is_p_from_mbAddrA =    (DF_edge_counter_TD == 6'd0  || DF_edge_counter_TD == 6'd2  ||
284
        DF_edge_counter_TD == 6'd16 || DF_edge_counter_TD == 6'd18 || DF_edge_counter_TD == 6'd32 ||
285
        DF_edge_counter_TD == 6'd34 || DF_edge_counter_TD == 6'd40 || DF_edge_counter_TD == 6'd42);
286
 
287
        assign Is_p_from_mbAddrB =    (DF_edge_counter_TD == 6'd4  || DF_edge_counter_TD == 6'd8  ||
288
        DF_edge_counter_TD == 6'd12 || DF_edge_counter_TD == 6'd13 || DF_edge_counter_TD == 6'd20 ||
289
        DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd29 ||
290
        DF_edge_counter_TD == 6'd36 || DF_edge_counter_TD == 6'd37 || DF_edge_counter_TD == 6'd44 ||
291
        DF_edge_counter_TD == 6'd45);
292
 
293
        assign Is_p_from_buf0 =       (DF_edge_counter_TD == 6'd1  || DF_edge_counter_TD == 6'd5  ||
294
        DF_edge_counter_TD == 6'd10 || DF_edge_counter_TD == 6'd14 || DF_edge_counter_TD == 6'd17 ||
295
        DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd26 || DF_edge_counter_TD == 6'd30 ||
296
        DF_edge_counter_TD == 6'd33 || DF_edge_counter_TD == 6'd38 || DF_edge_counter_TD == 6'd41 ||
297
        DF_edge_counter_TD == 6'd46);
298
 
299
        assign Is_p_from_buf1 =       (DF_edge_counter_TD == 6'd6  || DF_edge_counter_TD == 6'd9  ||
300
        DF_edge_counter_TD == 6'd15 || DF_edge_counter_TD == 6'd22 || DF_edge_counter_TD == 6'd25 ||
301
        DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || DF_edge_counter_TD == 6'd47);
302
 
303
        assign Is_p_from_buf2 =       (DF_edge_counter_TD == 6'd3  || DF_edge_counter_TD == 6'd11 ||
304
        DF_edge_counter_TD == 6'd19 || DF_edge_counter_TD == 6'd27 || DF_edge_counter_TD == 6'd35 ||
305
        DF_edge_counter_TD == 6'd43);
306
 
307
        assign Is_p_from_buf3 =       (DF_edge_counter_TD == 6'd7  || DF_edge_counter_TD == 6'd23);
308
 
309
        reg [7:0] p0,p1,p2,p3;
310
        always @ (Is_p_from_mbAddrA or Is_p_from_mbAddrB or Is_p_from_buf0 or Is_p_from_buf1 or
311
                Is_p_from_buf2 or Is_p_from_buf3 or one_edge_counter_TD or
312
                DF_mbAddrA_RF_dout or DF_mbAddrB_RAM_dout or
313
                buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or
314
                buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3)
315
                case ({Is_p_from_mbAddrA,Is_p_from_mbAddrB,Is_p_from_buf0,Is_p_from_buf1,Is_p_from_buf2,Is_p_from_buf3})
316
                        6'b100000:{p0,p1,p2,p3} <= DF_mbAddrA_RF_dout;
317
                        6'b010000:{p0,p1,p2,p3} <= DF_mbAddrB_RAM_dout;
318
                        6'b001000:      case (one_edge_counter_TD)
319
                                                        2'b00:{p0,p1,p2,p3} <= buf0_0;
320
                                                        2'b01:{p0,p1,p2,p3} <= buf0_1;
321
                                                        2'b10:{p0,p1,p2,p3} <= buf0_2;
322
                                                        2'b11:{p0,p1,p2,p3} <= buf0_3;
323
                                                endcase
324
                        6'b000100:      case (one_edge_counter_TD)
325
                                                        2'b00:{p0,p1,p2,p3} <= buf1_0;
326
                                                        2'b01:{p0,p1,p2,p3} <= buf1_1;
327
                                                        2'b10:{p0,p1,p2,p3} <= buf1_2;
328
                                                        2'b11:{p0,p1,p2,p3} <= buf1_3;
329
                                                endcase
330
                        6'b000010:      case (one_edge_counter_TD)
331
                                                        2'b00:{p0,p1,p2,p3} <= buf2_0;
332
                                                        2'b01:{p0,p1,p2,p3} <= buf2_1;
333
                                                        2'b10:{p0,p1,p2,p3} <= buf2_2;
334
                                                        2'b11:{p0,p1,p2,p3} <= buf2_3;
335
                                                endcase
336
                        6'b000001:      case (one_edge_counter_TD)
337
                                                        2'b00:{p0,p1,p2,p3} <= buf3_0;
338
                                                        2'b01:{p0,p1,p2,p3} <= buf3_1;
339
                                                        2'b10:{p0,p1,p2,p3} <= buf3_2;
340
                                                        2'b11:{p0,p1,p2,p3} <= buf3_3;
341
                                                endcase
342
                        default:{p0,p1,p2,p3} <= 0;
343
                endcase
344
 
345
        //q0 ~ q3
346
        wire Is_q_from_buf0;
347
        wire Is_q_from_buf1;
348
        wire Is_q_from_buf2;
349
        wire Is_q_from_buf3;
350
 
351
        assign Is_q_from_buf0 = (DF_edge_counter_TD == 6'd4  || DF_edge_counter_TD == 6'd12  ||
352
        DF_edge_counter_TD == 6'd20 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd36 ||
353
        DF_edge_counter_TD == 6'd44);
354
 
355
        assign Is_q_from_buf1 = (DF_edge_counter_TD == 6'd8  || DF_edge_counter_TD == 6'd13  ||
356
        DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd29 || DF_edge_counter_TD == 6'd37 ||
357
        DF_edge_counter_TD == 6'd45);
358
 
359
        assign Is_q_from_buf2 = (DF_edge_counter_TD == 6'd5  || DF_edge_counter_TD == 6'd14  ||
360
        DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd30 || DF_edge_counter_TD == 6'd38 ||
361
        DF_edge_counter_TD == 6'd46);
362
 
363
        assign Is_q_from_buf3 = (DF_edge_counter_TD == 6'd9  || DF_edge_counter_TD == 6'd15  ||
364
        DF_edge_counter_TD == 6'd25 || DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 ||
365
        DF_edge_counter_TD == 6'd47);
366
 
367
        reg [7:0] q0,q1,q2,q3;
368
        always @ (Is_q_from_buf0 or Is_q_from_buf1 or Is_q_from_buf2 or Is_q_from_buf3 or
369
                rec_DF_RAM_dout or one_edge_counter_TD or DF_edge_counter_TD or
370
                buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or
371
                buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3)
372
                case ({Is_q_from_buf0,Is_q_from_buf1,Is_q_from_buf2,Is_q_from_buf3})
373
                        4'b1000:case (one_edge_counter_TD)
374
                                                2'b00:{q3,q2,q1,q0} <= buf0_0;
375
                                                2'b01:{q3,q2,q1,q0} <= buf0_1;
376
                                                2'b10:{q3,q2,q1,q0} <= buf0_2;
377
                                                2'b11:{q3,q2,q1,q0} <= buf0_3;
378
                                        endcase
379
                        4'b0100:case (one_edge_counter_TD)
380
                                                2'b00:{q3,q2,q1,q0} <= buf1_0;
381
                                                2'b01:{q3,q2,q1,q0} <= buf1_1;
382
                                                2'b10:{q3,q2,q1,q0} <= buf1_2;
383
                                                2'b11:{q3,q2,q1,q0} <= buf1_3;
384
                                        endcase
385
                        4'b0010:case (one_edge_counter_TD)
386
                                                2'b00:{q3,q2,q1,q0} <= buf2_0;
387
                                                2'b01:{q3,q2,q1,q0} <= buf2_1;
388
                                                2'b10:{q3,q2,q1,q0} <= buf2_2;
389
                                                2'b11:{q3,q2,q1,q0} <= buf2_3;
390
                                        endcase
391
                        4'b0001:case (one_edge_counter_TD)
392
                                                2'b00:{q3,q2,q1,q0} <= buf3_0;
393
                                                2'b01:{q3,q2,q1,q0} <= buf3_1;
394
                                                2'b10:{q3,q2,q1,q0} <= buf3_2;
395
                                                2'b11:{q3,q2,q1,q0} <= buf3_3;
396
                                        endcase
397
                        default:if (DF_edge_counter_TD != 6'd48)        {q3,q2,q1,q0} <= rec_DF_RAM_dout;
398
                                        else                                                            {q3,q2,q1,q0} <= 0;
399
                endcase
400
 
401
        // |p0 - q0| < alpha
402
        assign absolute_TD0_a = (!disable_DF && bs_curr_TD != 0)? p0:0;
403
        assign absolute_TD0_b = (!disable_DF && bs_curr_TD != 0)? q0:0;
404
 
405
        // |p1 - p0| < beta
406
        assign absolute_TD1_a = (!disable_DF && bs_curr_TD != 0)? p0:0;
407
        assign absolute_TD1_b = (!disable_DF && bs_curr_TD != 0)? p1:0;
408
 
409
        // |q1 - q0| < beta
410
        assign absolute_TD2_a = (!disable_DF && bs_curr_TD != 0)? q0:0;
411
        assign absolute_TD2_b = (!disable_DF && bs_curr_TD != 0)? q1:0;
412
 
413
        // Threshold
414
        wire threshold;
415
        assign threshold = ((absolute_TD0_out < alpha) && (absolute_TD1_out < beta) &&
416
                                                (absolute_TD2_out < beta))? 1'b1:1'b0;
417
 
418
        //      Pipelined parameters
419
        reg [2:0] bs_curr_PRE;
420
        reg [5:0] DF_edge_counter_PRE;
421
        reg [1:0] one_edge_counter_PRE;
422
        reg lumaEdgeFlag_PRE,chromaEdgeFlag_PRE;
423
        reg [7:0] p0_PRE,p1_PRE,p2_PRE,p3_PRE;
424
        reg [7:0] q0_PRE,q1_PRE,q2_PRE,q3_PRE;
425
        reg [5:0] indexA_PRE;
426
        reg [7:0] alpha_PRE,beta_PRE;
427
        always @ (posedge gclk_DF or negedge reset_n)
428
                if (reset_n == 1'b0)
429
                        begin
430
                                bs_curr_PRE              <= 0;
431
                                DF_edge_counter_PRE  <= 6'd48;
432
                                one_edge_counter_PRE <= 2'd3;
433
                                lumaEdgeFlag_PRE         <= 0;
434
                                chromaEdgeFlag_PRE       <= 0;
435
                                indexA_PRE <= 0;
436
                                alpha_PRE  <= 0;
437
                                beta_PRE   <= 0;
438
                                p0_PRE <= 0;     p1_PRE <= 0;     p2_PRE <= 0;     p3_PRE <= 0;
439
                                q0_PRE <= 0;     q1_PRE <= 0;     q2_PRE <= 0;     q3_PRE <= 0;
440
                        end
441
                else
442
                        begin
443
                                bs_curr_PRE             <= (threshold)? bs_curr_TD:0;
444
                                DF_edge_counter_PRE     <= DF_edge_counter_TD;
445
                                one_edge_counter_PRE<= one_edge_counter_TD;
446
                                lumaEdgeFlag_PRE        <= (threshold)? lumaEdgeFlag_TD:0;
447
                                chromaEdgeFlag_PRE      <= (threshold)? chromaEdgeFlag_TD:0;
448
                                indexA_PRE <= (threshold)? indexA:0;
449
                                alpha_PRE  <= (threshold)? alpha:0;
450
                                beta_PRE   <= (threshold)? beta:0;
451
                                p0_PRE <= p0;   p1_PRE <= p1;   p2_PRE <= p2;   p3_PRE <= p3;
452
                                q0_PRE <= q0;   q1_PRE <= q1;   q2_PRE <= q2;   q3_PRE <= q3;
453
                        end
454
        //---------------------------------------------------------------------
455
        //3.PRE: Precomputation
456
        //---------------------------------------------------------------------
457
        wire [7:0] absolute_PRE0_a,absolute_PRE0_b;
458
        wire [7:0] absolute_PRE1_a,absolute_PRE1_b;
459
        wire [7:0] absolute_PRE2_a,absolute_PRE2_b;
460
        wire [7:0] absolute_PRE0_out,absolute_PRE1_out,absolute_PRE2_out;
461
 
462
        absolute absolute_PRE0 (.a(absolute_PRE0_a),.b(absolute_PRE0_b),.out(absolute_PRE0_out));
463
        absolute absolute_PRE1 (.a(absolute_PRE1_a),.b(absolute_PRE1_b),.out(absolute_PRE1_out));
464
        absolute absolute_PRE2 (.a(absolute_PRE2_a),.b(absolute_PRE2_b),.out(absolute_PRE2_out));
465
 
466
        // |p2 - p0| < beta
467
        assign absolute_PRE0_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p2_PRE:0;
468
        assign absolute_PRE0_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p0_PRE:0;
469
 
470
        // |q2 - q0| < beta
471
        assign absolute_PRE1_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q2_PRE:0;
472
        assign absolute_PRE1_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q0_PRE:0;
473
 
474
        // |p0 - q0| < alpha >> 2 + 2
475
        assign absolute_PRE2_a = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? p0_PRE:0;
476
        assign absolute_PRE2_b = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? q0_PRE:0;
477
 
478
        wire p2_m_p0_less_beta,q2_m_q0_less_beta,p0_m_q0_less_alpha_shift;
479
        assign p2_m_p0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0:
480
                                                                ((absolute_PRE0_out < beta_PRE)? 1'b1:1'b0);
481
        assign q2_m_q0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0:
482
                                                                ((absolute_PRE1_out < beta_PRE)? 1'b1:1'b0);
483
        assign p0_m_q0_less_alpha_shift = (!lumaEdgeFlag_PRE || bs_curr_PRE != 4)? 1'b0:
484
                                                                ((absolute_PRE2_out < ((alpha_PRE >> 2) + 2))? 1'b1:1'b0);
485
        // bs = 1 ~ 3
486
        reg [4:0] c1;
487
        always @ (bs_curr_PRE or indexA_PRE)
488
                if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
489
                        case (bs_curr_PRE)
490
                                3'd1:
491
                                if              (indexA_PRE < 23)       c1 <= 5'd0;
492
                                else if (indexA_PRE < 33)       c1 <= 5'd1;
493
                                else if (indexA_PRE < 37)       c1 <= 5'd2;
494
                                else if (indexA_PRE < 40)       c1 <= 5'd3;
495
                                else if (indexA_PRE < 43)       c1 <= 5'd4;
496
                                else
497
                                        case (indexA_PRE)
498
                                                6'd43:c1 <= 5'd5;       6'd44,6'd45:c1 <= 5'd6;
499
                                                6'd46:c1 <= 5'd7;       6'd47:c1 <= 5'd8;       6'd48:c1 <= 5'd9;
500
                                                6'd49:c1 <= 5'd10;      6'd50:c1 <= 5'd11;      6'd51:c1 <= 5'd13;
501
                                                default:c1 <= 0;
502
                                        endcase
503
                                3'd2:
504
                                if              (indexA_PRE < 21)       c1 <= 5'd0;
505
                                else if (indexA_PRE < 31)       c1 <= 5'd1;
506
                                else if (indexA_PRE < 35)       c1 <= 5'd2;
507
                                else if (indexA_PRE < 38)       c1 <= 5'd3;
508
                                else
509
                                        case (indexA_PRE)
510
                                                6'd38,6'd39:c1 <= 5'd4;
511
                                                6'd40,6'd41:c1 <= 5'd5;
512
                                                6'd42:c1 <= 5'd6;       6'd43:c1 <= 5'd7;       6'd44,6'd45:c1 <= 5'd8;
513
                                                6'd46:c1 <= 5'd10;      6'd47:c1 <= 5'd11;      6'd48:c1 <= 5'd12;
514
                                                6'd49:c1 <= 5'd13;      6'd50:c1 <= 5'd15;      6'd51:c1 <= 5'd17;
515
                                                default:c1 <= 5'd0;
516
                                        endcase
517
                                3'd3:
518
                                if              (indexA_PRE < 17)       c1 <= 5'd0;
519
                                else if (indexA_PRE < 27)       c1 <= 5'd1;
520
                                else if (indexA_PRE < 31)       c1 <= 5'd2;
521
                                else if (indexA_PRE < 34)       c1 <= 5'd3;
522
                                else if (indexA_PRE < 37)       c1 <= 5'd4;
523
                                else
524
                                        case (indexA_PRE)
525
                                                6'd37:c1 <= 5'd5;       6'd38,6'd39:c1 <= 5'd6;
526
                                                6'd40:c1 <= 5'd7;       6'd41:c1 <= 5'd8;       6'd42:c1 <= 5'd9;       6'd43:c1 <= 5'd10;
527
                                                6'd44:c1 <= 5'd11;      6'd45:c1 <= 5'd13;      6'd46:c1 <= 5'd14;      6'd47:c1 <= 5'd16;
528
                                                6'd48:c1 <= 5'd18;      6'd49:c1 <= 5'd20;      6'd50:c1 <= 5'd23;      6'd51:c1 <= 5'd25;
529
                                                default:c1 <= 5'd0;
530
                                        endcase
531
                                default:c1 <= 0;
532
                        endcase
533
                else
534
                        c1 <= 0;
535
 
536
        reg [4:0] c0;
537
        always @ (bs_curr_PRE or lumaEdgeFlag_PRE or c1 or p2_m_p0_less_beta or q2_m_q0_less_beta)
538
                if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
539
                        begin
540
                                if (lumaEdgeFlag_PRE)   //filter luma edge
541
                                        c0 <= (  p2_m_p0_less_beta &&  q2_m_q0_less_beta)? (c1 + 2):
542
                                                  ((!p2_m_p0_less_beta && !q2_m_q0_less_beta)? c1:(c1+1));
543
                                else                                    //filter chroma edge
544
                                        c0 <= c1 + 1;
545
                        end
546
                else
547
                        c0 <= 0;
548
 
549
        //delta_0i = [(q0 - p0) << 2 + (p1 - q1) + 4] >> 3 : P151 (8-334) of H.264/AVC standard 2003
550
        wire [8:0] delta_0i;
551
        wire need_delta_0i;
552
        wire [8:0]  q0_m_p0;             //p0 - q0
553
        wire [11:0] delta_0i_tmp;        //[(p0 - q0) << 2 + (p1 - q1) + 4]      
554
        assign need_delta_0i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4);
555
        assign q0_m_p0 =          (need_delta_0i)? ({1'b0,q0_PRE} + {1'b1,~p0_PRE} + 1):0;
556
        assign delta_0i_tmp = (need_delta_0i)? ({q0_m_p0[8],q0_m_p0,2'b0} + p1_PRE + {4'b1111,~q1_PRE} + 5):0;
557
        assign delta_0i = delta_0i_tmp[11:3];
558
 
559
 
560
        //delta p1i = [(p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)] >> 1     : P152 (8-341) of H.264/AVC standard 2003
561
        //delta q1i = [(q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)] >> 1     : P152 (8-343) of H.264/AVC standard 2003
562
        wire [8:0] delta_p1i,delta_q1i;
563
        wire need_p1i;
564
        wire need_q1i;
565
        wire [8:0] p0_q0_sum; //p0+q0+1
566
        wire [9:0] neg_p1_shift; //-(p1 << 1)
567
        wire [9:0] neg_q1_shift; //-(q1 << 1)
568
        wire [9:0] delta_p1i_tmp;// (p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)
569
        wire [9:0] delta_q1i_tmp;// (q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)
570
        assign need_p1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta);
571
        assign need_q1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta);
572
        assign p0_q0_sum = (need_p1i || need_q1i)? ({1'b0,p0_PRE} + {1'b0,q0_PRE} + 1):0;
573
        assign neg_p1_shift =  (need_p1i)? ({1'b1,~p1_PRE,1'b1} + 1):0;
574
        assign neg_q1_shift =  (need_q1i)? ({1'b1,~q1_PRE,1'b1} + 1):0;
575
        assign delta_p1i_tmp = (need_p1i)? (p2_PRE + p0_q0_sum[8:1] + neg_p1_shift):0;
576
        assign delta_q1i_tmp = (need_q1i)? (q2_PRE + p0_q0_sum[8:1] + neg_q1_shift):0;
577
        assign delta_p1i = delta_p1i_tmp[9:1];
578
        assign delta_q1i = delta_q1i_tmp[9:1];
579
 
580
        wire [8:0] clip_to_c_0_delta,clip_to_c_p1_delta,clip_to_c_q1_delta;
581
        wire [4:0] clip_to_c_0_c,clip_to_c_p1_c,clip_to_c_q1_c;
582
        wire [5:0] clip_to_c_0_out,clip_to_c_p1_out,clip_to_c_q1_out;
583
        clip_to_c clip_to_c_0 (.delta(clip_to_c_0_delta),.c(clip_to_c_0_c),.out(clip_to_c_0_out));
584
        clip_to_c clip_to_c_p1 (.delta(clip_to_c_p1_delta),.c(clip_to_c_p1_c),.out(clip_to_c_p1_out));
585
        clip_to_c clip_to_c_q1 (.delta(clip_to_c_q1_delta),.c(clip_to_c_q1_c),.out(clip_to_c_q1_out));
586
 
587
        assign clip_to_c_0_delta  = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? delta_0i:0;
588
        assign clip_to_c_0_c      = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? c0:0;
589
        assign clip_to_c_p1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? delta_p1i:0;
590
        assign clip_to_c_p1_c     = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? c1:0;
591
        assign clip_to_c_q1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? delta_q1i:0;
592
        assign clip_to_c_q1_c     = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? c1:0;
593
 
594
        //      Pipelined parameters
595
        reg [5:0] delta_0,delta_p1,delta_q1;
596
        always @ (posedge gclk_DF or negedge reset_n)
597
                if (reset_n == 1'b0)
598
                        begin delta_0 <= 0;      delta_p1 <= 0;   delta_q1 <= 0;   end
599
                else if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
600
                        begin
601
                                delta_0  <= clip_to_c_0_out;
602
                                delta_p1 <= (p2_m_p0_less_beta)? clip_to_c_p1_out:0;
603
                                delta_q1 <= (q2_m_q0_less_beta)? clip_to_c_q1_out:0;
604
                        end
605
 
606
        reg p2_m_p0_less_beta_FIR,q2_m_q0_less_beta_FIR,p0_m_q0_less_alpha_shift_FIR;
607
        reg lumaEdgeFlag_FIR,chromaEdgeFlag_FIR;
608
        reg [2:0] bs_curr_FIR;
609
        reg [5:0] DF_edge_counter_FIR;
610
        reg [1:0] one_edge_counter_FIR;
611
        reg [7:0] p0_FIR,p1_FIR,p2_FIR,p3_FIR;
612
        reg [7:0] q0_FIR,q1_FIR,q2_FIR,q3_FIR;
613
        always @ (posedge gclk_DF or negedge reset_n)
614
                if (reset_n == 1'b0)
615
                        begin
616
                                p2_m_p0_less_beta_FIR <= 0;      q2_m_q0_less_beta_FIR <= 0;
617
                                p0_m_q0_less_alpha_shift_FIR <= 0;
618
                                bs_curr_FIR             <= 0;
619
                                lumaEdgeFlag_FIR <= 0;                   chromaEdgeFlag_FIR <= 0;
620
                                DF_edge_counter_FIR <= 6'd48;   one_edge_counter_FIR <= 2'd3;
621
                                p0_FIR <= 0;     p1_FIR <= 0;     p2_FIR <= 0;     p3_FIR <= 0;
622
                                q0_FIR <= 0;     q1_FIR <= 0;     q2_FIR <= 0;     q3_FIR <= 0;
623
                        end
624
                else
625
                        begin
626
                                p2_m_p0_less_beta_FIR <= p2_m_p0_less_beta;
627
                                q2_m_q0_less_beta_FIR <= q2_m_q0_less_beta;
628
                                p0_m_q0_less_alpha_shift_FIR <= p0_m_q0_less_alpha_shift;
629
                                bs_curr_FIR     <= bs_curr_PRE;
630
                                lumaEdgeFlag_FIR <= lumaEdgeFlag_PRE;           chromaEdgeFlag_FIR <= chromaEdgeFlag_PRE;
631
                                DF_edge_counter_FIR <= DF_edge_counter_PRE; one_edge_counter_FIR <= one_edge_counter_PRE;
632
                                p0_FIR <= p0_PRE;       p1_FIR <= p1_PRE;       p2_FIR <= p2_PRE;       p3_FIR <= p3_PRE;
633
                                q0_FIR <= q0_PRE;       q1_FIR <= q1_PRE;       q2_FIR <= q2_PRE;       q3_FIR <= q3_PRE;
634
                        end
635
        //---------------------------------------------------------------------
636
        //4.FIR: filtering
637
        //---------------------------------------------------------------------
638
        reg [7:0] bs4_strong_FIR_p0,bs4_strong_FIR_p1,bs4_strong_FIR_p2,bs4_strong_FIR_p3;
639
        reg [7:0] bs4_strong_FIR_q0,bs4_strong_FIR_q1,bs4_strong_FIR_q2,bs4_strong_FIR_q3;
640
        wire [7:0] bs4_strong_FIR_p0_out,bs4_strong_FIR_p1_out,bs4_strong_FIR_p2_out;
641
        wire [7:0] bs4_strong_FIR_q0_out,bs4_strong_FIR_q1_out,bs4_strong_FIR_q2_out;
642
        bs4_strong_FIR bs4_strong_FIR (
643
                .p0(bs4_strong_FIR_p0),.p1(bs4_strong_FIR_p1),.p2(bs4_strong_FIR_p2),.p3(bs4_strong_FIR_p3),
644
                .q0(bs4_strong_FIR_q0),.q1(bs4_strong_FIR_q1),.q2(bs4_strong_FIR_q2),.q3(bs4_strong_FIR_q3),
645
                .p0_out(bs4_strong_FIR_p0_out),.p1_out(bs4_strong_FIR_p1_out),.p2_out(bs4_strong_FIR_p2_out),
646
                .q0_out(bs4_strong_FIR_q0_out),.q1_out(bs4_strong_FIR_q1_out),.q2_out(bs4_strong_FIR_q2_out)
647
                );
648
        reg [7:0] bs4_weak_FIR0_a,bs4_weak_FIR0_b,bs4_weak_FIR0_c;
649
        reg [7:0] bs4_weak_FIR1_a,bs4_weak_FIR1_b,bs4_weak_FIR1_c;
650
        wire [7:0] bs4_weak_FIR0_out,bs4_weak_FIR1_out;
651
        bs4_weak_FIR bs4_weak_FIR0 (.a(bs4_weak_FIR0_a),.b(bs4_weak_FIR0_b),.c(bs4_weak_FIR0_c),.out(bs4_weak_FIR0_out));
652
        bs4_weak_FIR bs4_weak_FIR1 (.a(bs4_weak_FIR1_a),.b(bs4_weak_FIR1_b),.c(bs4_weak_FIR1_c),.out(bs4_weak_FIR1_out));
653
        // bs = 4
654
        always @ (bs_curr_FIR or lumaEdgeFlag_FIR or p0_m_q0_less_alpha_shift_FIR
655
                or p2_m_p0_less_beta_FIR or q2_m_q0_less_beta_FIR
656
                or p0_FIR or p1_FIR or p2_FIR or p3_FIR or q0_FIR or q1_FIR or q2_FIR or q3_FIR)
657
                if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1 && p0_m_q0_less_alpha_shift_FIR
658
                        && (p2_m_p0_less_beta_FIR || q2_m_q0_less_beta_FIR))
659
                        begin
660
                                bs4_strong_FIR_p0 <= p0_FIR;    bs4_strong_FIR_p1 <= p1_FIR;
661
                                bs4_strong_FIR_p2 <= p2_FIR;    bs4_strong_FIR_p3 <= p3_FIR;
662
                                bs4_strong_FIR_q0 <= q0_FIR;    bs4_strong_FIR_q1 <= q1_FIR;
663
                                bs4_strong_FIR_q2 <= q2_FIR;    bs4_strong_FIR_q3 <= q3_FIR;
664
                        end
665
                else
666
                        begin
667
                                bs4_strong_FIR_p0 <= 0;  bs4_strong_FIR_p1 <= 0;  bs4_strong_FIR_p2 <= 0; bs4_strong_FIR_p3 <= 0;
668
                                bs4_strong_FIR_q0 <= 0;  bs4_strong_FIR_q1 <= 0;  bs4_strong_FIR_q2 <= 0;  bs4_strong_FIR_q3 <= 0;
669
                        end
670
        always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR
671
                or p2_m_p0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR
672
                or p1_FIR or p0_FIR or q1_FIR)
673
                if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1)
674
                        begin
675
                                if (!p2_m_p0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR)
676
                                        begin
677
                                                bs4_weak_FIR0_a <= p1_FIR;      bs4_weak_FIR0_b <= p0_FIR;      bs4_weak_FIR0_c <= q1_FIR;
678
                                        end
679
                                else
680
                                        begin
681
                                                bs4_weak_FIR0_a <= 0;    bs4_weak_FIR0_b <= 0;    bs4_weak_FIR0_c <= 0;
682
                                        end
683
                        end
684
                else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1)
685
                        begin
686
                                bs4_weak_FIR0_a <= p1_FIR;      bs4_weak_FIR0_b <= p0_FIR;      bs4_weak_FIR0_c <= q1_FIR;
687
                        end
688
                else
689
                        begin
690
                                bs4_weak_FIR0_a <= 0;    bs4_weak_FIR0_b <= 0;    bs4_weak_FIR0_c <= 0;
691
                        end
692
        always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR
693
                or q2_m_q0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR
694
                or q1_FIR or q0_FIR or p1_FIR)
695
                if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1)
696
                        begin
697
                                if (!q2_m_q0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR)
698
                                        begin
699
                                                bs4_weak_FIR1_a <= q1_FIR;      bs4_weak_FIR1_b <= q0_FIR;      bs4_weak_FIR1_c <= p1_FIR;
700
                                        end
701
                                else
702
                                        begin
703
                                                bs4_weak_FIR1_a <= 0;    bs4_weak_FIR1_b <= 0;    bs4_weak_FIR1_c <= 0;
704
                                        end
705
                        end
706
                else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1)
707
                        begin
708
                                bs4_weak_FIR1_a <= q1_FIR;      bs4_weak_FIR1_b <= q0_FIR;      bs4_weak_FIR1_c <= p1_FIR;
709
                        end
710
                else
711
                        begin
712
                                bs4_weak_FIR1_a <= 0;    bs4_weak_FIR1_b <= 0;    bs4_weak_FIR1_c <= 0;
713
                        end
714
        //bs = 1 ~ 3,for p0 and q0 filtering
715
        wire [9:0] p0_MW_tmp,q0_MW_tmp;
716
        wire [7:0] p0_MW_clipped,q0_MW_clipped;
717
        assign p0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,p0_FIR} + {{4{delta_0[5]}},delta_0}):0;
718
        assign q0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,q0_FIR} +
719
                                                {~delta_0[5],~delta_0[5],~delta_0[5],~delta_0[5],~delta_0} + 1):0;
720
        assign p0_MW_clipped = (p0_MW_tmp[9] == 1'b1)? 0:((p0_MW_tmp[8] == 1'b1)? 8'd255:p0_MW_tmp[7:0]);
721
        assign q0_MW_clipped = (q0_MW_tmp[9] == 1'b1)? 0:((q0_MW_tmp[8] == 1'b1)? 8'd255:q0_MW_tmp[7:0]);
722
 
723
        //      Pipelined parameters
724
        reg [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
725
        reg [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
726
        always @ (posedge gclk_DF or negedge reset_n)
727
                if (reset_n == 1'b0)
728
                        begin
729
                                p0_MW <= 0;      p1_MW <= 0;      p2_MW <= 0;
730
                                q0_MW <= 0;      q1_MW <= 0;      q2_MW <= 0;
731
                        end
732
                else if (bs_curr_FIR == 3'd4)
733
                        begin
734
                                if (lumaEdgeFlag_FIR)
735
                                        begin
736
                                                p0_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)?
737
                                                                        bs4_strong_FIR_p0_out:bs4_weak_FIR0_out;
738
                                                q0_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)?
739
                                                                        bs4_strong_FIR_q0_out:bs4_weak_FIR1_out;
740
                                                p1_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)?
741
                                                                        bs4_strong_FIR_p1_out:p1_FIR;
742
                                                q1_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)?
743
                                                                        bs4_strong_FIR_q1_out:q1_FIR;
744
                                                p2_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)?
745
                                                                        bs4_strong_FIR_p2_out:p2_FIR;
746
                                                q2_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)?
747
                                                                        bs4_strong_FIR_q2_out:q2_FIR;
748
                                        end
749
                                else
750
                                        begin
751
                                                p0_MW <= bs4_weak_FIR0_out;     q0_MW <= bs4_weak_FIR1_out;
752
                                                p1_MW <= p1_FIR;                q1_MW <= q1_FIR;
753
                                                p2_MW <= p2_FIR;                q2_MW <= q2_FIR;
754
                                        end
755
                        end
756
                else if (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)
757
                        begin
758
                                p0_MW <= p0_MW_clipped;
759
                                q0_MW <= q0_MW_clipped;
760
                                p1_MW <= (lumaEdgeFlag_FIR)? ((p2_m_p0_less_beta_FIR)? (p1_FIR + {delta_p1[5],delta_p1[5],delta_p1}):p1_FIR):p1_FIR;
761
                                q1_MW <= (lumaEdgeFlag_FIR)? ((q2_m_q0_less_beta_FIR)? (q1_FIR + {delta_q1[5],delta_q1[5],delta_q1}):q1_FIR):q1_FIR;
762
                                p2_MW <= p2_FIR;
763
                                q2_MW <= q2_FIR;
764
                        end
765
                else
766
                        begin
767
                                p0_MW <= p0_FIR;        p1_MW <= p1_FIR;        p2_MW <= p2_FIR;
768
                                q0_MW <= q0_FIR;        q1_MW <= q1_FIR;        q2_MW <= q2_FIR;
769
                        end
770
 
771
        reg [2:0] bs_curr_MW;
772
        reg [5:0] DF_edge_counter_MW;
773
        reg [1:0] one_edge_counter_MW;
774
        always @ (posedge gclk_DF or negedge reset_n)
775
                if (reset_n == 1'b0)
776
                        begin
777
                                DF_edge_counter_MW <= 6'd48;    one_edge_counter_MW <= 2'd3;
778
                                p3_MW <= 0;                                              q3_MW <= 0;
779
                                bs_curr_MW <= 0;
780
                        end
781
                else
782
                        begin
783
                                DF_edge_counter_MW <= DF_edge_counter_FIR;              p3_MW <= p3_FIR;
784
                                one_edge_counter_MW <= one_edge_counter_FIR;    q3_MW <= q3_FIR;
785
                                bs_curr_MW <= bs_curr_FIR;
786
                        end
787
endmodule
788
 
789
module absolute (a,b,out);
790
        input [7:0] a,b;
791
        output [7:0] out;
792
 
793
        assign out = (a > b)? (a - b):(b - a);
794
endmodule
795
 
796
module clip_to_c (delta,c,out);
797
        input [8:0] delta;
798
        input [4:0] c;           // 0 ~ 25,       [4:0]
799
        output [5:0] out;        // -25 ~ 25, [5:0] 
800
        reg [5:0] out;
801
 
802
        wire [5:0] neg_c;        //-25 ~ 25,[5:0]
803
        assign neg_c = {1'b1,~c} + 1;
804
 
805
        always @ (delta or c or neg_c)
806
                if (delta[8] == 1'b0)   //delta is positive
807
                        out <= (delta[7:0] > {3'b0,c})? {1'b0,c}:delta[5:0];
808
                else                                    //delta is negtive
809
                        out <= (delta[7:0] < {2'b11,neg_c})? {1'b1,neg_c}:delta[5:0];
810
endmodule
811
 
812
module bs4_strong_FIR (p0,p1,p2,p3,q0,q1,q2,q3,p0_out,p1_out,p2_out,q0_out,q1_out,q2_out);
813
        input [7:0]  p0,p1,p2,p3,q0,q1,q2,q3;
814
        output [7:0] p0_out,p1_out,p2_out,q0_out,q1_out,q2_out;
815
 
816
        wire [8:0] sum_p2p3,sum_p1p2,sum_p0q0,sum_p1q1,sum_q1q2,sum_q2q3;
817
        assign sum_p2p3 = p2 + p3;
818
        assign sum_p1p2 = p1 + p2;
819
        assign sum_p0q0 = p0 + q0;
820
        assign sum_p1q1 = p1 + q1;
821
        assign sum_q1q2 = q1 + q2;
822
        assign sum_q2q3 = q2 + q3;
823
 
824
        wire [9:0] sum_p2p3_x2,sum_q2q3_x2;
825
        assign sum_p2p3_x2 = {sum_p2p3,1'b0};
826
        assign sum_q2q3_x2 = {sum_q2q3,1'b0};
827
 
828
        wire [9:0] sum_0,sum_1,sum_2;
829
        assign sum_0 = sum_p0q0 + sum_p1p2;
830
        assign sum_1 = sum_p0q0 + sum_p1q1;
831
        assign sum_2 = sum_p0q0 + sum_q1q2;
832
 
833
        wire [10:0] p0_tmp,p2_tmp,q0_tmp,q2_tmp;
834
        assign p0_tmp = sum_0 + sum_1;
835
        assign p2_tmp = sum_p2p3_x2 + sum_0;
836
        assign q0_tmp = sum_1 + sum_2;
837
        assign q2_tmp = sum_q2q3_x2 + sum_2;
838
 
839
        assign p0_out = (p0_tmp + 4) >> 3;
840
        assign p1_out = (sum_0  + 2) >> 2;
841
        assign p2_out = (p2_tmp + 4) >> 3;
842
        assign q0_out = (q0_tmp + 4) >> 3;
843
        assign q1_out = (sum_2  + 2) >> 2;
844
        assign q2_out = (q2_tmp + 4) >> 3;
845
endmodule
846
 
847
module bs4_weak_FIR (a,b,c,out);
848
        input [7:0] a,b,c;
849
        output [7:0] out;
850
 
851
        wire [8:0] a_x2;
852
        assign a_x2 = {a,1'b0};
853
 
854
        wire [8:0] sum_bc;
855
        assign sum_bc = b + c;
856
 
857
        wire [9:0] out_tmp;
858
        assign out_tmp = (a_x2 + sum_bc) + 2;
859
        assign out = out_tmp[9:2];
860
endmodule
861
 

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